# ########## RX1 STREAM ###########

# Set INT_RX_ENABLE bit high attached to delay enable with enableRiseToAnalogOnDelay
STREAM      0
# Set INT_RX_ENABLE high
WRMASK      ADDR_SPI_RX1_CORE_PROGRAMMABLE_DELAYED_ENABLE_REGISTERS_RX_INT_DELAY_ENABLE 02 02
RD          R0 ADDR_SPI_RXB1_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_4
CONDCALL    30                  # Call LDO Power Up stream
RD          R0 ADDR_SPI_RXB1_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_5
CONDCALL    31                  # Call PLL Power Up stream
$IfRx1IntLo$ RD R0 ADDR_SPI_RXB1_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_6
$IfRx1IntLo$ CONDCALL 02        # Call PLL retune Pre VCO cal stream
RETURN


# Set INT_RX_ENABLE bit low attached to delay enable with enableFallToOffDelay
STREAM      1
WRMASK      ADDR_SPI_RX1_CORE_PROGRAMMABLE_DELAYED_ENABLE_REGISTERS_RX_INT_DELAY_ENABLE 00 02
RETURN


# DMA Power up Config A (Pre-VCO Cal)
STREAM      2
# Reset status register
WR          ADDR_SPI_RXB1_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_17 00
# Write Byte 0 of starting Address
WR          ADDR_SPI_CORE_1_GENERAL_DMA_2_REGISTERS_GENERAL_DMA_2_START_TABLE_ADDR_BYTE0 90
# Enable DMA
WR          ADDR_SPI_CORE_1_GENERAL_DMA_2_REGISTERS_GENERAL_DMA_2_CONTROL0 01
# Write Next_RX bit
WRMASK      ADDR_SPI_CORE_1_GENERAL_DMA_2_REGISTERS_GENERAL_DMA_2_CONTROL1 02 02
# Wait for Completion
RDWAIT      ADDR_SPI_RXB1_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_17 07 07
# Disable DMA
WRMASK      ADDR_SPI_CORE_1_GENERAL_DMA_2_REGISTERS_GENERAL_DMA_2_CONTROL0 00 01
# Wait for PLL lock
WAIT        $Pll1LockWait$
RETURN


# DMA Power up Config B (Post-VCO Cal and PLL Path Config and Power Up)
STREAM      3
# Calculate byte 0 of DMA address. Checks HOP_1_TOGGLE_READBACK. If frequency hopping mode is disabled 
# this register always reads back as 0
LD          R1 01
# Default address of DMA table
LD          R2 94
LD          R3 04
RD          R0 ADDR_SPI_CORE_2_PROGRAMMABLE_DELAYED_ENABLE_REGISTERS_MAIN_HOP_TOGGLE_READBACK
AND         R0 R1
MUL         R0 R3
ADD         R0 R2       # R0 will be 94 (non-FH) or 98 (FH)
WRA         R0 ADDR_SPI_CORE_1_GENERAL_DMA_2_REGISTERS_GENERAL_DMA_2_START_TABLE_ADDR_BYTE0
# Reset status register
WR          ADDR_SPI_RXB1_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_17 00
# Enable DMA
WR          ADDR_SPI_CORE_1_GENERAL_DMA_2_REGISTERS_GENERAL_DMA_2_CONTROL0 01
# Write Next_RX bit
WRMASK      ADDR_SPI_CORE_1_GENERAL_DMA_2_REGISTERS_GENERAL_DMA_2_CONTROL1 02 02
# Wait for Completion
RDWAIT      ADDR_SPI_RXB1_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_17 07 07
# Disable DMA
WRMASK      ADDR_SPI_CORE_1_GENERAL_DMA_2_REGISTERS_GENERAL_DMA_2_CONTROL0 00 01
RETURN


# DMA Power Down Config (PLL path power down)    
STREAM      4
# Calculate byte 0 of DMA address. Checks HOP_1_TOGGLE_READBACK. If frequency hopping mode is disabled 
# this register always reads back as 0
LD          R1 01
# Default address of DMA table
LD          R2 9C
LD          R3 04
RD          R0 ADDR_SPI_CORE_2_PROGRAMMABLE_DELAYED_ENABLE_REGISTERS_MAIN_HOP_TOGGLE_READBACK
AND         R0 R1
MUL         R0 R3
ADD         R0 R2       # R0 will be 9C (non-FH) or A0 (FH)
WRA         R0 ADDR_SPI_CORE_1_GENERAL_DMA_2_REGISTERS_GENERAL_DMA_2_START_TABLE_ADDR_BYTE0
# Reset status register
WR          ADDR_SPI_RXB1_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_17 00
# Enable DMA
WR          ADDR_SPI_CORE_1_GENERAL_DMA_2_REGISTERS_GENERAL_DMA_2_CONTROL0 01
# Write Next_RX bit
WRMASK      ADDR_SPI_CORE_1_GENERAL_DMA_2_REGISTERS_GENERAL_DMA_2_CONTROL1 02 02
# Wait for Completion
RDWAIT      ADDR_SPI_RXB1_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_17 07 07
# Disable DMA
WRMASK      ADDR_SPI_CORE_1_GENERAL_DMA_2_REGISTERS_GENERAL_DMA_2_CONTROL0 00 01   
RETURN


# RX Hop Edge
STREAM      5
TIMEOUT     FFFF
############# Partial power down Rx each hop ############
# Mask ADC output
WRMASK      ADDR_SPI_RX1_CORE_RX_DATAPATH_CONFIG_RX_DATAPATH_FORCE_ZERO 01 01
# Power down RX LO mux buffer
WR          ADDR_SPI_CORE_1_ANALOG_REGISTERS_RX1_LO_REG 07
########################################################

# Disable RX algorithms
CALL        19
# Update NCO FTW (FTW is updated in FW. This should have no effect if there is no FTW programmed)
WRMASK      ADDR_SPI_RX1_CORE_RX_DATAPATH_CONFIG_RX_NCO_FTW_UPDATE_CONTROL 00 01
WRMASK      ADDR_SPI_RX1_CORE_RX_DATAPATH_CONFIG_RX_NCO_FTW_UPDATE_CONTROL 01 01
#########################################################

# SOFTWARE_SPARE_10: =0 in LO Mux FH modes (1 frame delay), =2 or 3 in LO Retune FH modes (0 frame delay).
# We can use bit 1 as LO Retune mode.
# Run this stream ONLY in FH LO Mux FH modes.
RD          R0 ADDR_SPI_RXB1_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_10
LD          R1 02
AND         R0 R1
# Trigger stream 0D "INT LOOPBACK RISE STREAM" in LO Retune mode
CONDCALL    38
XOR         R0 R1
CONDCALL    35
RETURN


# RX Hop Edge During RX High
STREAM      6
# Set Rx enable flag for next frame
WR          ADDR_SPI_RXB1_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_7 02
RETURN


# RX ENABLE RISE STREAM
STREAM      7
TIMEOUT     FFFF
# Bypass stream 00 in Frequency Hopping mode
RD          R0 ADDR_SPI_RXB1_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_13
LD          R1 01
XOR         R0 R1
CONDCALL    00              # Set INT_RX_ENABLE bit high
RETURN


# RX ENABLE RISE DURING HOP MODE STREAM
STREAM      8
RETURN


# RX ENABLE FALL STREAM
STREAM      9
# Assert SPI GPIO Bit 2 High
#WRMASK     ADDR_SPI_CORE_GPIO_1P8V_CONTROL_GPIO_1P8V_SPI_SOURCE_BYTE0 04 04
# Bypass stream 01 in Frequency Hopping mode
RD          R0 ADDR_SPI_RXB1_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_13
LD          R1 01
XOR         R0 R1
CONDCALL    01              # Set INT_RX_ENABLE bit low
RETURN


# RX ENABLE FALL DURING HOP MODE
STREAM      0A
RETURN


# ORX ENABLE RISE STREAM
STREAM      0B
TIMEOUT     FFFF
# Interrupt ARM: streamProc_orx1EnableRiseHandler()
# This interrupt allows the ARM to does some processing in parallel
INTERRUPT   04
# Set flag which is cleared by ARM
WR          ADDR_SPI_RXB1_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_15 FF
RETURN


# EXT LOOPBACK RISE STREAM
STREAM      0C
RETURN


# INT LOOPBACK RISE STREAM
STREAM      0D
TIMEOUT     FFFF
# Wait on semaphore from ARM to update resources in LO Retune FH modes if it's RX frame
RD          R0 ADDR_SPI_RXB1_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_7
CONDCALL    39

# RX Hop Edge in LO MUX FH mode
CALL        35
RETURN


# ORX ENABLE FALL STREAM
STREAM      0E
# Set flag which is cleared by ARM
WR          ADDR_SPI_RXB1_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_15 FF
# Interrupt ARM: streamProc_orx1EnableFallHandler()
INTERRUPT   08
# Disable ORx
WRMASK      ADDR_SPI_RX1_CORE_PROGRAMMABLE_DELAYED_ENABLE_REGISTERS_RX_INT_DELAY_ENABLE 00 01
RETURN


# EXT LOOPBACK FALL STREAM
STREAM      0F
RETURN


# INT LOOPBACK FALL STREAM
STREAM      10
RETURN


# RX_INT_DELAYED1_ENABLE RISE (SPI BIT) (Set RX LNA switch)
STREAM      11
RD          R0 ADDR_SPI_RXB1_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_8
LD          R1 01
AND         R0 R1
CONDCALL    33
RETURN


# INT_ORX_DELAYED_ENABLE RISE (SPI_BIT)
STREAM      12
TIMEOUT     FFFF

# Force maximum attenuation on ORX
$IfRx1A$    WRMASK ADDR_SPI_RX1_ANA_ORX_FE_REGISTERS_ORX2FE_LOCM   40 40
$IfRx1A$    WRMASK ADDR_SPI_RX1_ANA_ORX_FE_REGISTERS_ORX2FE_LOCM_B 40 40
$IfNoRx1A$  WRMASK ADDR_SPI_RX1_ANA_ORX_FE_REGISTERS_ORX1FE_LOCM   40 40
$IfNoRx1A$  WRMASK ADDR_SPI_RX1_ANA_ORX_FE_REGISTERS_ORX1FE_LOCM_B 40 40

# Start DMA for ORx datapath switch
# rx_SwitchDigitalDataPath() - DMA Switch Digital Data Path
# Reset status register
WR          ADDR_SPI_RXB1_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_17 00
# Write Byte 0 of starting Address
WR          ADDR_SPI_CORE_1_GENERAL_DMA_2_REGISTERS_GENERAL_DMA_2_START_TABLE_ADDR_BYTE0 88
# Enable DMA
WR          ADDR_SPI_CORE_1_GENERAL_DMA_2_REGISTERS_GENERAL_DMA_2_CONTROL0 01
# Write Next_RX bit
WRMASK      ADDR_SPI_CORE_1_GENERAL_DMA_2_REGISTERS_GENERAL_DMA_2_CONTROL1 02 02

# loGen_LoMapping() - Set LOMUX_RX1 to be the same as LOMUX_TX1 for ORX1
# This could be done in DMA. 
# The reason a spare register is used, rather than reading TX lo mux settings, 
# is that ORx enable may happen in parallel with Tx power up.
RD          R0 ADDR_SPI_RXB1_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_18
WRA         R0 ADDR_SPI_CORE_1_ANALOG_REGISTERS_RX1_SEL_LO2

# Setting ANALOG_REGISTERS_RX1_LO_REG in Rx only and FH mode
# SOFTWARE_SPARE_9 is either 00 (indicating LO1) or 1 (indicating LO2)
# For ORx power up, ANALOG_REGISTERS_RX1_LO_REG should either be 0x1 (LO1)
# or 0x2 (LO2).
# Adding 01 to SOFTWARE_SPARE_9 yields either 01 (LO1) or 02 (LO2).
# This approach is used in order to:
#     * Save two sub streams
#     * Save a SW spare register 
#     * Save ARM PM, DM, and CYCLES in order to maintain and update 
#       a DMA table in FH mode.
# This approach could be replaced with one of the above if a different solution is 
# desired.
LD          R1 01
ADD         R0 R1 
LD          R1 03
XOR         R0 R1
WRA         R0 ADDR_SPI_CORE_1_ANALOG_REGISTERS_RX1_LO_REG

### alg_channelProfileSwitch (ORX) - Configure ORX Algorithms
# Set radio states (BBDC, NBFIC, AGC, RFDC)
# WR          ADDR_SPI_RX1_CORE_CHANNEL_CONFIGURATION_RX_CHAN_FUNCS_RADIO_STATES 55
# RX TIA Fc and Fine Tune
WRMASK      ADDR_SPI_RX1_ANA_ORX_TIA_CONFIGURATION_REGISTERS_ORXTIA_TUNER_MODE 01 01
# Select TIA Profile
WRMASK      ADDR_SPI_RXB1_CORE_AGC_GENERAL_SETUP_REGISTERS_RX_TIA_PROFILE 02 07
# RX TIA Fc and Fine Tune
WRMASK      ADDR_SPI_RX1_ANA_ORX_TIA_CONFIGURATION_REGISTERS_ORXTIA_TUNER_MODE 00 01

##### QEC Mutual Exclusion #####
# Trigger main stream "PLL1 LOCK RISE"
WR          ADDR_SPI_CORE_2_BBIC_INTERFACE_REGISTERS_BBIC_PLL  00
WR          ADDR_SPI_CORE_2_BBIC_INTERFACE_REGISTERS_BBIC_PLL  01
RDWAIT      ADDR_SPI_CORE_2_PROGRAMMABLE_DELAYED_ENABLE_REGISTERS_MAIN_INT_DELAY_ENABLE_PED_START_DELAY0  01  01
# QEC Mutual Exclusion
WRMASK      ADDR_SPI_CORE_RADIO_CONTROL_REGISTERS_ENABLES_FOR_STREAMPROC_RX2  00  20
# Set RX QEC Profile
WRMASK      ADDR_SPI_CORE_RADIO_CONTROL_REGISTERS_ENABLES_FOR_STREAMPROC_RX1  02  07
# Release resource
WR          ADDR_SPI_CORE_2_PROGRAMMABLE_DELAYED_ENABLE_REGISTERS_MAIN_INT_DELAY_ENABLE_PED_START_DELAY0  00
##### QEC Mutual Exclusion #####

# NB FIC (NSS-1644)
WRMASK      ADDR_SPI_RX1_CORE_RX_NBFIC_REGISTERS_RX_NBF_OBS_CONTROL1 00 02
# Set AGC to manual
RD          R0 ADDR_SPI_RXB1_CORE_AGC_GENERAL_SETUP_REGISTERS_AGC_CONFIG
WRA         R0 ADDR_SPI_RXB1_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_16
WRMASK      ADDR_SPI_RXB1_CORE_AGC_GENERAL_SETUP_REGISTERS_AGC_CONFIG 00 03

# Power down phase sync detector.
WRMASK      ADDR_SPI_TX1_ANA_LO_MUX_CONTROL_LO_MUX_CONTROL 10 10

### RCVR_OrxPowerUp (ORX, orx_adcType)
# Enable the HP ADC and LP ADC clocks
WRMASK      ADDR_SPI_CORE_1_ANALOG_SPARE_REGISTERS_ANALOG_SPARE_REG_8 00 03
# Enable the Clock Gen Output Buffer
WR          ADDR_SPI_RX1_CORE_CHANNEL_CONFIGURATION_RX_CLOCK_CONFIG_0 01
# Enable positive and negatve phase of the data clock
WRMASK      ADDR_SPI_CORE_1_ANALOG_SPARE_REGISTERS_ANALOG_SPARE_REG_1 07 07
# Power up mixer
# ORx can be used only when port A/B switching is disabled, so we keep the
# compile time flag for the ORX
$IfRx1A$    CALL 1D             # Power up ORX1A FE == Power up RX1B FE
$IfNoRx1A$  CALL 1C             # Power up ORX1B FE == Power up RX1A FE

# Power up TIA
WR          ADDR_SPI_RX1_ANA_POWER_DOWN_REGISTERS_ORX_PD 00
# Read ADC_Switching flag
LD          R7 01               # Select ORX ADC Profile
RD          R0 ADDR_SPI_RXB1_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_9
CONDCALL    20                  # Power up HP ADC
# Toggle the value in R0
LD          R1 01
XOR         R0 R1
CONDCALL    21                  # else, Power up LP ADC
# ORx does not use dynamic PFIR switch and bank is set by DMA
## RD          R0 ADDR_SPI_RX1_CORE_RX_DATAPATH_CONFIG_RX_NBDEM_ENABLE_1
## WR          ADDR_SPI_RX1_CORE_RX_DATAPATH_CONFIG_RX_NBDEM_ENABLE_1 00
## RD          R1 ADDR_SPI_RXB1_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_3
## WRA         R1 ADDR_SPI_CORE_RX1_DATAPATH_CONFIG_CORE_RX1_PFIR_MODE_MAPPING
## WRA         R0 ADDR_SPI_RX1_CORE_RX_DATAPATH_CONFIG_RX_NBDEM_ENABLE_1
# Select PFIR Bank to BANK B (Fix for TNDD-450 is in FW. Stream needs it?)
WRMASK      ADDR_SPI_CORE_MAG_CONFIG_MAG_SEL0 10 30
# Enable QEC Clocks
#WRMASK     ADDR_SPI_CORE_2_CORE_RXQEC_REGISTERS_CORE_RXQEC_CONTROL0 40 40
RD          R0 ADDR_SPI_CORE_1_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_7
LD          R1 01
AND         R0 R1
XOR         R0 R1
LD          R7 40
CONDCALL    29

# Trigger main stream "PLL1 LOCK RISE"
WR          ADDR_SPI_CORE_2_BBIC_INTERFACE_REGISTERS_BBIC_PLL  00
WR          ADDR_SPI_CORE_2_BBIC_INTERFACE_REGISTERS_BBIC_PLL  01
RDWAIT      ADDR_SPI_CORE_2_PROGRAMMABLE_DELAYED_ENABLE_REGISTERS_MAIN_INT_DELAY_ENABLE_PED_START_DELAY0  01  01
# QEC Reset
WRMASK      ADDR_SPI_CORE_RX_QEC_REGISTERS_RXQEC_SW_RESET 01 01
WRMASK      ADDR_SPI_CORE_RX_QEC_REGISTERS_RXQEC_SW_RESET 00 01
# Release resource
WR          ADDR_SPI_CORE_2_PROGRAMMABLE_DELAYED_ENABLE_REGISTERS_MAIN_INT_DELAY_ENABLE_PED_START_DELAY0  00

# Power up RX mixer LO buffer
# ORx can be used only when port A/B switching is disabled, so we keep the
# compile time flag for the ORX
$IfRx1A$    WR ADDR_SPI_RX1_ANA_POWER_DOWN_REGISTERS_ORX2_PD 00     # Power up ORX1A == Power up RX1B
$IfNoRx1A$  WR ADDR_SPI_RX1_ANA_POWER_DOWN_REGISTERS_ORX1_PD 00     # Power up ORX1B == Power up RX1A

# Check if DMA has completed 
# Wait for Completion
RDWAIT      ADDR_SPI_CORE_1_GENERAL_DMA_2_REGISTERS_GENERAL_DMA_2_STATUS_FLAGS 07 07
# Disable DMA
WRMASK      ADDR_SPI_CORE_1_GENERAL_DMA_2_REGISTERS_GENERAL_DMA_2_CONTROL0 00 01   

# Poll registers to see if ARM has completed it's tasks
RDWAIT      ADDR_SPI_RXB1_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_15 00 FF

# Disable forcing maximum attenuation on ORX
$IfRx1A$    WRMASK ADDR_SPI_RX1_ANA_ORX_FE_REGISTERS_ORX2FE_LOCM   00 40
$IfRx1A$    WRMASK ADDR_SPI_RX1_ANA_ORX_FE_REGISTERS_ORX2FE_LOCM_B 00 40
$IfNoRx1A$  WRMASK ADDR_SPI_RX1_ANA_ORX_FE_REGISTERS_ORX1FE_LOCM   00 40
$IfNoRx1A$  WRMASK ADDR_SPI_RX1_ANA_ORX_FE_REGISTERS_ORX1FE_LOCM_B 00 40

# Unmask data to datapath
WR          ADDR_SPI_RX1_CORE_RX_DATAPATH_CONFIG_RX_DATAPATH_FORCE_ZERO 10

### alg_channelProfileEnable (ORX)
WR         ADDR_SPI_RX1_CORE_PROGRAMMABLE_DELAYED_ENABLE_REGISTERS_HW_DELAY_ENABLE_0  00
WR          ADDR_SPI_RX1_CORE_PROGRAMMABLE_DELAYED_ENABLE_REGISTERS_HW_DELAY_ENABLE_1 00
# Unmask BBDC 
WR         ADDR_SPI_RXB1_CORE_DIGITAL_DC_OFFSET_CONTROL_REGISTERS_DIGITAL_DC_OFFSET_DECIMATE 01 
# Disable and re-enable BBDC
# WRMASK      ADDR_SPI_RX1_CORE_PROGRAMMABLE_DELAYED_ENABLE_REGISTERS_HW_DELAY_ENABLE_1 00 08
WRMASK      ADDR_SPI_RX1_CORE_PROGRAMMABLE_DELAYED_ENABLE_REGISTERS_HW_DELAY_ENABLE_1 08 08
# Enable ORX QEC
WRMASK      ADDR_SPI_RX1_CORE_PROGRAMMABLE_DELAYED_ENABLE_REGISTERS_HW_DELAY_ENABLE_0 04 04
# Enable FIC if spare_2 is set 
RD          R0 ADDR_SPI_RXB1_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_2
# Spare 2 will have bit 0 set if ORx NBFIC is enabled.
# Clear all bits except bit 0 in R0 and shift it left by 1 to match bit position of 
# NBFIC enable in HW_DELAYE_ENABLE_0 
LD          R1 01 
AND         R0 R1
SHIFT       R0 01       # Left shift 1
# Read/Modify/Write HW_DELAY_ENABLE_0
RD          R1 ADDR_SPI_RX1_CORE_PROGRAMMABLE_DELAYED_ENABLE_REGISTERS_HW_DELAY_ENABLE_0
OR          R0 R1
WRA         R0 ADDR_SPI_RX1_CORE_PROGRAMMABLE_DELAYED_ENABLE_REGISTERS_HW_DELAY_ENABLE_0
# RFDC is NOT enabled for ORx
# WRMASK      ADDR_SPI_RX1_CORE_PROGRAMMABLE_DELAYED_ENABLE_REGISTERS_HW_DELAY_ENABLE_1 04 04
WRMASK      ADDR_SPI_RX1_CORE_PROGRAMMABLE_DELAYED_ENABLE_REGISTERS_HW_DELAY_ENABLE_1 02 02
# Open SSI 
WR          ADDR_SPI_RX1_CORE_RX_DATAPATH_CONFIG_RX_DATAPATH_FORCE_ZERO 00

# Reset all SCIC filters
WRMASK      ADDR_SPI_RX1_CORE_RX_NBFIC_REGISTERS_RX_ALG_NBFIC_OBS_SCIC_RESET 01 01
WRMASK      ADDR_SPI_RX1_CORE_RX_NBFIC_REGISTERS_RX_ALG_NBFIC_OBS_SCIC_RESET 00 01
# Force digital gain strobe ((WORKAROUND_TNDD_581))
WRMASK      ADDR_SPI_RX1_CORE_RX_DIGITAL_GAIN_REGISTERS_GAIN_COMPENATION_AND_SLICER_CONFIG 40 40
RETURN


# RX_INT_DELAYED0_ENABLE RISE (SPI BIT)
STREAM      13
# Unmask datapath from interface
WR          ADDR_SPI_RX1_CORE_RX_DATAPATH_CONFIG_RX_DATAPATH_FORCE_ZERO 00
# Reset SCIC (ADRV9003-1374)
WRMASK      ADDR_SPI_RX1_CORE_RX_NBFIC_REGISTERS_RX_ALG_NBFIC_OBS_SCIC_RESET 01 01
WRMASK      ADDR_SPI_RX1_CORE_RX_NBFIC_REGISTERS_RX_ALG_NBFIC_OBS_SCIC_RESET 00 01
# Force digital gain strobe ((WORKAROUND_TNDD_581))
WRMASK      ADDR_SPI_RX1_CORE_RX_DIGITAL_GAIN_REGISTERS_GAIN_COMPENATION_AND_SLICER_CONFIG 40 40
CALL        25              # Enable algorithms
# Interrupt ARM: streamProc_rx1EnableRiseHandler()
INTERRUPT   01
RETURN


#INT_RX_DELAYED_ENABLE RISE (SPI BIT)
STREAM      14
TIMEOUT     FFFF
# Set bit int_delay_1_enable attached to delay enable with rxEnableRiseToOnDelay - rxEnableRiseToAnaOnDelay
WRMASK      ADDR_SPI_RX1_CORE_PROGRAMMABLE_DELAYED_ENABLE_REGISTERS_RX_INT_DELAY_ENABLE 08 08
#INTERRUPT   10
############# Power on LVDS pads ############
RD          R0 ADDR_SPI_RXB1_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_11
LD          R1 01
AND         R0 R1
CONDCALL    2E
#############################################
$IfRx1IntLo$ RD R0 ADDR_SPI_RXB1_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_1
$IfRx1IntLo$ CONDCALL 34        # Call PLL retune Pre VCO cal stream
# CALL        03                  # Call PLL Post VCO cal stream, LO mux, LO gen, LO path power up
# Enable magnitude compensation PFIR if it is enabled in device profile
RD          R0 ADDR_SPI_RXB1_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_0
CONDCALL    3A

# Enable the HP ADC and LP ADC clocks
WRMASK      ADDR_SPI_CORE_1_ANALOG_SPARE_REGISTERS_ANALOG_SPARE_REG_8 00 03
# Enable the Clock Gen Output Buffer
WR          ADDR_SPI_RX1_CORE_CHANNEL_CONFIGURATION_RX_CLOCK_CONFIG_0 01
# Enable positive and negatve phase of the data clock
WRMASK      ADDR_SPI_CORE_1_ANALOG_SPARE_REGISTERS_ANALOG_SPARE_REG_1 07 07
############# Power on RX FE ############
RD          R0 ADDR_SPI_RXB1_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_19
LD          R1 01               # Bit 0 is next frame port, 0: Port A, 1: Port B
AND         R0 R1               # If Bit 0 is 1
CONDCALL    1D                  # Power up RX1 Port B
# stream 1D does not use any R registers
SUB         R0 R1               # else
CONDCALL    1C                  # Power up RX1 Port A
#############################################
# Power up TIA
WR          ADDR_SPI_RX1_ANA_POWER_DOWN_REGISTERS_ORX_PD 00
# Enable datapath clocks
WR          ADDR_SPI_RX1_CORE_RX_DATAPATH_CONFIG_ALL_RX_ENABLE 01
# Read ADC_Switching flag
LD          R7 00               # Select RX ADC Profile
RD          R0 ADDR_SPI_RXB1_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_9
CONDCALL    20                  # Power up HP ADC
# Toggle the value in R0
LD          R1 01
XOR         R0 R1
CONDCALL    21                  # else, Power up LP ADC

# Trigger main stream "PLL1 LOCK RISE"
WR          ADDR_SPI_CORE_2_BBIC_INTERFACE_REGISTERS_BBIC_PLL  00
WR          ADDR_SPI_CORE_2_BBIC_INTERFACE_REGISTERS_BBIC_PLL  01
RDWAIT      ADDR_SPI_CORE_2_PROGRAMMABLE_DELAYED_ENABLE_REGISTERS_MAIN_INT_DELAY_ENABLE_PED_START_DELAY0  01  01
# Select PFIR Bank to BANK A
WRMASK      ADDR_SPI_CORE_MAG_CONFIG_MAG_SEL0 00 30
# Release resource
WR          ADDR_SPI_CORE_2_PROGRAMMABLE_DELAYED_ENABLE_REGISTERS_MAIN_INT_DELAY_ENABLE_PED_START_DELAY0  00

# Read PFIR Bank in use (could change dynamically) and select bank appropriately
RD          R1 ADDR_SPI_RXB1_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_3
WRA         R1 ADDR_SPI_CORE_RX1_DATAPATH_CONFIG_CORE_RX1_PFIR_MODE_MAPPING
#Enable QEC Clocks
#WRMASK     ADDR_SPI_CORE_2_CORE_RXQEC_REGISTERS_CORE_RXQEC_CONTROL0 40 40
RD          R0 ADDR_SPI_CORE_1_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_7
LD          R1 01
AND         R0 R1
XOR         R0 R1
LD          R7 40
CONDCALL    29

# Select RX datapath  Profile (Set all bits to Rx)
WRMASK      ADDR_SPI_RX1_CORE_RX_DATAPATH_CONFIG_ORX_PROFILE_SEL 00 FF
############# Power on RX mixer LO buffer ############
RD          R0 ADDR_SPI_RXB1_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_19
LD          R1 01               # Bit 0 is next frame port, 0: Port A, 1: Port B
AND         R0 R1               # If Bit 0 is 1
CONDCALL    1B                  # Power up RX1 Port B LO buffer
# stream 1B does not use R registers
SUB         R0 R1               # else
CONDCALL    1A                  # Power up RX1 Port A LO buffer
#############################################
# Trigger main stream "PLL1 LOCK RISE"
WR          ADDR_SPI_CORE_2_BBIC_INTERFACE_REGISTERS_BBIC_PLL  00
WR          ADDR_SPI_CORE_2_BBIC_INTERFACE_REGISTERS_BBIC_PLL  01
RDWAIT      ADDR_SPI_CORE_2_PROGRAMMABLE_DELAYED_ENABLE_REGISTERS_MAIN_INT_DELAY_ENABLE_PED_START_DELAY0  01  01
# Flush datapath filters inside RXQEC block
WRMASK      ADDR_SPI_CORE_RX_QEC_REGISTERS_RXQEC_SW_RESET 01 01
WRMASK      ADDR_SPI_CORE_RX_QEC_REGISTERS_RXQEC_SW_RESET 00 01
# Release resource
WR          ADDR_SPI_CORE_2_PROGRAMMABLE_DELAYED_ENABLE_REGISTERS_MAIN_INT_DELAY_ENABLE_PED_START_DELAY0  00

CALL        03                  # Call PLL Post VCO cal stream, LO mux, LO gen, LO path power up
$IfRx1IntLo$ RD  R0 ADDR_SPI_RXB1_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_1
$IfRx1IntLo$ LD  R1 01
$IfRx1IntLo$ AND R0 R1
$IfRx1IntLo$ CONDCALL 28        # Handle PLL phase sync

# Wait for analog to settle
WAIT        $Delay_80ns$
WAIT        $Delay_80ns$
WAIT        $Delay_80ns$
CALL        24                  # Configure algorithms
# Set bit int_delay_0_enable
WRMASK      ADDR_SPI_RX1_CORE_PROGRAMMABLE_DELAYED_ENABLE_REGISTERS_RX_INT_DELAY_ENABLE 04 04
# Unmask datapath from ADC
WR          ADDR_SPI_RX1_CORE_RX_DATAPATH_CONFIG_RX_DATAPATH_FORCE_ZERO 10
# Set GPIO to high for debug if feature is enabled
RD          R0 ADDR_SPI_CORE_1_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_2
CONDCALL    2C
RETURN


#INT_RX_DELAYED_ENABLE FALL (SPI BIT)
STREAM      15
TIMEOUT     FFFF
# Assert SPI GPIO Bit 2 Low
#WRMASK     ADDR_SPI_CORE_GPIO_1P8V_CONTROL_GPIO_1P8V_SPI_SOURCE_BYTE0 00 04
# Reset bit int_delay_0_enable and int_delay_1_enable
WRMASK      ADDR_SPI_RX1_CORE_PROGRAMMABLE_DELAYED_ENABLE_REGISTERS_RX_INT_DELAY_ENABLE 00 0C
#INTERRUPT   20
# Mask ADC from datapath
WR          ADDR_SPI_RX1_CORE_RX_DATAPATH_CONFIG_RX_DATAPATH_FORCE_ZERO 01
CALL        19                  # Disable RX algorithms
# Read ADC_Switching flag
RD          R0 ADDR_SPI_RXB1_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_9
CONDCALL    22                  # Power down HP ADC
# Toggle the value in R0
RD          R0 ADDR_SPI_RXB1_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_9
LD          R1 01
XOR         R0 R1
CONDCALL    23                  # else, Power down LP ADC 
############# Power down RX FE ############
RD          R0 ADDR_SPI_RXB1_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_19
LD          R1 02               # Bit 1 is current frame port, 0: Port A, 1: Port B
AND         R0 R1               # If Bit 1 is 1
# stream 1F does not use R registers
CONDCALL    1F                  # Power down RX1 Port B
SUB         R0 R1               # else
CONDCALL    1E                  # Power down RX1 Port A
#############################################
# Power down TIA
WR          ADDR_SPI_RX1_ANA_POWER_DOWN_REGISTERS_ORX_PD 07
#Disable RX QEC clocks
#WRMASK     ADDR_SPI_CORE_2_CORE_RXQEC_REGISTERS_CORE_RXQEC_CONTROL0 00 40
RD          R0 ADDR_SPI_CORE_1_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_7
LD          R1 01
AND         R0 R1
XOR         R0 R1
LD          R7 00
CONDCALL    29
# Disable the HP ADC and LPADC clocks
WRMASK      ADDR_SPI_CORE_1_ANALOG_SPARE_REGISTERS_ANALOG_SPARE_REG_8 03 03
# Disable the Clock Gen Output Buffer
WR          ADDR_SPI_RX1_CORE_CHANNEL_CONFIGURATION_RX_CLOCK_CONFIG_0 00
# Disable positive and negative phase of the data clock
WRMASK      ADDR_SPI_CORE_1_ANALOG_SPARE_REGISTERS_ANALOG_SPARE_REG_1 00 07 
CALL        04                  # DMA Power Down PLL path
# Disable magnitude compensation PFIR if it is enabled in device profile
RD          R0 ADDR_SPI_RXB1_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_0
CONDCALL    3B
# Set GPIO to low for debug if feature is enabled
RD          R0 ADDR_SPI_CORE_1_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_2
CONDCALL    2B
RETURN 


# INT_ORX_DELAYED_ENABLE FALL (SPI BIT)
STREAM      16
TIMEOUT     FFFF
# Mask ADC from datapath
WR          ADDR_SPI_RX1_CORE_RX_DATAPATH_CONFIG_RX_DATAPATH_FORCE_ZERO 01
# Disable algorithms
CALL        19

# Force maximum attenuation on ORX
$IfRx1A$    WRMASK ADDR_SPI_RX1_ANA_ORX_FE_REGISTERS_ORX2FE_LOCM   40 40
$IfRx1A$    WRMASK ADDR_SPI_RX1_ANA_ORX_FE_REGISTERS_ORX2FE_LOCM_B 40 40
$IfNoRx1A$  WRMASK ADDR_SPI_RX1_ANA_ORX_FE_REGISTERS_ORX1FE_LOCM   40 40
$IfNoRx1A$  WRMASK ADDR_SPI_RX1_ANA_ORX_FE_REGISTERS_ORX1FE_LOCM_B 40 40

# Start DMA for switch back to default Rx datapath
# Reset status register
WR          ADDR_SPI_RXB1_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_17 00
# Write Byte 0 of starting Address
WR          ADDR_SPI_CORE_1_GENERAL_DMA_2_REGISTERS_GENERAL_DMA_2_START_TABLE_ADDR_BYTE0 80 # Get appropriate starting addr
# Enable DMA
WR          ADDR_SPI_CORE_1_GENERAL_DMA_2_REGISTERS_GENERAL_DMA_2_CONTROL0 01
# Write Next_RX bit
WRMASK      ADDR_SPI_CORE_1_GENERAL_DMA_2_REGISTERS_GENERAL_DMA_2_CONTROL1 02 02
# Disable LO mux 
WR          ADDR_SPI_CORE_1_ANALOG_REGISTERS_RX1_LO_REG 07
### RCVR_OrxPowerDown (ORX, orx_adcType)
# Read ADC_Switching flag
RD          R0 ADDR_SPI_RXB1_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_9
CONDCALL    22                  # Power down HP ADC
# Toggle the value in R0
LD          R1 01
XOR         R0 R1
CONDCALL    23                  # else, Power down LP ADC 
# ORx can be used only when port A/B switching is disabled, so we keep the
# compile time flag for the ORX
$IfRx1A$    CALL 1F             # If Rx=Rx1A, power down Rx1B
$IfNoRx1A$  CALL 1E             # If Rx=Rx1B, power down Rx1A
# Power down TIA
WR          ADDR_SPI_RX1_ANA_POWER_DOWN_REGISTERS_ORX_PD 07
#Disable RX QEC clocks
#WRMASK     ADDR_SPI_CORE_2_CORE_RXQEC_REGISTERS_CORE_RXQEC_CONTROL0 00 40
RD          R0 ADDR_SPI_CORE_1_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_7
LD          R1 01
AND         R0 R1
XOR         R0 R1
LD          R7 00
CONDCALL    29
# Disable the HP ADC and LP ADC clocks
WRMASK      ADDR_SPI_CORE_1_ANALOG_SPARE_REGISTERS_ANALOG_SPARE_REG_8 03 03
# Disable the Clock Gen Output Buffer
WR          ADDR_SPI_RX1_CORE_CHANNEL_CONFIGURATION_RX_CLOCK_CONFIG_0 00
# Disable positive and negative phase of the data clock
WRMASK      ADDR_SPI_CORE_1_ANALOG_SPARE_REGISTERS_ANALOG_SPARE_REG_1 00 07 
# Mask datapath from interface
WR          ADDR_SPI_RX1_CORE_RX_DATAPATH_CONFIG_RX_DATAPATH_FORCE_ZERO 11

# Check if DMA has completed 
# Wait for Completion
RDWAIT      ADDR_SPI_CORE_1_GENERAL_DMA_2_REGISTERS_GENERAL_DMA_2_STATUS_FLAGS 07 07
# Disable DMA
WRMASK      ADDR_SPI_CORE_1_GENERAL_DMA_2_REGISTERS_GENERAL_DMA_2_CONTROL0 00 01   

# Restore AGC
RD          R0 ADDR_SPI_RXB1_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_16
WRA         R0 ADDR_SPI_RXB1_CORE_AGC_GENERAL_SETUP_REGISTERS_AGC_CONFIG
# Poll registers to see if ARM has completed it's tasks
RDWAIT      ADDR_SPI_RXB1_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_15 00 FF
# Toggle Global Reset
WRMASK      ADDR_SPI_RX1_CORE_ORX1_CONFIG_ORX1_DP_RESET 01 01
WRMASK      ADDR_SPI_RX1_CORE_ORX1_CONFIG_ORX1_DP_RESET 00 01
# Disable RX datapath clock
WR          ADDR_SPI_RX1_CORE_RX_DATAPATH_CONFIG_ALL_RX_ENABLE 00
RETURN


# RX_INT_DELAYED0_ENABLE FALL (SPI_BIT)
STREAM      17
TIMEOUT     FFFF
# Mask datapath from interface
WR          ADDR_SPI_RX1_CORE_RX_DATAPATH_CONFIG_RX_DATAPATH_FORCE_ZERO 11
# Toggle Global Reset -- Removed for NSS-4025
# WRMASK      ADDR_SPI_RX1_CORE_RX_DATAPATH_CONFIG_RX_DP_RESET 01 01
# WRMASK      ADDR_SPI_RX1_CORE_RX_DATAPATH_CONFIG_RX_DP_RESET 00 01
# Disable RX datapath clock
WR          ADDR_SPI_RX1_CORE_RX_DATAPATH_CONFIG_ALL_RX_ENABLE 00
############ Power off LVDS pads ############
RD          R0 ADDR_SPI_RXB1_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_11
LD          R1 01
AND         R0 R1
CONDCALL    2D
#############################################
# Interrupt ARM: streamProc_rx1EnableFallHandler()
INTERRUPT   02
$IfRx1PortImpedanceControl$ CALL        36
RETURN


# RX_INT_DELAYED1_ENABLE FALL (SPI_BIT) (Reset RX LNA switch)
STREAM      18
RD          R0 ADDR_SPI_RXB1_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_8
LD          R1 01
AND         R0 R1
CONDCALL    32
RETURN   


# Disable RX Algorithms
STREAM      19
# Mask BBDC
WR          ADDR_SPI_RXB1_CORE_DIGITAL_DC_OFFSET_CONTROL_REGISTERS_DIGITAL_DC_OFFSET_DECIMATE 21 
# Disable BBDC, RFDC, AGC, RSSI  
WR          ADDR_SPI_RX1_CORE_PROGRAMMABLE_DELAYED_ENABLE_REGISTERS_HW_DELAY_ENABLE_1 00
# Disable RXQEC_OBS, FIC_OBS, HD2_OBS
WR          ADDR_SPI_RX1_CORE_PROGRAMMABLE_DELAYED_ENABLE_REGISTERS_HW_DELAY_ENABLE_0 00
RETURN


# Power up RX1A mixer LO buffer
STREAM      1A
WR          ADDR_SPI_RX1_ANA_POWER_DOWN_REGISTERS_ORX1_PD 00
# Set current port to port A
WRMASK     ADDR_SPI_RXB1_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_19 00 04
RETURN


# Power up RX1B mixer LO buffer
STREAM      1B
WR          ADDR_SPI_RX1_ANA_POWER_DOWN_REGISTERS_ORX2_PD 00
# Set current port to port B
WRMASK     ADDR_SPI_RXB1_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_19 04 04
RETURN


# Power up RX1A
STREAM      1C
# Power down ORX, ILB mixers
WR          ADDR_SPI_RX1_ANA_POWER_DOWN_REGISTERS_ORX2_PD 07
WR          ADDR_SPI_RX1_ANA_POWER_DOWN_REGISTERS_LB1_PD  07
# Select RX mixer
WR          ADDR_SPI_RX1_ANA_ORX_FE_REGISTERS_ORX_BB_MUX  02
# Power up LO Delay
WRMASK      ADDR_SPI_RX1_ANA_LO_DELAY_REGISTERS_ORX1_LO_DELAY_CORR_CONTROL_1 00 10
# Power up RX mixer
WR          ADDR_SPI_RX1_ANA_POWER_DOWN_REGISTERS_ORX1_PD 02
RETURN


# Power up RX1B
STREAM      1D
# Power down ORX, ILB mixers
WR          ADDR_SPI_RX1_ANA_POWER_DOWN_REGISTERS_ORX1_PD 07
WR          ADDR_SPI_RX1_ANA_POWER_DOWN_REGISTERS_LB1_PD  07
# Select RX mixer
WR          ADDR_SPI_RX1_ANA_ORX_FE_REGISTERS_ORX_BB_MUX  01
# Power up LO Delay
WRMASK      ADDR_SPI_RX1_ANA_LO_DELAY_REGISTERS_ORX2_LO_DELAY_CORR_CONTROL_1 00 10
# Power up RX mixer
WR          ADDR_SPI_RX1_ANA_POWER_DOWN_REGISTERS_ORX2_PD 02
RETURN  


# Power down RX1A
STREAM      1E
# Power down LO buffer
WR          ADDR_SPI_RX1_ANA_POWER_DOWN_REGISTERS_ORX1_PD 02
# Power down LO Delay
WRMASK      ADDR_SPI_RX1_ANA_LO_DELAY_REGISTERS_ORX1_LO_DELAY_CORR_CONTROL_1 10 10
# Power down FE and Capdac	
WR          ADDR_SPI_RX1_ANA_POWER_DOWN_REGISTERS_ORX1_PD 07
# Power down RX mux
WR          ADDR_SPI_RX1_ANA_ORX_FE_REGISTERS_ORX_BB_MUX 03   
RETURN


# Power down RX1B
STREAM      1F
# Power down LO buffer
WR          ADDR_SPI_RX1_ANA_POWER_DOWN_REGISTERS_ORX2_PD 02
# Power down LO Delay
WRMASK      ADDR_SPI_RX1_ANA_LO_DELAY_REGISTERS_ORX2_LO_DELAY_CORR_CONTROL_1 10 10
# Power down FE and Capdac	
WR          ADDR_SPI_RX1_ANA_POWER_DOWN_REGISTERS_ORX2_PD 07
# Power down RX mux
WR          ADDR_SPI_RX1_ANA_ORX_FE_REGISTERS_ORX_BB_MUX 03   
RETURN


# Power up HP ADC (R7(ADC Profile): 0-RX; 1-ORX; 2-ILB; 3-ELB)
STREAM      20
# Disable the LP ADC clock
WRMASK      ADDR_SPI_CORE_1_ANALOG_SPARE_REGISTERS_ANALOG_SPARE_REG_8 02 02
# Enable ADC Startup Reset before Power Up
WRMASK      ADDR_SPI_RX1_CORE_RX_OVERLOAD_RESET_DETECTION_REGISTERS_RX_ADC_OVERLOAD_RESET_THRESHOLD 00 80
# Assert adc_rst_dc, adc_dac_bypass_rf and de-assert adc_pd_dacs-delay, adc_pd_bias
WR          ADDR_SPI_RX1_ADC_REGMAP1_ADC_PD 60
# Wait for 1us
WAIT        $Delay_1us$
# Assert adc_rst_dc, adc_dac_bypass_rf, adc_pd_dacs_delay, adc_pd_bias
WR          ADDR_SPI_RX1_ADC_REGMAP1_ADC_PD 00
# Release ADC Startup 
WRMASK      ADDR_SPI_RX1_CORE_RX_OVERLOAD_RESET_DETECTION_REGISTERS_RX_ADC_OVERLOAD_RESET_THRESHOLD 80 80 
# Select ADC Profile (HP ADC)
WRA         R7 ADDR_SPI_RX1_CORE_CHANNEL_CONFIGURATION_RX_ADC_PROFILE
RETURN


# Power up LP ADC
STREAM      21
# Disable the HP ADC clock
WRMASK      ADDR_SPI_CORE_1_ANALOG_SPARE_REGISTERS_ANALOG_SPARE_REG_8 01 01
# Enable ana and dig cal blocks, adc bias block, channel I&Q ADC clocks channel I&Q analog front end 
WR          ADDR_SPI_RX1_ADC_LP_VCOADC_ANA_POWER_DOWN_REG DF
# Wait for 4 us
WAIT        $Delay_1us$
WAIT        $Delay_1us$
WAIT        $Delay_1us$
WAIT        $Delay_1us$
# Enable clock for VCO ADC digital
WRMASK      ADDR_SPI_RX1_ADC_LP_VCOADC_DIG_CAL_EN 80 80
RETURN


# Power down HP ADC
STREAM      22
##force ADC Reset
WRMASK      ADDR_SPI_RX1_CORE_RX_OVERLOAD_RESET_DETECTION_REGISTERS_RX_ADC_OVERLOAD_RESET_SIZE 80 80
## Toggle adc_flash_reset_mode
RD          R0 ADDR_SPI_RX1_ADC_REGMAP1_ADC_FLASH_CAL_CTRL
LD          R1 10
XOR         R0 R1
WRA         R0 ADDR_SPI_RX1_ADC_REGMAP1_ADC_FLASH_CAL_CTRL
WRA         R0 ADDR_SPI_RX1_ADC_REGMAP1_ADC_FLASH_CAL_CTRL      # This seems to be redundent
# wait 10 cycles with ARM @184.32MHz or ~52ns as per Rama's stream low simulation. Reuse Delay_80ns tag to wait a little longer.
WAIT        $Delay_80ns$
# Release ADC reset
WRMASK      ADDR_SPI_RX1_CORE_RX_OVERLOAD_RESET_DETECTION_REGISTERS_RX_ADC_OVERLOAD_RESET_THRESHOLD 80 80
# Power down HP ADC
WR          ADDR_SPI_RX1_ADC_REGMAP1_ADC_PD 7F
# Clear Force ADC reset
WRMASK      ADDR_SPI_RX1_CORE_RX_OVERLOAD_RESET_DETECTION_REGISTERS_RX_ADC_OVERLOAD_RESET_SIZE 00 80
RETURN 


# Power Down LP ADC
STREAM      23
# Disable ana and dig cal blocks, adc bias block, channel I&Q ADC clocks channel I&Q analog front end 
WR          ADDR_SPI_RX1_ADC_LP_VCOADC_ANA_POWER_DOWN_REG 00
# Disable clock for VCO ADC digital
WRMASK      ADDR_SPI_RX1_ADC_LP_VCOADC_DIG_CAL_EN 00 80    
RETURN


# Configure RX Algorithms
STREAM      24
#####Configure Algorithms#######
# Set radio states (BBDC, NBFIC, AGC, RFDC)
WR          ADDR_SPI_RX1_CORE_CHANNEL_CONFIGURATION_RX_CHAN_FUNCS_RADIO_STATES 00
# RX TIA Fc and Fine Tune
WRMASK      ADDR_SPI_RX1_ANA_ORX_TIA_CONFIGURATION_REGISTERS_ORXTIA_TUNER_MODE 01 01
# Set TIA Profile (NSS-1963)
RD          R0 ADDR_SPI_RXB1_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_19
SHIFT       R0 FC  # right shift 4. Bit 4-5 is TIA profile
LD          R1 07
AND         R0 R1
R2          = R0
RD          R0 ADDR_SPI_RXB1_CORE_AGC_GENERAL_SETUP_REGISTERS_RX_TIA_PROFILE
LD          R1 F8
AND         R0 R1
OR          R0 R2
WRA         R0 ADDR_SPI_RXB1_CORE_AGC_GENERAL_SETUP_REGISTERS_RX_TIA_PROFILE
# RX TIA Fc and Fine Tune
WRMASK      ADDR_SPI_RX1_ANA_ORX_TIA_CONFIGURATION_REGISTERS_ORXTIA_TUNER_MODE 00 01

##### QEC Mutual Exclusion #####
# Mapping of the RXQEC profile. 
# QEC profile  | chan profile (A/B switch disabled) | chan profile (A/B switch enabled)
# 1   001'b    | LP/HP RX                           | LP/HP RX Port A
# 2   010'b    | ORX                                | Not used
# 4   100'b    | ILB                                | ILB
# 0   000'b    | ELB                                | LP/HP RX Port B
# Bit 5 of spare reg 19 is 0 if port switch is disabled
# Bit 5 of spare reg 19 is 0 for port A and 1 for port B if port switch is enabled

# Trigger main stream "PLL1 LOCK RISE"
WR          ADDR_SPI_CORE_2_BBIC_INTERFACE_REGISTERS_BBIC_PLL  00
WR          ADDR_SPI_CORE_2_BBIC_INTERFACE_REGISTERS_BBIC_PLL  01
RDWAIT      ADDR_SPI_CORE_2_PROGRAMMABLE_DELAYED_ENABLE_REGISTERS_MAIN_INT_DELAY_ENABLE_PED_START_DELAY0  01  01
# QEC Mutual Exclusion
WRMASK      ADDR_SPI_CORE_RADIO_CONTROL_REGISTERS_ENABLES_FOR_STREAMPROC_RX2  00  20
# Set RX QEC Profile
RD          R0 ADDR_SPI_RXB1_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_19
SHIFT       R0 FB           # right shift 5 bits
R2          = R0
LD          R0 01           # bit 5 is never used so it's always 0
SUB         R0 R2           # QEC profile = 1 - portType
WRA         R0 ADDR_SPI_CORE_RADIO_CONTROL_REGISTERS_ENABLES_FOR_STREAMPROC_RX1
# Release resource
WR          ADDR_SPI_CORE_2_PROGRAMMABLE_DELAYED_ENABLE_REGISTERS_MAIN_INT_DELAY_ENABLE_PED_START_DELAY0  00
##### QEC Mutual Exclusion #####

# NB FIC
#WRMASK     ADDR_SPI_RX1_CORE_RX_NBFIC_REGISTERS_RX_NBF_OBS_CONTROL1 02 02
# Use spare register 2 bit1 to control RX_NBF_PGOBS_DSEL (NSS-1644)
RD          R0 ADDR_SPI_RXB1_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_2
LD          R1 02
AND         R0 R1
R2          = R0
RD          R0 ADDR_SPI_RX1_CORE_RX_NBFIC_REGISTERS_RX_NBF_OBS_CONTROL1
LD          R1 FD
AND         R0 R1
OR          R0 R2
WRA         R0 ADDR_SPI_RX1_CORE_RX_NBFIC_REGISTERS_RX_NBF_OBS_CONTROL1
RETURN


# Enable RX Algorithms
STREAM      25
# Unmask BBDC
WR          ADDR_SPI_RXB1_CORE_DIGITAL_DC_OFFSET_CONTROL_REGISTERS_DIGITAL_DC_OFFSET_DECIMATE 01 
# Enable BBDC, RFDC, AGC, RSSI
WR          ADDR_SPI_RX1_CORE_PROGRAMMABLE_DELAYED_ENABLE_REGISTERS_HW_DELAY_ENABLE_1 0F
# Enable RXQEC_OBS, FIC_OBS, HD2_OBS
WR          ADDR_SPI_RX1_CORE_PROGRAMMABLE_DELAYED_ENABLE_REGISTERS_HW_DELAY_ENABLE_0 0B
# FIXME: temporary workaround for slicer 18 db issue in C0
WRMASK      ADDR_SPI_RXB1_CORE_DCSG_AGC_REGISTERS_DCSG_SLICER_GAIN  01  01
RETURN


STREAM      26
RETURN


# Port A/B Switch
STREAM      27
# set TIA profile. May need read mod write
WRMASK      ADDR_SPI_RX1_ANA_ORX_TIA_CONFIGURATION_REGISTERS_ORXTIA_TUNER_MODE 01 01
RD          R0 ADDR_SPI_RXB1_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_19
SHIFT       R0 FC  # right shift 4 bits. Bit 4-5 is TIA profile
WRA         R0 ADDR_SPI_RXB1_CORE_AGC_GENERAL_SETUP_REGISTERS_RX_TIA_PROFILE
WRMASK      ADDR_SPI_RX1_ANA_ORX_TIA_CONFIGURATION_REGISTERS_ORXTIA_TUNER_MODE 00 01

##### QEC Mutual Exclusion #####
# Trigger main stream "PLL1 LOCK RISE"
WR          ADDR_SPI_CORE_2_BBIC_INTERFACE_REGISTERS_BBIC_PLL  00
WR          ADDR_SPI_CORE_2_BBIC_INTERFACE_REGISTERS_BBIC_PLL  01
RDWAIT      ADDR_SPI_CORE_2_PROGRAMMABLE_DELAYED_ENABLE_REGISTERS_MAIN_INT_DELAY_ENABLE_PED_START_DELAY0  01  01
# QEC Mutual Exclusion 
WRMASK      ADDR_SPI_CORE_RADIO_CONTROL_REGISTERS_ENABLES_FOR_STREAMPROC_RX2  00  20
# Set RX QEC Profile
SHIFT       R0 FF
R2          = R0
LD          R0 01
SUB         R0 R2
WRA         R0 ADDR_SPI_CORE_RADIO_CONTROL_REGISTERS_ENABLES_FOR_STREAMPROC_RX1
# Release resource
WR          ADDR_SPI_CORE_2_PROGRAMMABLE_DELAYED_ENABLE_REGISTERS_MAIN_INT_DELAY_ENABLE_PED_START_DELAY0  00
##### QEC Mutual Exclusion #####

RD          R0 ADDR_SPI_RXB1_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_19
LD          R1 01               # Bit 0 is next frame port, 0: Port A, 1: Port B
AND         R0 R1               # If Bit 0 is 1
# all sub-functions do not use R registers
CONDCALL    1E                  # power down RX1 port A
CONDCALL    1D                  # Power up RX1 Port B
CONDCALL    1B                  # pouwer up RX1 port B mixer LO buffer
SUB         R0 R1               # else
CONDCALL    1F                  # power down RX1 port B
CONDCALL    1C                  # Power up RX1 Port A
CONDCALL    1A                  # pouwer up RX1 port A mixer LO buffer
RETURN


# Handle PLL phase sync if enabled
STREAM      28
LD          R0 $PllPhaseSyncWait$
CONDCALL    2A
RETURN


# Enable/disable QEC Clock (R7: 00-disable; 40-enable)
STREAM      29
# Trigger main stream "PLL1 LOCK RISE"
WR          ADDR_SPI_CORE_2_BBIC_INTERFACE_REGISTERS_BBIC_PLL  00
WR          ADDR_SPI_CORE_2_BBIC_INTERFACE_REGISTERS_BBIC_PLL  01
RDWAIT      ADDR_SPI_CORE_2_PROGRAMMABLE_DELAYED_ENABLE_REGISTERS_MAIN_INT_DELAY_ENABLE_PED_START_DELAY0  01  01
# Enable/disable QEC Clock
RD          R0 ADDR_SPI_CORE_2_CORE_RXQEC_REGISTERS_CORE_RXQEC_CONTROL0
LD          R1 BF
AND         R0 R1
OR          R0 R7
WRA         R0 ADDR_SPI_CORE_2_CORE_RXQEC_REGISTERS_CORE_RXQEC_CONTROL0
# Release resource
WR          ADDR_SPI_CORE_2_PROGRAMMABLE_DELAYED_ENABLE_REGISTERS_MAIN_INT_DELAY_ENABLE_PED_START_DELAY0  00
RETURN


# PLL phase sync
STREAM      2A
# Write to LO phase sync control SPI register
RD          R0 ADDR_SPI_CORE_1_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_6
LD          R1 01
AND         R0 R1       # R0: 0 (LO1) or 1 (LO2)
LD          R1 200
MUL         R0 R1       # R0: 0x0000 or 0x0200
LD          R1 ADDR_SPI_RF1_PLL_LO_PH_SYNC_REGS_PSCTL0
ADD         R0 R1       # R0: 0x1C4F (LO1) or 0x1E4F (LO2)
WRD         R0 81       # Abort any previous running phase sync
WAIT        $Delay_1us$
WRD         R0 6B       # Write caltyp value to start next phase sync
# Wait for PLL phase sync
WAIT        $PllPhaseSyncWait$
RETURN


# GPIO low observer
STREAM      2B
# Set SPI GPIO bit 0 low
WRMASK      ADDR_SPI_CORE_GPIO_1P8V_CONTROL_GPIO_1P8V_SPI_SOURCE_BYTE0 00 01
WAIT        5
RETURN


# GPIO high observer
STREAM      2C
# Set SPI GPIO bit 0 high
WRMASK      ADDR_SPI_CORE_GPIO_1P8V_CONTROL_GPIO_1P8V_SPI_SOURCE_BYTE0 01 01
WAIT        5
RETURN


# Power off LVDS pads (rx1_clk_lvds_oe, rx1_strobe_lvds_oe, rx1_Idata_lvds_oe, rx1_Qdata_lvds_oe)
STREAM      2D
# Disable RX1 interface : will clear all local flags
WRMASK      ADDR_SPI_RX1_CORE_RX_SSI_CONFIG_REGISTERS_LSSI_RX_CONTROL 00 07
# Disable strobe/idata/qdata
WRMASK      ADDR_SPI_CORE_LVDS_CMOS_CONFIG_REGISTERS_RX1_STROBE_LVDS_MODE_DELAY 00 01
WRMASK      ADDR_SPI_CORE_LVDS_CMOS_CONFIG_REGISTERS_RX1_CLK_LVDS_MODE_DELAY    00 01
WRMASK      ADDR_SPI_CORE_LVDS_CMOS_CONFIG_REGISTERS_RX1_IDATA_LVDS_MODE_DELAY  00 01
WRMASK      ADDR_SPI_CORE_LVDS_CMOS_CONFIG_REGISTERS_RX1_QDATA_LVDS_MODE_DELAY  00 01
# Enable RX CLK if SPARE_REGISTERS_11 bit 1 is 1
RD          R0 ADDR_SPI_RXB1_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_11
LD          R1 02
AND         R0 R1
SHIFT       R0 FF       # Right shift 1
R2          = R0
RD          R0 ADDR_SPI_CORE_LVDS_CMOS_CONFIG_REGISTERS_RX1_CLK_LVDS_MODE_DELAY
LD          R1 FE
AND         R0 R1
OR          R0 R2
WRA         R0 ADDR_SPI_CORE_LVDS_CMOS_CONFIG_REGISTERS_RX1_CLK_LVDS_MODE_DELAY
RETURN


# Power on LVDS pads (rx1_clk_lvds_oe, rx1_strobe_lvds_oe, rx1_Idata_lvds_oe, rx1_Qdata_lvds_oe)
STREAM      2E
# Clear RX LVDS FIFO (self clear bit)
# WRMASK      ADDR_SPI_RX1_CORE_RX_SSI_CONFIG_REGISTERS_LSSI_RX_CONTROL           08 08
# Enable the RX1 FIFO interface and Reset RX1 FIFO pointers
WRMASK      ADDR_SPI_RX1_CORE_RX_SSI_CONFIG_REGISTERS_LSSI_RX_CONTROL           06 06
WRMASK      ADDR_SPI_RX1_CORE_RX_SSI_CONFIG_REGISTERS_LSSI_RX_FIFO_CONTROL_RESET 03 03
# Enable RX1 LSSI interface pads
WRMASK      ADDR_SPI_CORE_LVDS_CMOS_CONFIG_REGISTERS_RX1_STROBE_LVDS_MODE_DELAY 01 01
WRMASK      ADDR_SPI_CORE_LVDS_CMOS_CONFIG_REGISTERS_RX1_CLK_LVDS_MODE_DELAY    01 01
WRMASK      ADDR_SPI_CORE_LVDS_CMOS_CONFIG_REGISTERS_RX1_IDATA_LVDS_MODE_DELAY  01 01
# Enable QDATA if SPARE_REGISTERS_11 bit 4 is 1 (2 lane LVDS)
RD          R0 ADDR_SPI_RXB1_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_11
LD          R1 10
AND         R0 R1
SHIFT       R0 FC       # Right shift 4
R2          = R0
RD          R0 ADDR_SPI_CORE_LVDS_CMOS_CONFIG_REGISTERS_RX1_QDATA_LVDS_MODE_DELAY
LD          R1 FE
AND         R0 R1
OR          R0 R2
WRA         R0 ADDR_SPI_CORE_LVDS_CMOS_CONFIG_REGISTERS_RX1_QDATA_LVDS_MODE_DELAY
# start RX1 interface
WRMASK      ADDR_SPI_RX1_CORE_RX_SSI_CONFIG_REGISTERS_LSSI_RX_CONTROL            01 01
# Release RX1 FIFO
WRMASK      ADDR_SPI_RX1_CORE_RX_SSI_CONFIG_REGISTERS_LSSI_RX_FIFO_CONTROL_RESET 00 03
RETURN


# To be called by RX Hop Edge Stream 5
STREAM      2F
# Retune PLL if required
$IfRx1IntLo$ RD R0 ADDR_SPI_RXB1_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_1
$IfRx1IntLo$ CONDCALL 34        # Call PLL retune Pre VCO cal stream

# DMA Power up Config B (Post-VCO Cal and PLL Path Config and Power Up)
CALL        03

# Handle PLL phase sync
CALL        28

# Can i call stream 13 directly without setting delay enable?
CALL        13
RETURN


# DMA Power up Config C (LDO Power Up)
STREAM      30
# Reset status register
WR          ADDR_SPI_RXB1_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_17 00
# Write Byte 0 of starting Address
WR          ADDR_SPI_CORE_1_GENERAL_DMA_2_REGISTERS_GENERAL_DMA_2_START_TABLE_ADDR_BYTE0 E0
# Enable DMA
WR          ADDR_SPI_CORE_1_GENERAL_DMA_2_REGISTERS_GENERAL_DMA_2_CONTROL0 01
# Write Next_RX bit
WRMASK      ADDR_SPI_CORE_1_GENERAL_DMA_2_REGISTERS_GENERAL_DMA_2_CONTROL1 02 02
# Wait for Completion
RDWAIT      ADDR_SPI_RXB1_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_17 07 07
# Disable DMA
WRMASK      ADDR_SPI_CORE_1_GENERAL_DMA_2_REGISTERS_GENERAL_DMA_2_CONTROL0 00 01
# Wait for LDO power up
WAIT        $LdoPowerUpWait$
RETURN     


# DMA Power up Config D (PLL Power Up)
STREAM      31
# Reset status register
WR          ADDR_SPI_RXB1_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_17 00
# Write Byte 0 of starting Address
WR          ADDR_SPI_CORE_1_GENERAL_DMA_2_REGISTERS_GENERAL_DMA_2_START_TABLE_ADDR_BYTE0 E4
# Enable DMA
WR          ADDR_SPI_CORE_1_GENERAL_DMA_2_REGISTERS_GENERAL_DMA_2_CONTROL0 01
# Write Next_RX bit
WRMASK      ADDR_SPI_CORE_1_GENERAL_DMA_2_REGISTERS_GENERAL_DMA_2_CONTROL1 02 02
# Wait for Completion
RDWAIT      ADDR_SPI_RXB1_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_17 07 07
# Disable DMA
WRMASK      ADDR_SPI_CORE_1_GENERAL_DMA_2_REGISTERS_GENERAL_DMA_2_CONTROL0 00 01   
RETURN


# Reset RX LNA switch (AGPIO bit 1 low)
STREAM      32
WRMASK      ADDR_SPI_CORE_1_GPIO_ANALOG_CONTROL_GPIO_ANALOG_SPI_SOURCE_7_0  00  02
RETURN


# Set RX LNA switch (AGPIO bit 1 high)
STREAM      33
WRMASK      ADDR_SPI_CORE_1_GPIO_ANALOG_CONTROL_GPIO_ANALOG_SPI_SOURCE_7_0  02  02
RETURN


# PLL retune Pre VCO cal or only wait for PLL lock (R0: SOFTWARE_SPARE_1)
STREAM      34
R2          = R0
LD          R1 01
AND         R0 R1
CONDCALL    02        # Call PLL retune Pre VCO cal stream
R0          = R2
LD          R1 02
AND         R0 R1
CONDCALL    37        # Wait for PLL lock by another stream without retuning LO
RETURN


# RX Hop Edge in LO MUX FH mode
STREAM      35
# Copy all bits from spare_14 to spare_19 except bit2 indicating the current port
RD          R0 ADDR_SPI_RXB1_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_19
LD          R2 04
AND         R0 R2
R2          = R0
RD          R0 ADDR_SPI_RXB1_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_14
# SOFTWARE_SPARE_14 bit2 is cleared in FW function rxPortSwitchUpdate()
OR          R0 R2
WRA         R0 ADDR_SPI_RXB1_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_19

#################### RX port A/B switch #################
# Bit 1 of RX_INT_DELAY_ENABLE indicates if RX is currently On or Off
# Bit 1 of SPARE_7 indicates if the upcoming frame is RX (SPARE_7 can only be 0 or 2)
# Bit 1 of SPARE_19 indicates if RX port is changed in the upcoming frame
# If all the bits are 1, we need to do port switch. If either current
# RX is off or the upcoming frame is not RX, the switch will be
# completed in the delay enable fall and rise streams.
RD          R0 ADDR_SPI_RX1_CORE_PROGRAMMABLE_DELAYED_ENABLE_REGISTERS_RX_INT_DELAY_ENABLE
RD          R4 ADDR_SPI_RXB1_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_19
AND         R0 R4
RD          R4 ADDR_SPI_RXB1_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_7
AND         R0 R4
# Stream 27 and sub-functions use R0 and R1
CONDCALL    27
##########################################################

#################### Check Rx status #####################
# If starting an Rx frame, and Rx is already powered up, just swap the LO, etc. (Consecutive RX frame case)
RD          R0 ADDR_SPI_RX1_CORE_PROGRAMMABLE_DELAYED_ENABLE_REGISTERS_RX_INT_DELAY_ENABLE
# R0 (SOFTWARE_SPARE_7) is either 0x2 or 0x0, and R0 can be 0x2, 0x6, or 0xE
# Since we just need to know if bit 1 (0x2) is set, we can AND directly with R0
RD          R4 ADDR_SPI_RXB1_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_7
AND         R0 R4
CONDCALL    2F
##########################################################

################# Set Rx power up/dowm ###################
# Set INT_RX_DELAYED_ENABLE
RD          R0 ADDR_SPI_RX1_CORE_PROGRAMMABLE_DELAYED_ENABLE_REGISTERS_RX_INT_DELAY_ENABLE
LD          R1 FD
AND         R0 R1
OR          R0 R4
WRA         R0 ADDR_SPI_RX1_CORE_PROGRAMMABLE_DELAYED_ENABLE_REGISTERS_RX_INT_DELAY_ENABLE
##########################################################

# Disable Rx enable flag for next frame
WR          ADDR_SPI_RXB1_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_7 00
RETURN


# Toggle ORx
STREAM      36
# Read Current Port
RD          R0 ADDR_SPI_RXB1_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_19
LD          R1 04 # Current Port Bit Position
AND         R0 R1
#If Currently Port B, Toggle Port A
CONDCALL 3C
#Else Toggle Port B
XOR         R0 R1
CONDCALL 3D
RETURN


# Wait for PLL lock
STREAM      37
WAIT        $Pll1LockWait$
RETURN


# Trigger stream 0D "INT LOOPBACK RISE STREAM"
STREAM      38
# Mark as none RX frame first
WR          ADDR_SPI_RXB1_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_7 00
WRMASK      ADDR_SPI_CORE_2_BBIC_INTERFACE_REGISTERS_BBIC_RX1_BYTE1  00  02
WRMASK      ADDR_SPI_CORE_2_BBIC_INTERFACE_REGISTERS_BBIC_RX1_BYTE1  02  02
RETURN


# Wait on semaphore from ARM to update resources in LO Retune FH modes
STREAM      39
RDWAIT      ADDR_SPI_RXB1_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_10  02  03

# Reset semaphore from ARM to update resources in LO Retune FH modes
WR          ADDR_SPI_RXB1_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_10  03
RETURN

# Power up RX PFIR
STREAM      3A
WRMASK      ADDR_SPI_RX1_CORE_RX_DATAPATH_CONFIG_RX_NBDEM_ENABLE_1 04 04
RETURN

#Power down RX Pfir
STREAM      3B
WRMASK      ADDR_SPI_RX1_CORE_RX_DATAPATH_CONFIG_RX_NBDEM_ENABLE_1 00 04
RETURN

# Toggle ORxA
STREAM      3C
# Power Up
WRMASK ADDR_SPI_RX1_ANA_POWER_DOWN_REGISTERS_ORX_PD 00 07               # rxTia_HwPowerUp
WRMASK ADDR_SPI_RX1_ANA_POWER_DOWN_REGISTERS_ORX2_PD 01 01              # WRITE_ANALOG_RX_MEM_MAP_ORX1FE_PD(base, 0x1u);                  /* Power down Mixer */ 
WRMASK ADDR_SPI_RX1_ANA_POWER_DOWN_REGISTERS_LB1_PD  01 01              # WRITE_ANALOG_RX_MEM_MAP_LB1FE_PD(base, 0x1u);                   /* Power down Mixer */   
WRMASK ADDR_SPI_RX1_ANA_ORX_FE_REGISTERS_ORX_BB_MUX 02 02               # WRITE_ANALOG_RX_MEM_MAP_PD_BB_AMUX_ORX2_TX2LB(base, 0x1u);      /* power down RX/LBRX Mux */
WRMASK ADDR_SPI_RX1_ANA_ORX_FE_REGISTERS_ORX_BB_MUX 00 04               # WRITE_ANALOG_RX_MEM_MAP_SELECT_ORX1_OR_TX1LB(base, 0x0u);       /* Select RX */
WRMASK ADDR_SPI_RX1_ANA_ORX_FE_REGISTERS_ORX_BB_MUX 00 01               # WRITE_ANALOG_RX_MEM_MAP_PD_BB_AMUX_ORX1_TX1LB(base, 0x0u);      /* power up RX Mux */      
# WRMASK ADDR_SPI_RX1_ANA_LO_DELAY_REGISTERS_ORX1_LO_DELAY_CORR_CONTROL_1 00 10     # WRITE_ANALOG_RX_MEM_MAP_ORX1_LO_DELAY_CORR_PD(base, 0x0u);      /* power-up LO delay */
WRMASK ADDR_SPI_RX1_ANA_POWER_DOWN_REGISTERS_ORX1_PD 00 04              # WRITE_ANALOG_RX_MEM_MAP_PD_ORX1_MIXER_CAPDAC(base, 0x0u);       /* Power up RX_B mixer */
WRMASK ADDR_SPI_RX1_ANA_POWER_DOWN_REGISTERS_ORX1_PD 02 02              # WRITE_ANALOG_RX_MEM_MAP_PD_ORX1_LODELAY_BUFFER(base, 0x1u);     /* power down LO buffer */
WRMASK ADDR_SPI_RX1_ANA_POWER_DOWN_REGISTERS_ORX1_PD 00 01              # WRITE_ANALOG_RX_MEM_MAP_ORX1FE_PD(base, 0x0u);                  /* Power up Mixer */ 

# Power Down
WRMASK ADDR_SPI_RX1_ANA_POWER_DOWN_REGISTERS_ORX1_PD 02 02              # rxFePowerLoBuffer()
WRMASK ADDR_SPI_RX1_ANA_POWER_DOWN_REGISTERS_ORX_PD 07 07               # rxTia_HwPowerDown
WRMASK ADDR_SPI_RX1_ANA_LO_DELAY_REGISTERS_ORX1_LO_DELAY_CORR_CONTROL_1 10 10       # WRITE_ANALOG_RX_MEM_MAP_ORX1_LO_DELAY_CORR_PD(base, 0x1u);      /* power-down LO delay */            
WRMASK ADDR_SPI_RX1_ANA_POWER_DOWN_REGISTERS_ORX1_PD 04 04              # WRITE_ANALOG_RX_MEM_MAP_PD_ORX1_MIXER_CAPDAC(base, 0x1u);       /* Power down loopback mixer */
WRMASK ADDR_SPI_RX1_ANA_POWER_DOWN_REGISTERS_ORX1_PD 01 01              # WRITE_ANALOG_RX_MEM_MAP_ORX1FE_PD(base, 0x1u);                  /* Power down loopback mixer */       
# WRMASK ADDR_SPI_RX1_ANA_ORX_FE_REGISTERS_ORX_BB_MUX 02 02             # WRITE_ANALOG_RX_MEM_MAP_PD_BB_AMUX_ORX1_TX1LB(base, 0x1u);      /* power down RX mux */  
RETURN

# Toggle ORxB
STREAM      3D
# Power Up
WRMASK ADDR_SPI_RX1_ANA_POWER_DOWN_REGISTERS_ORX_PD 00 07               # rxTia_HwPowerUp
WRMASK ADDR_SPI_RX1_ANA_POWER_DOWN_REGISTERS_ORX1_PD 01 01              # WRITE_ANALOG_RX_MEM_MAP_ORX1FE_PD(base, 0x1u);                  /* Power down Mixer */ 
WRMASK ADDR_SPI_RX1_ANA_POWER_DOWN_REGISTERS_LB1_PD  01 01              # WRITE_ANALOG_RX_MEM_MAP_LB1FE_PD(base, 0x1u);                   /* Power down Mixer */   
WRMASK ADDR_SPI_RX1_ANA_ORX_FE_REGISTERS_ORX_BB_MUX 01 01               # WRITE_ANALOG_RX_MEM_MAP_PD_BB_AMUX_ORX1_TX1LB(base, 0x1u);      /* power down RX/LBRX Mux */
WRMASK ADDR_SPI_RX1_ANA_ORX_FE_REGISTERS_ORX_BB_MUX 00 08               # WRITE_ANALOG_RX_MEM_MAP_SELECT_ORX2_OR_TX2LB(base, 0x0u);       /* Select RX */
WRMASK ADDR_SPI_RX1_ANA_ORX_FE_REGISTERS_ORX_BB_MUX 00 02               # WRITE_ANALOG_RX_MEM_MAP_PD_BB_AMUX_ORX2_TX2LB(base, 0x0u);      /* power up RX Mux */      
# WRMASK ADDR_SPI_RX1_ANA_LO_DELAY_REGISTERS_ORX2_LO_DELAY_CORR_CONTROL_1 00 10     # WRITE_ANALOG_RX_MEM_MAP_ORX2_LO_DELAY_CORR_PD(base, 0x0u);      /* power-up LO delay */
WRMASK ADDR_SPI_RX1_ANA_POWER_DOWN_REGISTERS_ORX2_PD 00 04              # WRITE_ANALOG_RX_MEM_MAP_PD_ORX2_MIXER_CAPDAC(base, 0x0u);       /* Power up RX_B mixer */
WRMASK ADDR_SPI_RX1_ANA_POWER_DOWN_REGISTERS_ORX2_PD 02 02              # WRITE_ANALOG_RX_MEM_MAP_PD_ORX2_LODELAY_BUFFER(base, 0x1u);     /* power down LO buffer */
WRMASK ADDR_SPI_RX1_ANA_POWER_DOWN_REGISTERS_ORX2_PD 00 01              # WRITE_ANALOG_RX_MEM_MAP_ORX2FE_PD(base, 0x0u);                  /* Power up Mixer */ 

# Power Down
WRMASK ADDR_SPI_RX1_ANA_POWER_DOWN_REGISTERS_ORX2_PD 02 02              # rxFePowerLoBuffer()
WRMASK ADDR_SPI_RX1_ANA_POWER_DOWN_REGISTERS_ORX_PD 07 07               # rxTia_HwPowerDown
WRMASK ADDR_SPI_RX1_ANA_LO_DELAY_REGISTERS_ORX2_LO_DELAY_CORR_CONTROL_1 10 10       # WRITE_ANALOG_RX_MEM_MAP_ORX2_LO_DELAY_CORR_PD(base, 0x1u);      /* power-down LO delay */            
WRMASK ADDR_SPI_RX1_ANA_POWER_DOWN_REGISTERS_ORX2_PD 04 04              # WRITE_ANALOG_RX_MEM_MAP_PD_ORX2_MIXER_CAPDAC(base, 0x1u);       /* Power down loopback mixer */
WRMASK ADDR_SPI_RX1_ANA_POWER_DOWN_REGISTERS_ORX2_PD 01 01              # WRITE_ANALOG_RX_MEM_MAP_ORX2FE_PD(base, 0x1u);                  /* Power down loopback mixer */       
# WRMASK ADDR_SPI_RX1_ANA_ORX_FE_REGISTERS_ORX_BB_MUX 02 02             # WRITE_ANALOG_RX_MEM_MAP_PD_BB_AMUX_ORX2_TX2LB(base, 0x1u);      /* power down RX mux */  
RETURN

STREAM      3E
RETURN

STREAM      3F
RETURN
