# ########## RX2 STREAM ###########

# Set INT_RX_ENABLE bit high attached to delay enable with enableRiseToAnalogOnDelay
STREAM      0
# Set INT_RX_ENABLE high
WRMASK      ADDR_SPI_RX2_CORE_PROGRAMMABLE_DELAYED_ENABLE_REGISTERS_RX_INT_DELAY_ENABLE 02 02
RD          R0 ADDR_SPI_RXB2_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_4
CONDCALL    30                  # Call LDO Power Up stream
RD          R0 ADDR_SPI_RXB2_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_5
CONDCALL    31                  # Call PLL Power Up stream
$IfRx2IntLo$ RD R0 ADDR_SPI_RXB2_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_6
$IfRx2IntLo$ CONDCALL 02        # Call PLL retune Pre VCO cal stream
RETURN


# Set INT_RX_ENABLE bit low attached to delay enable with enableFallToOffDelay
STREAM      1
WRMASK      ADDR_SPI_RX2_CORE_PROGRAMMABLE_DELAYED_ENABLE_REGISTERS_RX_INT_DELAY_ENABLE 00 02
RETURN


# DMA Power up Config A (Pre-VCO Cal)
STREAM      2
# Reset status register
WR          ADDR_SPI_RXB2_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_17 00
# Write Byte 0 of starting Address
WR          ADDR_SPI_CORE_1_GENERAL_DMA_3_REGISTERS_GENERAL_DMA_3_START_TABLE_ADDR_BYTE0 A4
# Enable DMA
WR          ADDR_SPI_CORE_1_GENERAL_DMA_3_REGISTERS_GENERAL_DMA_3_CONTROL0 01
# Write Next_RX bit
WRMASK      ADDR_SPI_CORE_1_GENERAL_DMA_3_REGISTERS_GENERAL_DMA_3_CONTROL1 02 02
# Wait for Completion
RDWAIT      ADDR_SPI_RXB2_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_17 07 07
# Disable DMA
WRMASK      ADDR_SPI_CORE_1_GENERAL_DMA_3_REGISTERS_GENERAL_DMA_3_CONTROL0 00 01
# Wait for PLL lock
WAIT        $Pll1LockWait$
# Set DMA debug flag
WRMASK      ADDR_SPI_RXB2_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_10 01 01
RETURN


# DMA Power up Config B (Post-VCO Cal and PLL Path Config and Power Up)
STREAM      3
RD          R0 ADDR_SPI_RXB2_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_13
CONDCALL    26
# Calculate byte 0 of DMA address. Checks HOP_1_TOGGLE_READBACK. If frequency hopping mode is disabled 
# this register always readsback as 0
LD          R1 02
# Default address of DMA table
LD          R2 A8
RD          R0 ADDR_SPI_CORE_2_PROGRAMMABLE_DELAYED_ENABLE_REGISTERS_MAIN_HOP_TOGGLE_READBACK
AND         R0 R1
# Since hop read back for channel 2 is now 0x2, rather than 0x1 for channel 1, we can multiple
# the read back by 0x2, rather than 0x4, to get the appropriate DMA start address offset.
# R1 already contain 0x2
MUL         R0 R1
ADD         R0 R2
WRA         R0 ADDR_SPI_CORE_1_GENERAL_DMA_3_REGISTERS_GENERAL_DMA_3_START_TABLE_ADDR_BYTE0
# Reset status register
WR          ADDR_SPI_RXB2_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_17 00
# Enable DMA
WR          ADDR_SPI_CORE_1_GENERAL_DMA_3_REGISTERS_GENERAL_DMA_3_CONTROL0 01
# Write Next_RX bit
WRMASK      ADDR_SPI_CORE_1_GENERAL_DMA_3_REGISTERS_GENERAL_DMA_3_CONTROL1 02 02
# Wait for Completion
RDWAIT      ADDR_SPI_RXB2_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_17 07 07
# Disable DMA
WRMASK      ADDR_SPI_CORE_1_GENERAL_DMA_3_REGISTERS_GENERAL_DMA_3_CONTROL0 00 01
# Set DMA debug flag and clear DMA debug flag from power down stream
WRMASK      ADDR_SPI_RXB2_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_10 02 12
RETURN


# DMA Power Down Config (PLL path power down)    
STREAM      4
# Write Byte 0 of starting Address
# WR          ADDR_SPI_CORE_1_GENERAL_DMA_3_REGISTERS_GENERAL_DMA_3_START_TABLE_ADDR_BYTE0 B0
# Calculate byte 0 of DMA address. Checks HOP_1_TOGGLE_READBACK. If frequency hopping mode is disabled 
# this register always readsback as 0
LD          R1 02
# Default address of DMA table
LD          R2 B0
RD          R0 ADDR_SPI_CORE_2_PROGRAMMABLE_DELAYED_ENABLE_REGISTERS_MAIN_HOP_TOGGLE_READBACK
AND         R0 R1
# Since hop read back for channel 2 is now 0x2, rather than 0x1 for channel 1, we can multiple
# the read back by 0x2, rather than 0x4, to get the appropriate DMA start address offset.
# R1 already contain 0x2
MUL         R0 R1
ADD         R0 R2
WRA         R0 ADDR_SPI_CORE_1_GENERAL_DMA_3_REGISTERS_GENERAL_DMA_3_START_TABLE_ADDR_BYTE0
# Reset status register
WR          ADDR_SPI_RXB2_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_17 00
# Enable DMA
WR          ADDR_SPI_CORE_1_GENERAL_DMA_3_REGISTERS_GENERAL_DMA_3_CONTROL0 01
# Write Next_RX bit
WRMASK      ADDR_SPI_CORE_1_GENERAL_DMA_3_REGISTERS_GENERAL_DMA_3_CONTROL1 02 02
# Wait for Completion
RDWAIT      ADDR_SPI_RXB2_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_17 07 07
# Disable DMA
WRMASK      ADDR_SPI_CORE_1_GENERAL_DMA_3_REGISTERS_GENERAL_DMA_3_CONTROL0 00 01   
# Set DMA debug flag and clear DMA debug flags from power up stream
WR          ADDR_SPI_RXB2_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_10 10
RETURN


# RX Hop Edge
STREAM      5
TIMEOUT     FFFF
############# Partial power down Rx each hop ############
# Mask ADC output
WRMASK      ADDR_SPI_RX2_CORE_RX_DATAPATH_CONFIG_RX_DATAPATH_FORCE_ZERO 01 01
# Power down RX LO mux buffer
WR          ADDR_SPI_CORE_1_ANALOG_REGISTERS_RX2_LO_REG 07
# Disable RX algorithms
CALL        19
# Update NCO FTW (This should have no effect if there is no FTW programmed)
WRMASK      ADDR_SPI_RX2_CORE_RX_DATAPATH_CONFIG_RX_NCO_FTW_UPDATE_CONTROL 01 01
WRMASK      ADDR_SPI_RX2_CORE_RX_DATAPATH_CONFIG_RX_NCO_FTW_UPDATE_CONTROL 00 01
#########################################################

#################### Check Rx status #####################
# If starting an Rx frame, and Rx is already powered up, 
# just swap the LO, etc.
RD          R0 ADDR_SPI_RX2_CORE_PROGRAMMABLE_DELAYED_ENABLE_REGISTERS_RX_INT_DELAY_ENABLE
# R0 (SOFTWARE_SPARE_7) is either 0x2 or 0x0, and R1 can be 0x2, 0x6, or 0xE
# Since we just need to know if bit 1 (0x2) is set, we can AND directly with R0
# 2F may result in R1 and R3 getting reset
RD          R4 ADDR_SPI_RXB2_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_7
AND         R0 R4
CONDCALL    2F
##########################################################

################# Set Rx power up/dowm ###################
# Set INT_RX_DELAYED_ENABLE
RD          R0 ADDR_SPI_RX2_CORE_PROGRAMMABLE_DELAYED_ENABLE_REGISTERS_RX_INT_DELAY_ENABLE
LD          R3 FD
AND         R0 R3
OR          R0 R4
WRA         R0 ADDR_SPI_RX2_CORE_PROGRAMMABLE_DELAYED_ENABLE_REGISTERS_RX_INT_DELAY_ENABLE
##########################################################

# Disable Rx enable flag for next frame
WR          ADDR_SPI_RXB2_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_7 00
RETURN


# RX Hop Edge During RX High
STREAM      6
# Set Rx enable flag for next frame
WR ADDR_SPI_RXB2_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_7 02
RETURN


# RX ENABLE RISE STREAM
STREAM      7
TIMEOUT     FFFF
# Bypass stream 00 in Frequency Hopping mode
RD          R0 ADDR_SPI_RXB2_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_13
LD          R1 01
XOR         R0 R1
CONDCALL    00              # Set INT_RX_ENABLE bit high
RETURN


# RX ENABLE RISE DURING HOP MODE STREAM
STREAM      8
RETURN


# RX ENABLE FALL STREAM
STREAM      9
#WR         ADDR_SPI_RXB2_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_11 10
# Assert SPI GPIO Bit 3 High
#WRMASK     ADDR_SPI_CORE_GPIO_1P8V_CONTROL_GPIO_1P8V_SPI_SOURCE_BYTE0 08 08
# Bypass stream 01 in Frequency Hopping mode
RD          R0 ADDR_SPI_RXB2_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_13
LD          R1 01
XOR         R0 R1
CONDCALL    01              # Set INT_RX_ENABLE bit low
RETURN


# RX ENABLE FALL DURING HOP MODE
STREAM      0A
RETURN


# ORX ENABLE RISE STREAM
STREAM      0B
TIMEOUT     FFFF
# Interrupt ARM: streamProc_orx2EnableRiseHandler()
# This interrupt allows the ARM to does some processing in parallel
INTERRUPT   04
# Set flag which is cleared by ARM
WR          ADDR_SPI_RXB2_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_15 FF
RETURN


# EXT LOOPBACK RISE STREAM
STREAM      0C
RETURN


# INT LOOPBACK RISE STREAM
STREAM      0D
RETURN


# ORX ENABLE FALL STREAM
STREAM      0E
# Set flag which is cleared by ARM
WR          ADDR_SPI_RXB2_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_15 FF
INTERRUPT   08
# Disable ORx
WRMASK      ADDR_SPI_RX2_CORE_PROGRAMMABLE_DELAYED_ENABLE_REGISTERS_RX_INT_DELAY_ENABLE 00 01
RETURN


# EXT LOOPBACK FALL STREAM
STREAM      0F
RETURN


# INT LOOPBACK FALL STREAM
STREAM      10
RETURN


# RX_INT_DELAYED1_ENABLE RISE (SPI BIT) (Set LNA power up GPIO pin)
STREAM      11
#WRMASK     ADDR_SPI_RXB2_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_11 08 08
# Assert SPI GPIO Bit 3 Low
#WRMASK     ADDR_SPI_CORE_GPIO_1P8V_CONTROL_GPIO_1P8V_SPI_SOURCE_BYTE0 00 08
RETURN


# INT_ORX_DELAYED_ENABLE RISE (SPI_BIT)
STREAM      12
TIMEOUT     FFFF

# Force maximum attenuation on ORX
$IfRx2A$    WRMASK ADDR_SPI_RX2_ANA_ORX_FE_REGISTERS_ORX2FE_LOCM   40 40
$IfRx2A$    WRMASK ADDR_SPI_RX2_ANA_ORX_FE_REGISTERS_ORX2FE_LOCM_B 40 40
$IfNoRx2A$  WRMASK ADDR_SPI_RX2_ANA_ORX_FE_REGISTERS_ORX1FE_LOCM   40 40
$IfNoRx2A$  WRMASK ADDR_SPI_RX2_ANA_ORX_FE_REGISTERS_ORX1FE_LOCM_B 40 40

# Start DMA for ORx datapath switch
# rx_SwitchDigitalDataPath() - DMA Switch Digital Data Path
# Reset status register
WR          ADDR_SPI_RXB2_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_17 00# Unmask data to datapath
# Write Byte 0 of starting Address
WR          ADDR_SPI_CORE_1_GENERAL_DMA_3_REGISTERS_GENERAL_DMA_3_START_TABLE_ADDR_BYTE0 8C
# Enable DMA
WR          ADDR_SPI_CORE_1_GENERAL_DMA_3_REGISTERS_GENERAL_DMA_3_CONTROL0 01
# Write Next_RX bit
WRMASK      ADDR_SPI_CORE_1_GENERAL_DMA_3_REGISTERS_GENERAL_DMA_3_CONTROL1 02 02

# loGen_LoMapping() - Set LOMUX_RX2 to be the same as LOMUX_TX1 for ORX2
# This could be done in DMA. 
# The reason a spare register is used, rather than reading TX lo mux settings, 
# is that ORx enable may happen in parallel with Tx power up.
RD          R0 ADDR_SPI_RXB2_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_18
WRA         R0 ADDR_SPI_CORE_1_ANALOG_REGISTERS_RX2_SEL_LO2

# Setting ANALOG_REGISTERS_RX2_LO_REG in Rx only and FH mode
# SOFTWARE_SPARE_9 is either 00 (indicating LO1) or 1 (indicating LO2)
# For ORx power up, ANALOG_REGISTERS_RX2_LO_REG should either be 0x1 (LO1)
# or 0x2 (LO2).
# Adding 01 to SOFTWARE_SPARE_9 yields either 01 (LO1) or 02 (LO2).
# This approach is used in order to:
#     * Save two sub streams
#     * Save a SW spare register 
#     * Save ARM PM, DM, and CYCLES in order to maintain and update 
#       a DMA table in FH mode.
# This approach could be replaced with one of the above if a different solution is 
# desired.
LD          R1 01
ADD         R0 R1 
LD          R1 03
XOR         R0 R1
WRA         R0 ADDR_SPI_CORE_1_ANALOG_REGISTERS_RX2_LO_REG

### alg_channelProfileSwitch (ORX) - Configure ORX Algorithms
# Set radio states (BBDC, NBFIC, AGC, RFDC)
# WR          ADDR_SPI_RX2_CORE_CHANNEL_CONFIGURATION_RX_CHAN_FUNCS_RADIO_STATES 55
# RX TIA Fc and Fine Tune
WRMASK      ADDR_SPI_RX2_ANA_ORX_TIA_CONFIGURATION_REGISTERS_ORXTIA_TUNER_MODE 01 01
# Select TIA Profile
WRMASK      ADDR_SPI_RXB2_CORE_AGC_GENERAL_SETUP_REGISTERS_RX_TIA_PROFILE 02 07
# RX TIA Fc and Fine Tune
WRMASK      ADDR_SPI_RX2_ANA_ORX_TIA_CONFIGURATION_REGISTERS_ORXTIA_TUNER_MODE 00 01

##### QEC Mutual Exclusion #####
# Trigger main stream "PLL1 LOCK RISE"
WR          ADDR_SPI_CORE_2_BBIC_INTERFACE_REGISTERS_BBIC_PLL  00
WR          ADDR_SPI_CORE_2_BBIC_INTERFACE_REGISTERS_BBIC_PLL  04
RDWAIT      ADDR_SPI_CORE_2_PROGRAMMABLE_DELAYED_ENABLE_REGISTERS_MAIN_INT_DELAY_ENABLE_PED_END_DELAY0  01  01
# QEC Mutual Exclusion 
WRMASK      ADDR_SPI_CORE_RADIO_CONTROL_REGISTERS_ENABLES_FOR_STREAMPROC_RX2  20  20
# Set RX QEC Profile
WRMASK      ADDR_SPI_CORE_RADIO_CONTROL_REGISTERS_ENABLES_FOR_STREAMPROC_RX2  01  07
# Release resource
WR          ADDR_SPI_CORE_2_PROGRAMMABLE_DELAYED_ENABLE_REGISTERS_MAIN_INT_DELAY_ENABLE_PED_END_DELAY0  00
##### QEC Mutual Exclusion #####

# NB FIC (NSS-1644)
WRMASK      ADDR_SPI_RX2_CORE_RX_NBFIC_REGISTERS_RX_NBF_OBS_CONTROL1 00 02
# Set AGC to manual
RD          R0 ADDR_SPI_RXB2_CORE_AGC_GENERAL_SETUP_REGISTERS_AGC_CONFIG
WRA         R0 ADDR_SPI_RXB2_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_16
WRMASK      ADDR_SPI_RXB2_CORE_AGC_GENERAL_SETUP_REGISTERS_AGC_CONFIG 00 03

# Power down phase sync detector.
WRMASK      ADDR_SPI_TX2_ANA_LO_MUX_CONTROL_LO_MUX_CONTROL 10 10

### RCVR_OrxPowerUp (ORX, orx_adcType)
# Enable the HP ADC and LP ADC clocks
WRMASK      ADDR_SPI_CORE_1_ANALOG_SPARE_REGISTERS_ANALOG_SPARE_REG_9 00 03
# Enable the Clock Gen Output Buffer
WR          ADDR_SPI_RX2_CORE_CHANNEL_CONFIGURATION_RX_CLOCK_CONFIG_0 01
# Enable positive and negatve phase of the data clock
WRMASK      ADDR_SPI_CORE_1_ANALOG_SPARE_REGISTERS_ANALOG_SPARE_REG_2 07 07
$IfRx2A$    CALL 1D             # Power up ORX2A FE == Power up RX2B FE
$IfNoRx2A$  CALL 1C             # Power up ORX2B FE == Power up RX2A FE

# Power up TIA
WR          ADDR_SPI_RX2_ANA_POWER_DOWN_REGISTERS_ORX_PD 00
# Read ADC_Switching flag
LD          R7 01               # Select ORX ADC Profile
RD          R0 ADDR_SPI_RXB2_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_9
CONDCALL    20                  # Power up HP ADC
# Toggle the value in R0
LD          R1 01
XOR         R0 R1
CONDCALL    21                  # else, Power up LP ADC
# Select PFIR Bank to BANK D (Fix for TNDD-450 is in FW. Stream needs it?)
WRMASK      ADDR_SPI_CORE_MAG_CONFIG_MAG_SEL0 C0 C0
# ORx does not use dynamic PFIR switch and bank is set by DMA
# Read PFIR Bank in use (could change dynamically) and select bank appropriately
## RD          R1 ADDR_SPI_RXB2_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_3
## WRA         R1 ADDR_SPI_CORE_RX2_DATAPATH_CONFIG_CORE_RX2_PFIR_MODE_MAPPING
# Enable QEC Clocks
#WRMASK     ADDR_SPI_CORE_2_CORE_RXQEC_REGISTERS_CORE_RXQEC_CONTROL0 80 80
RD          R0 ADDR_SPI_CORE_1_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_7
LD          R1 01
AND         R0 R1
XOR         R0 R1
LD          R7 80
CONDCALL    29

# Trigger main stream "PLL2 LOCK RISE"
WR          ADDR_SPI_CORE_2_BBIC_INTERFACE_REGISTERS_BBIC_PLL  00
WR          ADDR_SPI_CORE_2_BBIC_INTERFACE_REGISTERS_BBIC_PLL  04
RDWAIT      ADDR_SPI_CORE_2_PROGRAMMABLE_DELAYED_ENABLE_REGISTERS_MAIN_INT_DELAY_ENABLE_PED_END_DELAY0  01  01
# QEC Reset
WRMASK      ADDR_SPI_CORE_RX_QEC_REGISTERS_RXQEC_SW_RESET 02 02
WRMASK      ADDR_SPI_CORE_RX_QEC_REGISTERS_RXQEC_SW_RESET 00 02
# Release resource
WR          ADDR_SPI_CORE_2_PROGRAMMABLE_DELAYED_ENABLE_REGISTERS_MAIN_INT_DELAY_ENABLE_PED_END_DELAY0  00

# Power up RX mixer LO buffer
$IfRx2A$    WR ADDR_SPI_RX2_ANA_POWER_DOWN_REGISTERS_ORX2_PD 00     # Power up ORX2A == Power up RX2B
$IfNoRx2A$  WR ADDR_SPI_RX2_ANA_POWER_DOWN_REGISTERS_ORX1_PD 00     # Power up ORX2B == Power up RX2A

# Check if DMA has completed 
# Wait for Completion
RDWAIT      ADDR_SPI_CORE_1_GENERAL_DMA_3_REGISTERS_GENERAL_DMA_3_STATUS_FLAGS 07 07
# Disable DMA
WRMASK      ADDR_SPI_CORE_1_GENERAL_DMA_3_REGISTERS_GENERAL_DMA_3_CONTROL0 00 01   

# Poll registers to see if ARM has completed it's tasks
RDWAIT      ADDR_SPI_RXB2_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_15 00 FF

# Disable forcing maximum attenuation on ORX
$IfRx2A$    WRMASK ADDR_SPI_RX2_ANA_ORX_FE_REGISTERS_ORX2FE_LOCM   00 40
$IfRx2A$    WRMASK ADDR_SPI_RX2_ANA_ORX_FE_REGISTERS_ORX2FE_LOCM_B 00 40
$IfNoRx2A$  WRMASK ADDR_SPI_RX2_ANA_ORX_FE_REGISTERS_ORX1FE_LOCM   00 40
$IfNoRx2A$  WRMASK ADDR_SPI_RX2_ANA_ORX_FE_REGISTERS_ORX1FE_LOCM_B 00 40

# Unmask data to datapath
WR          ADDR_SPI_RX2_CORE_RX_DATAPATH_CONFIG_RX_DATAPATH_FORCE_ZERO 10

### alg_channelProfileEnable (ORX)
WR         ADDR_SPI_RX2_CORE_PROGRAMMABLE_DELAYED_ENABLE_REGISTERS_HW_DELAY_ENABLE_0 00
WR         ADDR_SPI_RX2_CORE_PROGRAMMABLE_DELAYED_ENABLE_REGISTERS_HW_DELAY_ENABLE_1 00
# Unmask BBDC 
WR         ADDR_SPI_RXB2_CORE_DIGITAL_DC_OFFSET_CONTROL_REGISTERS_DIGITAL_DC_OFFSET_DECIMATE 01 
# Disable and re-enable BBDC
# WRMASK      ADDR_SPI_RX2_CORE_PROGRAMMABLE_DELAYED_ENABLE_REGISTERS_HW_DELAY_ENABLE_1 00 08
WRMASK      ADDR_SPI_RX2_CORE_PROGRAMMABLE_DELAYED_ENABLE_REGISTERS_HW_DELAY_ENABLE_1 08 08
# Enable ORX QEC
WRMASK      ADDR_SPI_RX2_CORE_PROGRAMMABLE_DELAYED_ENABLE_REGISTERS_HW_DELAY_ENABLE_0 04 04
# Enable FIC if spare_2 is set 
RD          R0 ADDR_SPI_RXB2_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_2
# Spare 2 will have bit 0 set if ORx NBFIC is enabled.
# Clear all bits except bit 0 in R0 and shift it left by 1 to match bit position of 
# NBFIC enable in HW_DELAYE_ENABLE_0 
LD          R1 01 
AND         R0 R1
SHIFT       R0 01       # Left shift 1
# Read/Modify/Write HW_DELAY_ENABLE_0
RD          R1 ADDR_SPI_RX2_CORE_PROGRAMMABLE_DELAYED_ENABLE_REGISTERS_HW_DELAY_ENABLE_0
OR          R0 R1
WRA         R0 ADDR_SPI_RX2_CORE_PROGRAMMABLE_DELAYED_ENABLE_REGISTERS_HW_DELAY_ENABLE_0
# RFDC is NOT enabled for ORx
#WRMASK     ADDR_SPI_RX2_CORE_PROGRAMMABLE_DELAYED_ENABLE_REGISTERS_HW_DELAY_ENABLE_1 04 04
WRMASK      ADDR_SPI_RX2_CORE_PROGRAMMABLE_DELAYED_ENABLE_REGISTERS_HW_DELAY_ENABLE_1 02 02
# Open SSI 
WR          ADDR_SPI_RX2_CORE_RX_DATAPATH_CONFIG_RX_DATAPATH_FORCE_ZERO 00

# Reset all SCIC filters
WRMASK      ADDR_SPI_RX2_CORE_RX_NBFIC_REGISTERS_RX_ALG_NBFIC_OBS_SCIC_RESET 01 01
WRMASK      ADDR_SPI_RX2_CORE_RX_NBFIC_REGISTERS_RX_ALG_NBFIC_OBS_SCIC_RESET 00 01
# Force digital gain strobe ((WORKAROUND_TNDD_581))
WRMASK      ADDR_SPI_RX2_CORE_RX_DIGITAL_GAIN_REGISTERS_GAIN_COMPENATION_AND_SLICER_CONFIG 40 40
RETURN


# RX_INT_DELAYED0_ENABLE RISE (SPI BIT)
STREAM      13
# Unmask datapath from interface
WR          ADDR_SPI_RX2_CORE_RX_DATAPATH_CONFIG_RX_DATAPATH_FORCE_ZERO 00
# Reset SCIC (ADRV9003-1374)
WRMASK     ADDR_SPI_RX2_CORE_RX_NBFIC_REGISTERS_RX_ALG_NBFIC_OBS_SCIC_RESET 01 01
WRMASK     ADDR_SPI_RX2_CORE_RX_NBFIC_REGISTERS_RX_ALG_NBFIC_OBS_SCIC_RESET 00 01
# Force digital gain strobe ((WORKAROUND_TNDD_581))
WRMASK      ADDR_SPI_RX2_CORE_RX_DIGITAL_GAIN_REGISTERS_GAIN_COMPENATION_AND_SLICER_CONFIG 40 40
CALL        25              # Enable algorithms
# Interrupt ARM: streamProc_rx2EnableRiseHandler()
INTERRUPT   01
#WRMASK     ADDR_SPI_RXB2_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_11 04 04
RETURN


#INT_RX_DELAYED_ENABLE RISE (SPI BIT)
STREAM      14
TIMEOUT     FFFF
# Set bit int_delay_1_enable attached to delay enable with rxEnableRiseToOnDelay - rxEnableRiseToAnaOnDelay
WRMASK      ADDR_SPI_RX2_CORE_PROGRAMMABLE_DELAYED_ENABLE_REGISTERS_RX_INT_DELAY_ENABLE 08 08
#INTERRUPT   10
############# Power on LVDS pads ############
RD          R0 ADDR_SPI_RXB2_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_11
LD          R1 01
AND         R0 R1
CONDCALL    2E
#############################################
$IfRx2IntLo$ RD R0 ADDR_SPI_RXB2_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_1
$IfRx2IntLo$ CONDCALL 02        # Call PLL retune Pre VCO cal stream
# CALL        03                  # Call PLL Post VCO cal stream, LO mux, LO gen, LO path power up
# Enable magnitude compensation PFIR
#WRMASK      ADDR_SPI_RX2_CORE_RX_DATAPATH_CONFIG_RX_NBDEM_ENABLE_1 04 04
# Enable the HP ADC and LP ADC clocks
WRMASK      ADDR_SPI_CORE_1_ANALOG_SPARE_REGISTERS_ANALOG_SPARE_REG_9 00 03
# Enable the Clock Gen Output Buffer
WR          ADDR_SPI_RX2_CORE_CHANNEL_CONFIGURATION_RX_CLOCK_CONFIG_0 01
# Enable positive and negatve phase of the data clock
WRMASK      ADDR_SPI_CORE_1_ANALOG_SPARE_REGISTERS_ANALOG_SPARE_REG_2 07 07
$IfRx2A$    CALL 1C             # Power up RX2A FE
$IfNoRx2A$  CALL 1D             # Power up RX2B FE
# Power up TIA
WR          ADDR_SPI_RX2_ANA_POWER_DOWN_REGISTERS_ORX_PD 00
# Enable datapath clocks
WR          ADDR_SPI_RX2_CORE_RX_DATAPATH_CONFIG_ALL_RX_ENABLE 01
# Read ADC_Switching flag
LD          R7 00               # Select RX ADC Profile
RD          R0 ADDR_SPI_RXB2_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_9
CONDCALL    20                  # Power up HP ADC
# Toggle the value in R0
LD          R1 01
XOR         R0 R1
CONDCALL    21                  # else, Power up LP ADC

# Trigger main stream "PLL2 LOCK RISE"
WR          ADDR_SPI_CORE_2_BBIC_INTERFACE_REGISTERS_BBIC_PLL  00
WR          ADDR_SPI_CORE_2_BBIC_INTERFACE_REGISTERS_BBIC_PLL  04
RDWAIT      ADDR_SPI_CORE_2_PROGRAMMABLE_DELAYED_ENABLE_REGISTERS_MAIN_INT_DELAY_ENABLE_PED_END_DELAY0  01  01
# Select PFIR Bank to BANK C
WRMASK      ADDR_SPI_CORE_MAG_CONFIG_MAG_SEL0 80 C0
WR          ADDR_SPI_CORE_2_PROGRAMMABLE_DELAYED_ENABLE_REGISTERS_MAIN_INT_DELAY_ENABLE_PED_END_DELAY0  00

# Read PFIR Bank in use (could change dynamically) and select bank appropriately
RD          R1 ADDR_SPI_RXB2_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_3
WRA         R1 ADDR_SPI_CORE_RX2_DATAPATH_CONFIG_CORE_RX2_PFIR_MODE_MAPPING
#Enable QEC Clocks
#WRMASK     ADDR_SPI_CORE_2_CORE_RXQEC_REGISTERS_CORE_RXQEC_CONTROL0 80 80
RD          R0 ADDR_SPI_CORE_1_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_7
LD          R1 01
AND         R0 R1
XOR         R0 R1
LD          R7 80
CONDCALL    29

# Select RX datapath  Profile (Set all bits to Rx)
WRMASK      ADDR_SPI_RX2_CORE_RX_DATAPATH_CONFIG_ORX_PROFILE_SEL 00 FF
# Power up RX mixer LO buffer
$IfRx2A$    WR          ADDR_SPI_RX2_ANA_POWER_DOWN_REGISTERS_ORX1_PD 00
$IfNoRx2A$  WR          ADDR_SPI_RX2_ANA_POWER_DOWN_REGISTERS_ORX2_PD 00
# Trigger main stream "PLL2 LOCK RISE"
WR          ADDR_SPI_CORE_2_BBIC_INTERFACE_REGISTERS_BBIC_PLL  00
WR          ADDR_SPI_CORE_2_BBIC_INTERFACE_REGISTERS_BBIC_PLL  04
RDWAIT      ADDR_SPI_CORE_2_PROGRAMMABLE_DELAYED_ENABLE_REGISTERS_MAIN_INT_DELAY_ENABLE_PED_END_DELAY0  01  01
# Flush datapath filters inside RXQEC block
WRMASK      ADDR_SPI_CORE_RX_QEC_REGISTERS_RXQEC_SW_RESET 02 02
WRMASK      ADDR_SPI_CORE_RX_QEC_REGISTERS_RXQEC_SW_RESET 00 02
# Release resource
WR          ADDR_SPI_CORE_2_PROGRAMMABLE_DELAYED_ENABLE_REGISTERS_MAIN_INT_DELAY_ENABLE_PED_END_DELAY0  00

CALL        03                  # Call PLL Post VCO cal stream, LO mux, LO gen, LO path power up
$IfRx2IntLo$ RD R0 ADDR_SPI_RXB2_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_1
$IfRx2IntLo$ CONDCALL 28        # Handle PLL phase sync

# Wait for analog to settle
WAIT        $Delay_80ns$
WAIT        $Delay_80ns$
WAIT        $Delay_80ns$
CALL        24                  # Configure algorithms
# Set bit int_delay_0_enable
WRMASK      ADDR_SPI_RX2_CORE_PROGRAMMABLE_DELAYED_ENABLE_REGISTERS_RX_INT_DELAY_ENABLE 04 04
# Unmask datapath from ADC
WR          ADDR_SPI_RX2_CORE_RX_DATAPATH_CONFIG_RX_DATAPATH_FORCE_ZERO 10
# Set GPIO to high for debug if feature is enabled
RD          R0 ADDR_SPI_CORE_1_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_2
CONDCALL    2C
RETURN


#INT_RX_DELAYED_ENABLE FALL (SPI BIT)
STREAM      15
TIMEOUT     FFFF
# Assert SPI GPIO Bit 3 Low
#WRMASK     ADDR_SPI_CORE_GPIO_1P8V_CONTROL_GPIO_1P8V_SPI_SOURCE_BYTE0 00 08
# Reset bit int_delay_0_enable and int_delay_1_enable
WRMASK      ADDR_SPI_RX2_CORE_PROGRAMMABLE_DELAYED_ENABLE_REGISTERS_RX_INT_DELAY_ENABLE 00 0C
#INTERRUPT   20
# Mask ADC from datapath
WR          ADDR_SPI_RX2_CORE_RX_DATAPATH_CONFIG_RX_DATAPATH_FORCE_ZERO 01
# Disable magnitude compensation PFIR
#WRMASK      ADDR_SPI_RX2_CORE_RX_DATAPATH_CONFIG_RX_NBDEM_ENABLE_1 00 04
CALL        19                  # Disable RX algorithms
# Read ADC_Switching flag
RD          R0 ADDR_SPI_RXB2_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_9
CONDCALL    22                  # Power down HP ADC
# Toggle the value in R0
RD          R0 ADDR_SPI_RXB2_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_9
LD          R1 01
XOR         R0 R1
CONDCALL    23                  # else, Power down LP ADC 
$IfRx2A$    CALL 1E             # Power down RX2A FE
$IfNoRx2A$  CALL 1F             # Power down RX2B FE
# Power down TIA
WR          ADDR_SPI_RX2_ANA_POWER_DOWN_REGISTERS_ORX_PD 07
#Disable RX QEC clocks
#WRMASK     ADDR_SPI_CORE_2_CORE_RXQEC_REGISTERS_CORE_RXQEC_CONTROL0 00 80
RD          R0 ADDR_SPI_CORE_1_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_7
LD          R1 01
AND         R0 R1
XOR         R0 R1
LD          R7 00
CONDCALL    29
# Disable the HP ADC and LPADC clocks
WRMASK      ADDR_SPI_CORE_1_ANALOG_SPARE_REGISTERS_ANALOG_SPARE_REG_9 03 03
# Disable the Clock Gen Output Buffer
WR          ADDR_SPI_RX2_CORE_CHANNEL_CONFIGURATION_RX_CLOCK_CONFIG_0 00
# Disable positive and negative phase of the data clock
WRMASK      ADDR_SPI_CORE_1_ANALOG_SPARE_REGISTERS_ANALOG_SPARE_REG_2  00 07 
CALL        04                  # DMA Power Down PLL path
# Set GPIO to low for debug if feature is enabled
RD          R0 ADDR_SPI_CORE_1_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_2
CONDCALL    2B
RETURN 


# INT_ORX_DELAYED_ENABLE FALL (SPI BIT)
STREAM      16
TIMEOUT     FFFF
# Mask ADC from datapath
WR          ADDR_SPI_RX2_CORE_RX_DATAPATH_CONFIG_RX_DATAPATH_FORCE_ZERO 01
# Disable algorithms
CALL        19

# Force maximum attenuation on ORX
$IfRx2A$    WRMASK ADDR_SPI_RX2_ANA_ORX_FE_REGISTERS_ORX2FE_LOCM   40 40
$IfRx2A$    WRMASK ADDR_SPI_RX2_ANA_ORX_FE_REGISTERS_ORX2FE_LOCM_B 40 40
$IfNoRx2A$  WRMASK ADDR_SPI_RX2_ANA_ORX_FE_REGISTERS_ORX1FE_LOCM   40 40
$IfNoRx2A$  WRMASK ADDR_SPI_RX2_ANA_ORX_FE_REGISTERS_ORX1FE_LOCM_B 40 40

# Start DMA for switch back to default Rx datapath
# Reset status register
WR          ADDR_SPI_RXB2_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_17 00
# Write Byte 0 of starting Address
WR          ADDR_SPI_CORE_1_GENERAL_DMA_3_REGISTERS_GENERAL_DMA_3_START_TABLE_ADDR_BYTE0 84 # Get appropriate starting addr
# Enable DMA
WR          ADDR_SPI_CORE_1_GENERAL_DMA_3_REGISTERS_GENERAL_DMA_3_CONTROL0 01
# Write Next_RX bit
WRMASK      ADDR_SPI_CORE_1_GENERAL_DMA_3_REGISTERS_GENERAL_DMA_3_CONTROL1 02 02
# Disable LO mux 
WR          ADDR_SPI_CORE_1_ANALOG_REGISTERS_RX2_LO_REG 07
### RCVR_OrxPowerDown (ORX, orx_adcType)
# Read ADC_Switching flag
RD          R0 ADDR_SPI_RXB2_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_9
CONDCALL    22                  # Power down HP ADC
# Toggle the value in R0
LD          R1 01
XOR         R0 R1
CONDCALL    23                  # else, Power down LP ADC 
$IfRx2A$    CALL 1F             # If Rx=Rx2A, power down Rx2B
$IfNoRx2A$  CALL 1E             # If Rx=Rx2B, power down Rx2A
# Power down TIA
WR          ADDR_SPI_RX2_ANA_POWER_DOWN_REGISTERS_ORX_PD 07
#Disable RX QEC clocks
#WRMASK     ADDR_SPI_CORE_2_CORE_RXQEC_REGISTERS_CORE_RXQEC_CONTROL0 00 80
RD          R0 ADDR_SPI_CORE_1_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_7
LD          R1 01
AND         R0 R1
XOR         R0 R1
LD          R7 00
CONDCALL    29
# Disable the HP ADC and LP ADC clocks
WRMASK      ADDR_SPI_CORE_1_ANALOG_SPARE_REGISTERS_ANALOG_SPARE_REG_9 03 03
# Disable the Clock Gen Output Buffer
WR          ADDR_SPI_RX2_CORE_CHANNEL_CONFIGURATION_RX_CLOCK_CONFIG_0 00
# Disable positive and negative phase of the data clock
WRMASK      ADDR_SPI_CORE_1_ANALOG_SPARE_REGISTERS_ANALOG_SPARE_REG_2  00 07
# Mask datapath from interface
WR          ADDR_SPI_RX2_CORE_RX_DATAPATH_CONFIG_RX_DATAPATH_FORCE_ZERO 11

# Check if DMA has completed 
# Wait for Completion
RDWAIT      ADDR_SPI_CORE_1_GENERAL_DMA_3_REGISTERS_GENERAL_DMA_3_STATUS_FLAGS 07 07
# Disable DMA
WRMASK      ADDR_SPI_CORE_1_GENERAL_DMA_3_REGISTERS_GENERAL_DMA_3_CONTROL0 00 01   

# Restore AGC
RD          R0 ADDR_SPI_RXB2_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_16
WRA         R0 ADDR_SPI_RXB2_CORE_AGC_GENERAL_SETUP_REGISTERS_AGC_CONFIG
# Poll registers to see if ARM has completed it's tasks
RDWAIT      ADDR_SPI_RXB2_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_15 00 FF
# Toggle Global Reset
WRMASK      ADDR_SPI_RX2_CORE_ORX1_CONFIG_ORX1_DP_RESET 01 01
WRMASK      ADDR_SPI_RX2_CORE_ORX1_CONFIG_ORX1_DP_RESET 00 01
# Disable RX datapath clock
WR          ADDR_SPI_RX2_CORE_RX_DATAPATH_CONFIG_ALL_RX_ENABLE 00
RETURN


# RX_INT_DELAYED0_ENABLE FALL (SPI_BIT)
STREAM      17
TIMEOUT     FFFF
# Mask datapath from interface
WR          ADDR_SPI_RX2_CORE_RX_DATAPATH_CONFIG_RX_DATAPATH_FORCE_ZERO 11
# Toggle Global Reset
WRMASK      ADDR_SPI_RX2_CORE_RX_DATAPATH_CONFIG_RX_DP_RESET 01 01
WRMASK      ADDR_SPI_RX2_CORE_RX_DATAPATH_CONFIG_RX_DP_RESET 00 01
# Disable RX datapath clock
WR          ADDR_SPI_RX2_CORE_RX_DATAPATH_CONFIG_ALL_RX_ENABLE 00
############ Power off LVDS pads ############
RD          R0 ADDR_SPI_RXB2_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_11
LD          R1 01
AND         R0 R1
CONDCALL    2D
#############################################
# Interrupt ARM: streamProc_rx2GenericStreamHandler()
INTERRUPT   02
RETURN


# RX_INT_DELAYED1_ENABLE FALL (SPI_BIT)
STREAM      18
#WRMASK     ADDR_SPI_RXB2_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_11 80 80
RETURN   


# Disable RX Algorithms
STREAM      19
# Mask BBDC
WR          ADDR_SPI_RXB2_CORE_DIGITAL_DC_OFFSET_CONTROL_REGISTERS_DIGITAL_DC_OFFSET_DECIMATE 21 
# Disable BBDC, RFDC, AGC, RSSI  
WR          ADDR_SPI_RX2_CORE_PROGRAMMABLE_DELAYED_ENABLE_REGISTERS_HW_DELAY_ENABLE_1 00
# Disable RXQEC_OBS, FIC_OBS, HD2_OBS
WR          ADDR_SPI_RX2_CORE_PROGRAMMABLE_DELAYED_ENABLE_REGISTERS_HW_DELAY_ENABLE_0 00
#WRMASK     ADDR_SPI_CORE_RADIO_CONTROL_REGISTERS_ENABLES_FOR_STREAMPROC_RX2 00 01
# Clear RX2 QEC mutex debug bit
#WRMASK      ADDR_SPI_CORE_1_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_7  00  20
RETURN


STREAM      1A
RETURN


STREAM      1B
RETURN


# Power up RX2A
STREAM      1C
# Power down ORX, ILB mixers
WR          ADDR_SPI_RX2_ANA_POWER_DOWN_REGISTERS_ORX2_PD 07
WR          ADDR_SPI_RX2_ANA_POWER_DOWN_REGISTERS_LB1_PD  07
# Select RX mixer
WR          ADDR_SPI_RX2_ANA_ORX_FE_REGISTERS_ORX_BB_MUX  02
# Power up LO Delay
WRMASK      ADDR_SPI_RX2_ANA_LO_DELAY_REGISTERS_ORX1_LO_DELAY_CORR_CONTROL_1 00 10
# Power up RX mixer
WR          ADDR_SPI_RX2_ANA_POWER_DOWN_REGISTERS_ORX1_PD 02
RETURN


# Power up RX2B
STREAM      1D
# Power down ORX, ILB mixers
WR          ADDR_SPI_RX2_ANA_POWER_DOWN_REGISTERS_ORX1_PD 07
WR          ADDR_SPI_RX2_ANA_POWER_DOWN_REGISTERS_LB1_PD  07
# Select RX mixer
WR          ADDR_SPI_RX2_ANA_ORX_FE_REGISTERS_ORX_BB_MUX  01
# Power up LO Delay
WRMASK      ADDR_SPI_RX2_ANA_LO_DELAY_REGISTERS_ORX1_LO_DELAY_CORR_CONTROL_1 00 10
# Power up RX mixer
WR          ADDR_SPI_RX2_ANA_POWER_DOWN_REGISTERS_ORX2_PD 02
RETURN  


# Power down RX2A
STREAM      1E
# Power down LO buffer
WR          ADDR_SPI_RX2_ANA_POWER_DOWN_REGISTERS_ORX1_PD 02
# Power down LO Delay
WRMASK      ADDR_SPI_RX2_ANA_LO_DELAY_REGISTERS_ORX1_LO_DELAY_CORR_CONTROL_1 10 10
# Power down FE and Capdac	
WR          ADDR_SPI_RX2_ANA_POWER_DOWN_REGISTERS_ORX1_PD 07
# Power down RX mux
WR          ADDR_SPI_RX2_ANA_ORX_FE_REGISTERS_ORX_BB_MUX 03   
RETURN


# Power down RX2B
STREAM      1F
# Power down LO buffer
WR          ADDR_SPI_RX2_ANA_POWER_DOWN_REGISTERS_ORX2_PD 02
# Power down LO Delay
WRMASK      ADDR_SPI_RX2_ANA_LO_DELAY_REGISTERS_ORX2_LO_DELAY_CORR_CONTROL_1 10 10
# Power down FE and Capdac	
WR          ADDR_SPI_RX2_ANA_POWER_DOWN_REGISTERS_ORX2_PD 07
# Power down RX mux
WR          ADDR_SPI_RX2_ANA_ORX_FE_REGISTERS_ORX_BB_MUX 03   
RETURN


# Power up HP ADC (R7(ADC Profile): 0-RX; 1-ORX; 2-ILB; 3-ELB)
STREAM      20
# Disable the LP ADC clock
WRMASK      ADDR_SPI_CORE_1_ANALOG_SPARE_REGISTERS_ANALOG_SPARE_REG_9 02 02
# Enable ADC Startup Reset before Power Up
WRMASK      ADDR_SPI_RX2_CORE_RX_OVERLOAD_RESET_DETECTION_REGISTERS_RX_ADC_OVERLOAD_RESET_THRESHOLD 00 80
# Assert adc_rst_dc, adc_dac_bypass_rf and de-assert adc_pd_dacs-delay, adc_pd_bias
WR          ADDR_SPI_RX2_ADC_REGMAP1_ADC_PD 60
# Wait for 1us
WAIT        $Delay_1us$
# Assert adc_rst_dc, adc_dac_bypass_rf, adc_pd_dacs_delay, adc_pd_bias
WR          ADDR_SPI_RX2_ADC_REGMAP1_ADC_PD 00
# Release ADC Startup 
WRMASK      ADDR_SPI_RX2_CORE_RX_OVERLOAD_RESET_DETECTION_REGISTERS_RX_ADC_OVERLOAD_RESET_THRESHOLD 80 80 
# Select ADC Profile (HP ADC)
WRA         R7 ADDR_SPI_RX2_CORE_CHANNEL_CONFIGURATION_RX_ADC_PROFILE
RETURN


# Power up LP ADC
STREAM      21
# Disable the HP ADC clock
WRMASK      ADDR_SPI_CORE_1_ANALOG_SPARE_REGISTERS_ANALOG_SPARE_REG_9 01 01
# Enable ana and dig cal blocks, adc bias block, channel I&Q ADC clocks channel I&Q analog front end 
WR          ADDR_SPI_RX2_ADC_LP_VCOADC_ANA_POWER_DOWN_REG DF
# Wait for 4 us
WAIT        $Delay_1us$
WAIT        $Delay_1us$
WAIT        $Delay_1us$
WAIT        $Delay_1us$
# Enable clock for VCO ADC digital
WRMASK      ADDR_SPI_RX2_ADC_LP_VCOADC_DIG_CAL_EN 80 80
RETURN


# Power down HP ADC
STREAM      22
##force ADC Reset
WRMASK      ADDR_SPI_RX2_CORE_RX_OVERLOAD_RESET_DETECTION_REGISTERS_RX_ADC_OVERLOAD_RESET_SIZE 80 80
## Toggle adc_flash_reset_mode
RD          R0 ADDR_SPI_RX2_ADC_REGMAP1_ADC_FLASH_CAL_CTRL
LD          R1 10
XOR         R0 R1
WRA         R0 ADDR_SPI_RX2_ADC_REGMAP1_ADC_FLASH_CAL_CTRL
WRA         R0 ADDR_SPI_RX2_ADC_REGMAP1_ADC_FLASH_CAL_CTRL      # This seems to be redundent
# wait 10 cycles with ARM @184.32MHz or ~52ns as per Rama's stream low simulation. Reuse Delay_80ns tag to wait a little longer.
WAIT        $Delay_80ns$
# Release ADC reset
WRMASK      ADDR_SPI_RX2_CORE_RX_OVERLOAD_RESET_DETECTION_REGISTERS_RX_ADC_OVERLOAD_RESET_THRESHOLD 80 80
# Power down HP ADC
WR          ADDR_SPI_RX2_ADC_REGMAP1_ADC_PD 7F
# Clear Force ADC reset
WRMASK      ADDR_SPI_RX2_CORE_RX_OVERLOAD_RESET_DETECTION_REGISTERS_RX_ADC_OVERLOAD_RESET_SIZE 00 80
RETURN 


# Power Down LP ADC
STREAM      23
# Disable ana and dig cal blocks, adc bias block, channel I&Q ADC clocks channel I&Q analog front end 
WR          ADDR_SPI_RX2_ADC_LP_VCOADC_ANA_POWER_DOWN_REG 00
# Disable clock for VCO ADC digital
WRMASK      ADDR_SPI_RX2_ADC_LP_VCOADC_DIG_CAL_EN 00 80    
RETURN


# Configure RX Algorithms
STREAM      24
#####Configure Algorithms#######
# Set radio states (BBDC, NBFIC, AGC, RFDC)
WR          ADDR_SPI_RX2_CORE_CHANNEL_CONFIGURATION_RX_CHAN_FUNCS_RADIO_STATES 00
# RX TIA Fc and Fine Tune
WRMASK      ADDR_SPI_RX2_ANA_ORX_TIA_CONFIGURATION_REGISTERS_ORXTIA_TUNER_MODE 01 01
# Set TIA Profile (NSS-1963)
RD          R0 ADDR_SPI_RXB2_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_14
LD          R1 07
AND         R0 R1
R2          = R0
RD          R0 ADDR_SPI_RXB2_CORE_AGC_GENERAL_SETUP_REGISTERS_RX_TIA_PROFILE
LD          R1 F8
AND         R0 R1
OR          R0 R2
WRA         R0 ADDR_SPI_RXB2_CORE_AGC_GENERAL_SETUP_REGISTERS_RX_TIA_PROFILE
# RX TIA Fc and Fine Tune
WRMASK      ADDR_SPI_RX2_ANA_ORX_TIA_CONFIGURATION_REGISTERS_ORXTIA_TUNER_MODE 00 01

##### QEC Mutual Exclusion #####
# Trigger main stream "PLL1 LOCK RISE"
WR          ADDR_SPI_CORE_2_BBIC_INTERFACE_REGISTERS_BBIC_PLL  00
WR          ADDR_SPI_CORE_2_BBIC_INTERFACE_REGISTERS_BBIC_PLL  04
RDWAIT      ADDR_SPI_CORE_2_PROGRAMMABLE_DELAYED_ENABLE_REGISTERS_MAIN_INT_DELAY_ENABLE_PED_END_DELAY0  01  01
# QEC Mutual Exclusion 
WRMASK      ADDR_SPI_CORE_RADIO_CONTROL_REGISTERS_ENABLES_FOR_STREAMPROC_RX2  20  20
# Set RX QEC Profile
WRMASK      ADDR_SPI_CORE_RADIO_CONTROL_REGISTERS_ENABLES_FOR_STREAMPROC_RX2  01  07
# Release resource
WR          ADDR_SPI_CORE_2_PROGRAMMABLE_DELAYED_ENABLE_REGISTERS_MAIN_INT_DELAY_ENABLE_PED_END_DELAY0  00
##### QEC Mutual Exclusion #####

# NB FIC
#WRMASK     ADDR_SPI_RX2_CORE_RX_NBFIC_REGISTERS_RX_NBF_OBS_CONTROL1 02 02
# Use spare register 2 bit1 to control RX_NBF_PGOBS_DSEL (NSS-1644)
RD          R0 ADDR_SPI_RXB2_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_2
LD          R1 02
AND         R0 R1
R2          = R0
RD          R0 ADDR_SPI_RX2_CORE_RX_NBFIC_REGISTERS_RX_NBF_OBS_CONTROL1
LD          R1 FD
AND         R0 R1
OR          R0 R2
WRA         R0 ADDR_SPI_RX2_CORE_RX_NBFIC_REGISTERS_RX_NBF_OBS_CONTROL1
RETURN


# Enable RX Algorithms
STREAM      25
# Unmask BBDC
WR          ADDR_SPI_RXB2_CORE_DIGITAL_DC_OFFSET_CONTROL_REGISTERS_DIGITAL_DC_OFFSET_DECIMATE 01 
# Enable BBDC, RFDC, AGC, RSSI
WR          ADDR_SPI_RX2_CORE_PROGRAMMABLE_DELAYED_ENABLE_REGISTERS_HW_DELAY_ENABLE_1 0F
# Enable RXQEC_OBS, FIC_OBS, HD2_OBS
WR          ADDR_SPI_RX2_CORE_PROGRAMMABLE_DELAYED_ENABLE_REGISTERS_HW_DELAY_ENABLE_0 0B
# FIXME: temporary workaround for slicer 18 db issue in C0
WRMASK      ADDR_SPI_RXB2_CORE_DCSG_AGC_REGISTERS_DCSG_SLICER_GAIN  01  01
RETURN


STREAM      26
# Pend on sw spare 4
RDWAIT     ADDR_SPI_CORE_1_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_4  00  01
RETURN


STREAM      27
RETURN


# Handle PLL phase sync if enabled
STREAM      28
LD          R0 $PllPhaseSyncWait$
CONDCALL    2A
RETURN


# Enable/disable QEC Clock (R7: 00-disable; 80-enable)
STREAM      29
# Trigger main stream "PLL1 LOCK RISE"
WR          ADDR_SPI_CORE_2_BBIC_INTERFACE_REGISTERS_BBIC_PLL  00
WR          ADDR_SPI_CORE_2_BBIC_INTERFACE_REGISTERS_BBIC_PLL  04
RDWAIT      ADDR_SPI_CORE_2_PROGRAMMABLE_DELAYED_ENABLE_REGISTERS_MAIN_INT_DELAY_ENABLE_PED_END_DELAY0  01  01
# Enable/disable QEC Clock
RD          R0 ADDR_SPI_CORE_2_CORE_RXQEC_REGISTERS_CORE_RXQEC_CONTROL0
LD          R1 7F
AND         R0 R1
OR          R0 R7
WRA         R0 ADDR_SPI_CORE_2_CORE_RXQEC_REGISTERS_CORE_RXQEC_CONTROL0
# Release resource
WR          ADDR_SPI_CORE_2_PROGRAMMABLE_DELAYED_ENABLE_REGISTERS_MAIN_INT_DELAY_ENABLE_PED_END_DELAY0  00
RETURN


# PLL phase sync
STREAM      2A
# Write to LO phase sync control SPI register
RD          R0 ADDR_SPI_CORE_1_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_6
SHIFT       R0 FF       # Right shift 1
LD          R1 01
AND         R0 R1       # R0: 0 (LO1) or 1 (LO2)
LD          R1 200
MUL         R0 R1       # R0: 0x0000 or 0x0200
LD          R1 ADDR_SPI_RF1_PLL_LO_PH_SYNC_REGS_PSCTL0
ADD         R0 R1       # R0: 0x1C4F (LO1) or 0x1E4F (LO2)
WRD         R0 0B
# Wait for PLL phase sync
WAIT        $PllPhaseSyncWait$
RETURN


# GPIO low observer
STREAM      2B
WAIT        5
# Set SPI GPIO bit 1 low
WRMASK      ADDR_SPI_CORE_GPIO_1P8V_CONTROL_GPIO_1P8V_SPI_SOURCE_BYTE0 00 04
RETURN


# GPIO high observer
STREAM      2C
WAIT        5
# Set SPI GPIO bit 1 high
WRMASK      ADDR_SPI_CORE_GPIO_1P8V_CONTROL_GPIO_1P8V_SPI_SOURCE_BYTE0 04 04
RETURN


# Power off LVDS pads (rx2_clk_lvds_oe, rx2_strobe_lvds_oe, rx2_Idata_lvds_oe, rx2_Qdata_lvds_oe)
STREAM      2D
# Disable strobe/idata/qdata
WRMASK      ADDR_SPI_CORE_LVDS_CMOS_CONFIG_REGISTERS_RX2_STROBE_LVDS_MODE_DELAY 00 01
WRMASK      ADDR_SPI_CORE_LVDS_CMOS_CONFIG_REGISTERS_RX2_IDATA_LVDS_MODE_DELAY  00 01
WRMASK      ADDR_SPI_CORE_LVDS_CMOS_CONFIG_REGISTERS_RX2_QDATA_LVDS_MODE_DELAY  00 01
# Enable RX CLK if SPARE_REGISTERS_11 bit 1 is 1
RD          R0 ADDR_SPI_RXB2_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_11
LD          R1 02
AND         R0 R1
SHIFT       R0 FF       # Right shift 1
R2          = R0
RD          R0 ADDR_SPI_CORE_LVDS_CMOS_CONFIG_REGISTERS_RX2_CLK_LVDS_MODE_DELAY
LD          R1 FE
AND         R0 R1
OR          R0 R2
WRA         R0 ADDR_SPI_CORE_LVDS_CMOS_CONFIG_REGISTERS_RX2_CLK_LVDS_MODE_DELAY
RETURN


# Power on LVDS pads (rx2_clk_lvds_oe, rx2_strobe_lvds_oe, rx2_Idata_lvds_oe, rx2_Qdata_lvds_oe)
STREAM      2E
# Clear RX LVDS FIFO (self clear bit)
WRMASK      ADDR_SPI_RX2_CORE_RX_SSI_CONFIG_REGISTERS_LSSI_RX_CONTROL           08 08
WRMASK      ADDR_SPI_CORE_LVDS_CMOS_CONFIG_REGISTERS_RX2_CLK_LVDS_MODE_DELAY    01 01
WRMASK      ADDR_SPI_CORE_LVDS_CMOS_CONFIG_REGISTERS_RX2_STROBE_LVDS_MODE_DELAY 01 01
WRMASK      ADDR_SPI_CORE_LVDS_CMOS_CONFIG_REGISTERS_RX2_IDATA_LVDS_MODE_DELAY  01 01
# Enable QDATA if SPARE_REGISTERS_11 bit 4 is 1 (2 lane LVDS)
RD          R0 ADDR_SPI_RXB2_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_11
LD          R1 10
AND         R0 R1
SHIFT       R0 FC       # Right shift 4
R2          = R0
RD          R0 ADDR_SPI_CORE_LVDS_CMOS_CONFIG_REGISTERS_RX2_QDATA_LVDS_MODE_DELAY
LD          R1 FE
AND         R0 R1
OR          R0 R2
WRA         R0 ADDR_SPI_CORE_LVDS_CMOS_CONFIG_REGISTERS_RX2_QDATA_LVDS_MODE_DELAY
RETURN


# To be called by RX Hop Edge Stream 5
STREAM      2F
# DMA Power up Config B (Post-VCO Cal and PLL Path Config and Power Up)
CALL        03
# Can i call stream 13 directly without setting delay enable?
CALL        13
RETURN


# DMA Power up Config C (LDO Power Up)
STREAM      30
# Reset status register
WR          ADDR_SPI_RXB2_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_17 00
# Write Byte 0 of starting Address
WR          ADDR_SPI_CORE_1_GENERAL_DMA_3_REGISTERS_GENERAL_DMA_3_START_TABLE_ADDR_BYTE0 E8
# Enable DMA
WR          ADDR_SPI_CORE_1_GENERAL_DMA_3_REGISTERS_GENERAL_DMA_3_CONTROL0 01
# Write Next_RX bit
WRMASK      ADDR_SPI_CORE_1_GENERAL_DMA_3_REGISTERS_GENERAL_DMA_3_CONTROL1 02 02
# Wait for Completion
RDWAIT      ADDR_SPI_RXB2_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_17 07 07
# Disable DMA
WRMASK      ADDR_SPI_CORE_1_GENERAL_DMA_3_REGISTERS_GENERAL_DMA_3_CONTROL0 00 01
# Wait for LDO power up
WAIT        $LdoPowerUpWait$
# Set DMA debug flag
WRMASK      ADDR_SPI_RXB2_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_10 04 04 
RETURN     


# DMA Power up Config D (PLL Power Up)
STREAM      31
# Reset status register
WR          ADDR_SPI_RXB2_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_17 00
# Write Byte 0 of starting Address
WR          ADDR_SPI_CORE_1_GENERAL_DMA_3_REGISTERS_GENERAL_DMA_3_START_TABLE_ADDR_BYTE0 EC
# Enable DMA
WR          ADDR_SPI_CORE_1_GENERAL_DMA_3_REGISTERS_GENERAL_DMA_3_CONTROL0 01
# Write Next_RX bit
WRMASK      ADDR_SPI_CORE_1_GENERAL_DMA_3_REGISTERS_GENERAL_DMA_3_CONTROL1 02 02
# Wait for Completion
RDWAIT      ADDR_SPI_RXB2_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_17 07 07
# Disable DMA
WRMASK      ADDR_SPI_CORE_1_GENERAL_DMA_3_REGISTERS_GENERAL_DMA_3_CONTROL0 00 01   
# Set DMA debug flag
WRMASK      ADDR_SPI_RXB2_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_10 08 08  
RETURN


STREAM      32
RETURN

STREAM      33
RETURN

STREAM      34
RETURN

STREAM      35
RETURN

STREAM      36
RETURN

STREAM      37
RETURN

STREAM      38
RETURN

STREAM      39
RETURN

STREAM      3A
RETURN

STREAM      3B
RETURN

STREAM      3C
RETURN

STREAM      3D
RETURN

STREAM      3E
RETURN

STREAM      3F
RETURN
