# ########## MAIN STREAM ###########

# PLL phase sync
STREAM      0
# Write to LO phase sync control SPI register
RD          R0 ADDR_SPI_CORE_1_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_6
LD          R1 01
AND         R0 R1       # R0: 0 (LO1) or 1 (LO2)
LD          R1 200
MUL         R0 R1       # R0: 0x0000 or 0x0200
LD          R1 ADDR_SPI_RF1_PLL_LO_PH_SYNC_REGS_PSCTL0
ADD         R0 R1       # R0: 0x1C4F (LO1) or 0x1E4F (LO2)
WRD         R0 0B
# Wait for PLL phase sync
WAIT        $PllPhaseSyncWait$
RETURN


# Setup FH LO2
STREAM      1
WRMASK      ADDR_SPI_CORE_1_ANALOG_REGISTERS_RF2_EXTLO_BYTE11 00 08
WRMASK      ADDR_SPI_CORE_1_ANALOG_REGISTERS_RF2_EXTLO_BYTE8  08 08
RETURN


# Lock PLL retune
STREAM      2
# 'Lock' lo output power up by setting sw spare 4. This will be checked by stream in FH mode
WR          ADDR_SPI_CORE_1_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_4  01 
RETURN


STREAM      3
# Trigger DMA by writing next Tx event
WR          ADDR_SPI_CORE_DMA_REGISTERS_DMA_CONTROL1 01
# Wait for Completion
RDWAIT      ADDR_SPI_CORE_DMA_REGISTERS_DMA_STATUS_FLAGS 07 07
# Wait for VCO calibration
WAIT        $Pll1LockWait$
# Handle PLL phase sync if enabled
LD          R0 $PllPhaseSyncWait$
CONDCALL    00
# 'Unlock' lo output power up
WR          ADDR_SPI_CORE_1_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_4  00
RETURN


# Setup FH LO1
STREAM      4
WRMASK      ADDR_SPI_CORE_1_ANALOG_REGISTERS_RF1_EXTLO_BYTE11 00 08
WRMASK      ADDR_SPI_CORE_1_ANALOG_REGISTERS_RF1_EXTLO_BYTE8  08 08
RETURN


# RF PLL1 LOCK RISE (We repupose MAIN_INT_DELAY_ENABLE_PED_END_DELAY0 and MAIN_INT_DELAY_ENABLE_PED_START_DELAY0 for Mutex)
STREAM      5
# Poll RX2/TX2 register and wait for it to be free
RDWAIT      ADDR_SPI_CORE_2_PROGRAMMABLE_DELAYED_ENABLE_REGISTERS_MAIN_INT_DELAY_ENABLE_PED_END_DELAY0    00  01
# Write register to take "semaphore" and block STREAM 7
WR          ADDR_SPI_CORE_2_PROGRAMMABLE_DELAYED_ENABLE_REGISTERS_MAIN_INT_DELAY_ENABLE_PED_START_DELAY0  01
RETURN


STREAM      6
RETURN


# RF PLL2 LOCK RISE (We repupose MAIN_INT_DELAY_ENABLE_PED_END_DELAY0 and MAIN_INT_DELAY_ENABLE_PED_START_DELAY0 for Mutex)
STREAM      7
# Poll RX1/TX1 register and wait for it to be free
RDWAIT      ADDR_SPI_CORE_2_PROGRAMMABLE_DELAYED_ENABLE_REGISTERS_MAIN_INT_DELAY_ENABLE_PED_START_DELAY0  00  01
# Write register to take "semaphore" and block STREAM 5
WR          ADDR_SPI_CORE_2_PROGRAMMABLE_DELAYED_ENABLE_REGISTERS_MAIN_INT_DELAY_ENABLE_PED_END_DELAY0    01
RETURN


STREAM      8
RETURN


# AUX PLL LOCK RISE
STREAM      9
RETURN


STREAM      A
RETURN


# MONITOR RISE
STREAM      B
RETURN


# MONITOR FALL
STREAM      C
RETURN


# GP INTERRUPT RISE
STREAM      D
RETURN


# GPIO 0 ENABLE RISE
STREAM      E
RETURN


# GPIO 0 ENABLE FALL
STREAM      F
RETURN


# GPIO 1 ENABLE RISE
STREAM      10
RETURN


# GPIO 1 ENABLE FALL
STREAM      11
RETURN


# GPIO 2 ENABLE RISE
STREAM      12
RETURN


# GPIO 2 ENABLE FALL
STREAM      13
RETURN


# GPIO 3 ENABLE RISE
STREAM      14
RETURN


# GPIO 3 ENABLE FALL
STREAM      15
RETURN


# INT_DELAYED_ENABLE_RISE
STREAM      16
RETURN


# INT_DELAYED_ENABLE_FALL
STREAM      17
RETURN


# Hop_edge_0
STREAM      18
TIMEOUT     FFFF

# Start ARM hop edge process
INTERRUPT   01

# Set flag to indicate LO tune in progress
RD          R0 ADDR_SPI_CORE_1_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_5
CONDCALL    02

# Switch A/B registers
# Toggle main_hop_1_toggle and main_hop_2_toggle
RD          R0  ADDR_SPI_CORE_2_PROGRAMMABLE_DELAYED_ENABLE_REGISTERS_MAIN_ENABLE
LD          R1  03
XOR         R0  R1
WRA         R0  ADDR_SPI_CORE_2_PROGRAMMABLE_DELAYED_ENABLE_REGISTERS_MAIN_ENABLE

# LO Power down and DMA setup
RD          R0 ADDR_SPI_CORE_1_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_6
# Power down LO output for LO2 and set DMA start address
CONDCALL    01
LD          R1 01
XOR         R0 R1
# Power down LO output for LO1 and set DMA start address
CONDCALL    04

# If in LO Retune mode, start DMA
RD          R0 ADDR_SPI_CORE_1_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_5
CONDCALL    03

# Interrupt ARM 
INTERRUPT   02
RETURN


# Hop_edge_1
STREAM      19
RETURN     

  
# Hop_edge_2
STREAM      1A
RETURN


# Hop_edge_3
STREAM      1B
RETURN


STREAM      1C
RETURN


STREAM      1D
RETURN


STREAM      1E
RETURN


STREAM      1F
RETURN


STREAM      20
RETURN


STREAM      21
RETURN


STREAM      22
RETURN


STREAM      23
RETURN


STREAM      24
RETURN


STREAM      25
RETURN


STREAM      26
RETURN


STREAM      27
RETURN


STREAM      28
RETURN


STREAM      29
RETURN


STREAM      2A
RETURN


STREAM      2B
RETURN


STREAM      2C
RETURN


STREAM      2D
RETURN


STREAM      2E
RETURN


STREAM      2F
RETURN


STREAM      30
RETURN


STREAM      31
RETURN


STREAM      32
RETURN

STREAM      33
RETURN

STREAM      34
RETURN

STREAM      35
RETURN

STREAM      36
RETURN

STREAM      37
RETURN

STREAM      38
RETURN

STREAM      39
RETURN

STREAM      3A
RETURN

STREAM      3B
RETURN

STREAM      3C
RETURN

STREAM      3D
RETURN

STREAM      3E
RETURN

STREAM      3F
RETURN
