# ########## TX2 STREM ###########

# Set INT_TX_ENABLE bit high attached to delay enable with zero delay
STREAM      0
WRMASK      ADDR_SPI_TX2_CORE_PROGRAMMABLE_DELAYED_ENABLE_REGISTERS_TX_INT_DELAY_ENABLE 01 01
RETURN


# Set INT_TX_ENABLE bit low attached to delay enable with enableHold delay
STREAM      1
WRMASK      ADDR_SPI_TX2_CORE_PROGRAMMABLE_DELAYED_ENABLE_REGISTERS_TX_INT_DELAY_ENABLE 00 01
RETURN


# DMA Power up Config A (Pre-VCO Cal)
STREAM      2
# Write Byte 0 of starting Address
WR          ADDR_SPI_CORE_1_GENERAL_DMA_1_REGISTERS_GENERAL_DMA_1_START_TABLE_ADDR_BYTE0 24
# Enable DMA
WR          ADDR_SPI_CORE_1_GENERAL_DMA_1_REGISTERS_GENERAL_DMA_1_CONTROL0 01
# Write Next_TX bit
WRMASK      ADDR_SPI_CORE_1_GENERAL_DMA_1_REGISTERS_GENERAL_DMA_1_CONTROL1 01 01
# Wait for Completion
RDWAIT      ADDR_SPI_CORE_1_GENERAL_DMA_1_REGISTERS_GENERAL_DMA_1_STATUS_FLAGS 07 07
# Disable DMA
WRMASK      ADDR_SPI_CORE_1_GENERAL_DMA_1_REGISTERS_GENERAL_DMA_1_CONTROL0 00 01
# Wait for PLL lock
WAIT        $PllLockWait$
# Set DMA debug flag
WRMASK      ADDR_SPI_TX2_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_10 01 01
RETURN


# DMA Power up Config B (Post-VCO Cal and PLL Path Config and Power Up)
STREAM      3
# Write Byte 0 of starting Address
WR          ADDR_SPI_CORE_1_GENERAL_DMA_1_REGISTERS_GENERAL_DMA_1_START_TABLE_ADDR_BYTE0 28
# Enable DMA
WR          ADDR_SPI_CORE_1_GENERAL_DMA_1_REGISTERS_GENERAL_DMA_1_CONTROL0 01
# Write Next_TX bit
WRMASK      ADDR_SPI_CORE_1_GENERAL_DMA_1_REGISTERS_GENERAL_DMA_1_CONTROL1 01 01
# Wait for Completion
RDWAIT      ADDR_SPI_CORE_1_GENERAL_DMA_1_REGISTERS_GENERAL_DMA_1_STATUS_FLAGS 07 07
# Disable DMA
WRMASK      ADDR_SPI_CORE_1_GENERAL_DMA_1_REGISTERS_GENERAL_DMA_1_CONTROL0 00 01
# Set DMA debug flag and clear DMA debug flag from power down stream
WRMASK      ADDR_SPI_TX2_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_10 02 12
RETURN


# DMA Power Down Config (PLL path power down)    
STREAM      4
# Write Byte 0 of starting Address
WR          ADDR_SPI_CORE_1_GENERAL_DMA_1_REGISTERS_GENERAL_DMA_1_START_TABLE_ADDR_BYTE0 2C
# Enable DMA
WR          ADDR_SPI_CORE_1_GENERAL_DMA_1_REGISTERS_GENERAL_DMA_1_CONTROL0 01
# Write Next_TX bit
WRMASK      ADDR_SPI_CORE_1_GENERAL_DMA_1_REGISTERS_GENERAL_DMA_1_CONTROL1 01 01
# Wait for Completion
RDWAIT      ADDR_SPI_CORE_1_GENERAL_DMA_1_REGISTERS_GENERAL_DMA_1_STATUS_FLAGS 07 07
# Disable DMA
WRMASK      ADDR_SPI_CORE_1_GENERAL_DMA_1_REGISTERS_GENERAL_DMA_1_CONTROL0 00 01
# Set DMA debug flag and clear DMA debug flags from power up stream
WR          ADDR_SPI_TX2_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_10 10
RETURN


# TX Hop Edge
STREAM      5
TIMEOUT     FFFF
# Save TX attenuation/mode, change to SPI mode, ramp down
CALL        1F
# Mask DAC output
WRMASK      ADDR_SPI_TX2_CORE_TX_SSI_CONFIG_REGISTERS_TXDP_INTF_CONTROL C0 C0
# Power down TX LO mux buf
WRMASK      ADDR_SPI_CORE_1_ANALOG_REGISTERS_TX2_LO_REG 04 04
# Check if SOFTWARE_SPARE_7 is 1, call stream 2F.
RD          R0 ADDR_SPI_TX2_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_7
CONDCALL    2F
# TX ENABLE FALL DURING HOP MODE
CALL        0A
# Interrupt ARM: streamProc_tx2HopEdgeHandler()
INTERRUPT   04
RETURN


# TX Hop Edge During TX High
STREAM      6
RETURN


# TX Enable Rise
STREAM      7
# Assert SPI GPIO Bit 1 High
#WRMASK     ADDR_SPI_CORE_GPIO_1P8V_CONTROL_GPIO_1P8V_SPI_SOURCE_BYTE0 02 02
# Bypass stream 00 in Frequency Hopping mode
RD          R0 ADDR_SPI_CORE_1_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_0
LD          R1 01
XOR         R0 R1
CONDCALL    00              # Set INT_TX_ENABLE bit high
RETURN


# TX Enable Rise During Hop Mode
STREAM      8
RETURN


# TX Enable Fall
STREAM      9
# Assert SPI GPIO Bit 1 High
#WRMASK     ADDR_SPI_CORE_GPIO_1P8V_CONTROL_GPIO_1P8V_SPI_SOURCE_BYTE0 02 02
# Bypass stream 01 in Frequency Hopping mode
RD          R0 ADDR_SPI_CORE_1_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_0
LD          R1 01
XOR         R0 R1
CONDCALL    01              # Set INT_TX_ENABLE bit low
RETURN


# TX ENABLE FALL DURING HOP MODE
STREAM      0A
# Set INT_TX_ENABLE bit according to SOFTWARE_SPARE_7 attached to delay enable with zero delay
RD          R0 ADDR_SPI_TX2_CORE_PROGRAMMABLE_DELAYED_ENABLE_REGISTERS_TX_INT_DELAY_ENABLE
LD          R1 FE
AND         R0 R1
RD          R1 ADDR_SPI_TX2_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_7
OR          R0 R1
WRA         R0 ADDR_SPI_TX2_CORE_PROGRAMMABLE_DELAYED_ENABLE_REGISTERS_TX_INT_DELAY_ENABLE
RETURN


# ORX ENABLE RISE
STREAM      0B
RETURN


# TX GAIN CHANGE RISE
STREAM      0C
RETURN


# TX GAIN RAMP UP RISE
STREAM      0D
RETURN


# DDC LO SYNC RISE
STREAM      0E
RETURN


# NCO LO SYNC 0 RISE
STREAM      0F
RETURN


# NCO LO SYNC 1 RISE
STREAM      10
RETURN


# NCO LO SYNC 2 RISE
STREAM      11
RETURN


# ORX ENABLE FALL
STREAM      12
RETURN


# TX GAIN CHANGE FALL
STREAM      13
RETURN


# TX GAIN RAMPUP FALL
STREAM      14
RETURN


# INT_TX_DELAYED_ENABLE RISE (Enable TX digital, Power up LDO, PLL if Power Savings Mode > 0)
STREAM      15
TIMEOUT     FFFF
# Set int_delay_0_enable bit attached to delay enable with txEnableRiseToAnalogOnDelay
# Set int_delay_1_enable bit attached to delay enable with txEnableRiseToOnDelay
WRMASK      ADDR_SPI_TX2_CORE_PROGRAMMABLE_DELAYED_ENABLE_REGISTERS_TX_INT_DELAY_ENABLE 06 06 
# Trigger StreamProc1Int3_Handler() in ARM
#INTERRUPT   08
# Enable datapath clocks
WR          ADDR_SPI_TX2_CORE_TX_DATAPATH_CONFIG_ALL_TX_ENABLE 01
# Unmask interface to datapath
WR          ADDR_SPI_TX2_CORE_TX_SSI_CONFIG_REGISTERS_TXDP_INTF_CONTROL C0
RD          R0 ADDR_SPI_TX2_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_4
CONDCALL    30              # Call LDO Power Up stream
RD R0 ADDR_SPI_TX2_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_5
CONDCALL    31              # Call PLL Power Up stream
$IfNoTx2FMDM$ RD          R0 ADDR_SPI_TX2_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_5
$IfNoTx2FMDM$ CONDCALL    1D              # Call TX DAC Bias power up txPathConfig_Powerup
$IfTx2IntLo$ RD R0  ADDR_SPI_TX2_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_6
$IfTx2IntLo$ CONDCALL 02    # Call PLL retune Pre VCO cal stream
RETURN


# INT_DELAYED_0_ENABLE RISE (Power up TX analog)
STREAM      16
TIMEOUT     FFFF
$IfTx2IntLo$ RD R0  ADDR_SPI_TX2_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_1
$IfTx2IntLo$ CONDCALL 02    # Call PLL retune Pre VCO cal stream
# Bypass stream 03 in Frequency Hopping mode
RD          R0 ADDR_SPI_CORE_1_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_0
LD          R1 01
XOR         R0 R1
CONDCALL    03              # Call PLL Post VCO cal stream, LO mux, LO gen, LO path power up
$IfNoTx2FMDM$ CALL 1B       # TX IQ power up substreams
$IfTx2FMDM$   CALL 1C       # TX FMDM power up substream
# Bypass stream 1E in Frequency Hopping mode
RD          R0 ADDR_SPI_CORE_1_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_0
LD          R1 01
XOR         R0 R1
CONDCALL    1E
# Interrupt ARM: streamProc_tx2EnableRiseHandler()
INTERRUPT   01
RETURN


# INT_DELAYED_1_ENABLE RISE ( Set TX antenna switch)
STREAM      17
# Assert SPI GPIO Bit 1 Low
#WRMASK     ADDR_SPI_CORE_GPIO_1P8V_CONTROL_GPIO_1P8V_SPI_SOURCE_BYTE0 00 02
RETURN


# INT_TX_DELAYED_ENABLE FALL (Disable tracking calibration, TX digital datapath, interface)
STREAM      18
# Reset int_delay_0_enable bit attached to delay enable with txEnableFallToOffDelay - txEnableHoldDelay + 1
# Reset int_delay_1_enable bit attached to delay enable with txEnableFallToOffDelay - txEnableHoldDelay
WR          ADDR_SPI_TX2_CORE_PROGRAMMABLE_DELAYED_ENABLE_REGISTERS_TX_INT_DELAY_ENABLE 00 
# Disable TX Calibrations (DPD, QEC/LOL, CLGC RSSI/CC, GAN RSSI/CC)
WR          ADDR_SPI_TX2_CORE_PROGRAMMABLE_DELAYED_ENABLE_REGISTERS_TX_HW_DELAY_ENABLE 00
# Disable RX calibrations
WR          ADDR_SPI_RX2_CORE_PROGRAMMABLE_DELAYED_ENABLE_REGISTERS_HW_DELAY_ENABLE_0 00
WR          ADDR_SPI_RX2_CORE_PROGRAMMABLE_DELAYED_ENABLE_REGISTERS_HW_DELAY_ENABLE_1 00
# Mask interface from datapath
WRMASK      ADDR_SPI_TX2_CORE_TX_SSI_CONFIG_REGISTERS_TXDP_INTF_CONTROL 30 30
# Trigger StreamProc1Int2_Handler() in ARM
#INTERRUPT   04
RETURN


# INT_DELAYED_0_ENABLE FALL (Power down TX analog) (ported from ARM txPathConfig_StreamPowerDown())
STREAM      19
$IfNoTx2FMDM$ TIMEOUT 0FFF
$IfTx2FMDM$   TIMEOUT FFFF # In A0 TX atten clock is much slower in FM-DM mode, thus TX atten ramp is slower
# Mask datapath from analog
WRMASK      ADDR_SPI_TX2_CORE_TX_SSI_CONFIG_REGISTERS_TXDP_INTF_CONTROL F0 F0
# Bypass stream 1F in Frequency Hopping mode
RD          R0 ADDR_SPI_CORE_1_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_0
LD          R1 01
XOR         R0 R1
CONDCALL    1F              # Save TX attenuation/mode, change to SPI mode, ramp down
# Restore saved TX attenuation (NOTE: Must write the MSB first. Otherwise, the value won't latch)
RD          R0  ADDR_SPI_TX2_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_3
WRA         R0  ADDR_SPI_TX2_CORE_TX_POWER_CONTROL_ATTENUATION_REGISTERS_TX_ATTENUATION_SPI_MODE_1
RD          R0  ADDR_SPI_TX2_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_2
WRA         R0  ADDR_SPI_TX2_CORE_TX_POWER_CONTROL_ATTENUATION_REGISTERS_TX_ATTENUATION_SPI_MODE_0
# Power down pre-distorter, LO delay block ( buffer) and LO delay block (DAC)
WR          ADDR_SPI_TX2_ANA_POWER_DOWN_REGISTERS_TX_PD 76
# Power down upconverter
WR          ADDR_SPI_TX2_ANA_POWER_DOWN_REGISTERS_TX_PD 7E
# Power down the TXBBAF
WR          ADDR_SPI_TX2_ANA_POWER_DOWN_REGISTERS_TX_PD 7F
# Wait for 80ns
WAIT        $Delay_80ns$
# Wait for 80ns
WAIT        $Delay_80ns$
# Disable TX LO mux buf (removed because it's handled in DMA)
#WRMASK     ADDR_SPI_CORE_1_ANALOG_REGISTERS_TX2_LO_REG 04 04
#WR         ADDR_SPI_CORE_1_ANALOG_REGISTERS_TX2_LO_REG 07
# Disable TX LO Line recv buf
WRMASK      ADDR_SPI_TX2_ANA_POWER_DOWN_REGISTERS_LO_LINE_TERMINATION_CONTROL 04 04
#WR         ADDR_SPI_TX2_ANA_POWER_DOWN_REGISTERS_LO_LINE_TERMINATION_CONTROL 0C
# Wait for 80ns
WAIT        $Delay_80ns$
# Disable TX DAC top level clock
WR          ADDR_SPI_TX2_CORE_CLOCK_CONTROL_REGISTERS_CLOCK_CONTROL_4 00
# Toggle Datapath Reset
WRMASK      ADDR_SPI_TX2_CORE_TX_DATAPATH_CONFIG_TX_DP_RESET 01 01
WRMASK      ADDR_SPI_TX2_CORE_TX_DATAPATH_CONFIG_TX_DP_RESET 00 01
# Disable datapath clocks
WR          ADDR_SPI_TX2_CORE_TX_DATAPATH_CONFIG_ALL_TX_ENABLE 00
CALL        04                  # Power down PLL path
# Interrupt ARM: streamProc_tx2EnableFallHandler()
INTERRUPT   02
RETURN


# INT_DELAYED_1_ENABLE FALL (Reset TX antenna switch)
STREAM      1A
# Assert SPI GPIO Bit 1 Low
#WRMASK     ADDR_SPI_CORE_GPIO_1P8V_CONTROL_GPIO_1P8V_SPI_SOURCE_BYTE0 00 02
RETURN


# TX Power Up IQ mode (ported from ARM txPathConfig_StreamPowerUp())
STREAM      1B
TIMEOUT     0FFF
# Power up the DAC ( excluding DAC Bias)
WR          ADDR_SPI_TX2_DAC_TX_DAC_POWERDOWN_TXDAC_PWRDOWN_1 00
# Power Up the TXBBAF and upconverter
WR          ADDR_SPI_TX2_ANA_POWER_DOWN_REGISTERS_TX_PD 76
# Wait for 80 ns
WAIT        $Delay_80ns$
# Enable Top DAC clks
WR          ADDR_SPI_TX2_CORE_CLOCK_CONTROL_REGISTERS_CLOCK_CONTROL_4 80
# Wait for 80 ns
WAIT        $Delay_80ns$
# Enable TX LO Line recv buf
WRMASK      ADDR_SPI_TX2_ANA_POWER_DOWN_REGISTERS_LO_LINE_TERMINATION_CONTROL 00 04
#WR         ADDR_SPI_TX2_ANA_POWER_DOWN_REGISTERS_LO_LINE_TERMINATION_CONTROL 08
# Enable TX LO mux buf (removed because it's handled in DMA)
#WRMASK     ADDR_SPI_CORE_1_ANALOG_REGISTERS_TX2_LO_REG 00 04
#WR         ADDR_SPI_CORE_1_ANALOG_REGISTERS_TX2_LO_REG 02
# Wait for 80ns
WAIT        $Delay_80ns$
# Wait for 80ns
WAIT        $Delay_80ns$
# Power up LO delay block (DAC) and LO delay block (buffer)
WR          ADDR_SPI_TX2_ANA_POWER_DOWN_REGISTERS_TX_PD 16
# Wait for 80ns
WAIT        $Delay_80ns$
# Power up pre-distorter
WR          ADDR_SPI_TX2_ANA_POWER_DOWN_REGISTERS_TX_PD 12
RETURN


# TX Power Up DM Mode (ported from ARM txPredistorter_PowerUpDmMode())
STREAM      1C
TIMEOUT     FFFF
# Power up bias current distribution
WRMASK      ADDR_SPI_TX2_ANA_POWER_DOWN_REGISTERS_IDIST_CONTROL 00 01
# Configure Pre-distorter as a driver
WRMASK      ADDR_SPI_TX2_ANA_POWER_DOWN_REGISTERS_TX_PD2 01 01
# Increase bias current for 9dBm output power
WRMASK      ADDR_SPI_TX2_ANA_TX_UPCONVERTER_REGISTERS_TX_UPCONV_CONFIG0 03 03
# Enable TX LO Line recv buf
WRMASK      ADDR_SPI_TX2_ANA_POWER_DOWN_REGISTERS_LO_LINE_TERMINATION_CONTROL 00 04
# Enable TX LO mux buf (removed because it's handled in DMA)
#WRMASK     ADDR_SPI_CORE_1_ANALOG_REGISTERS_TX2_LO_REG 00 04
# Power up upconverter, lo delay (DAC, buffers), pre-distorter
WR          ADDR_SPI_TX2_ANA_POWER_DOWN_REGISTERS_TX_PD 13
RETURN

# TX Power Up IQ mode (ported from ARM txPathConfig_Powerup())
STREAM      1D
TIMEOUT     FFFF
# Assume TX Attenuator is in ramp down state
# Enable TXDAC top level clock 
WRMASK      ADDR_SPI_TX2_CORE_CLOCK_CONTROL_REGISTERS_CLOCK_CONTROL_4 80 80
# txDac_Powerup
# WRITE_TXDAC_MEM_MAP_TXDAC_THROW_LSB_CTRL(base, 1u);
WRMASK      ADDR_SPI_TX2_DAC_TX_DAC_THROW_CONTROL_TXDAC_THROW_CTRL 01 03
# WRITE_TXDAC_MEM_MAP_TXDAC_THROW_ISB_CTRL(base, 1u);
WRMASK      ADDR_SPI_TX2_DAC_TX_DAC_THROW_CONTROL_TXDAC_THROW_CTRL 04 0C
# Wait for Supply/Clocks Ready
RDWAIT      ADDR_SPI_TX2_DAC_TX_DAC_POWERDOWN_TXDAC_PWRDOWN_3 80 80
# Power up the DACs
WRMASK      ADDR_SPI_TX2_DAC_TX_DAC_POWERDOWN_TXDAC_PWRDOWN_1 00 E0
# Wait for DAC power-up (17-35us),  bit 3 power up state I
RDWAIT      ADDR_SPI_TX2_DAC_TX_DAC_POWERDOWN_TXDAC_PWRDOWN_1 08 08
# bit 1 power up state Q
RDWAIT      ADDR_SPI_TX2_DAC_TX_DAC_POWERDOWN_TXDAC_PWRDOWN_1 02 02
# Increase DAC fullscale range by 2x to give the calibration more range to correct DAC errors
WRMASK      ADDR_SPI_TX2_DAC_TX_DAC_CALIBRATION_TXDAC_CALIBRATION_6 03 03
RETURN


# Ramp Up TX attenuator, restore TX attenuation mode and unmask DAC
STREAM      1E
# Ramp Up TX attenuator
WR          ADDR_SPI_TX2_CORE_TX_POWER_CONTROL_ATTENUATION_REGISTERS_TDD_RAMP 01
# Wait for ramp up to complete
RDWAIT      ADDR_SPI_TX2_CORE_TX_POWER_CONTROL_ATTENUATION_REGISTERS_TDD_RAMP 00 01
# Restore saved TX attenuation mode
RD          R0  ADDR_SPI_TX2_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_9
WRA         R0  ADDR_SPI_TX2_CORE_TX_POWER_CONTROL_ATTENUATION_REGISTERS_TX_TPC_CONFIG
# Unmask DAC
WR          ADDR_SPI_TX2_CORE_TX_SSI_CONFIG_REGISTERS_TXDP_INTF_CONTROL 00
RETURN


# Save TX attenuation/mode, change to SPI mode, ramp down
STREAM      1F
# Save current TX attenuation
WR          ADDR_SPI_TX2_CORE_TX_ATTENUATION_READ_REGISTERS_TX_ATTENUATION_0_READBACK   00
RD          R0  ADDR_SPI_TX2_CORE_TX_ATTENUATION_READ_REGISTERS_TX_ATTENUATION_0_READBACK
WRA         R0  ADDR_SPI_TX2_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_2
RD          R0  ADDR_SPI_TX2_CORE_TX_ATTENUATION_READ_REGISTERS_TX_ATTENUATION_1_READBACK
WRA         R0  ADDR_SPI_TX2_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_3
# Save current TX attenuation mode
RD          R0  ADDR_SPI_TX2_CORE_TX_POWER_CONTROL_ATTENUATION_REGISTERS_TX_TPC_CONFIG
LD          R1  F7              # keep fifo_overflow bit to 0
AND         R0  R1
WRA         R0  ADDR_SPI_TX2_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_9
# Change current TX attenuation mode to SPI mode
WRMASK      ADDR_SPI_TX2_CORE_TX_POWER_CONTROL_ATTENUATION_REGISTERS_TX_TPC_CONFIG  01  03
# Ramp Down TX attenuator
WR          ADDR_SPI_TX2_CORE_TX_POWER_CONTROL_ATTENUATION_REGISTERS_TDD_RAMP 02
# Wait for ramp down to complete
RDWAIT      ADDR_SPI_TX2_CORE_TX_POWER_CONTROL_ATTENUATION_REGISTERS_TDD_RAMP 00 02
RETURN

STREAM      20
RETURN

STREAM      21
RETURN

STREAM      22
RETURN

STREAM      23
RETURN

STREAM      24
RETURN

STREAM      25
RETURN

STREAM      26
RETURN

STREAM      27
RETURN

STREAM      28
RETURN

STREAM      29
RETURN

STREAM      2A
RETURN

STREAM      2B
RETURN

STREAM      2C
RETURN

STREAM      2D
RETURN

STREAM      2E
RETURN


# To be called by TX Hop Edge Stream 5
STREAM      2F
# DMA Power up Config B (Post-VCO Cal and PLL Path Config and Power Up)
CALL        03
# Ramp up tx attenuator and interrupt ARM
CALL 1E
RETURN


# DMA Power up Config C (LDO Power Up)
STREAM      30
# Write Byte 0 of starting Address
WR          ADDR_SPI_CORE_1_GENERAL_DMA_1_REGISTERS_GENERAL_DMA_1_START_TABLE_ADDR_BYTE0 48
# Enable DMA
WR          ADDR_SPI_CORE_1_GENERAL_DMA_1_REGISTERS_GENERAL_DMA_1_CONTROL0 01
# Write Next_TX bit
WRMASK      ADDR_SPI_CORE_1_GENERAL_DMA_1_REGISTERS_GENERAL_DMA_1_CONTROL1 01 01
# Wait for Completion
RDWAIT      ADDR_SPI_CORE_1_GENERAL_DMA_1_REGISTERS_GENERAL_DMA_1_STATUS_FLAGS 07 07
# Disable DMA
WRMASK      ADDR_SPI_CORE_1_GENERAL_DMA_1_REGISTERS_GENERAL_DMA_1_CONTROL0 00 01
# Wait for LDO power up
WAIT        $LdoPowerUpWait$
# Set DMA debug flag
WRMASK      ADDR_SPI_TX2_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_10 04 04
RETURN


# DMA Power up Config D (PLL Power Up)  
STREAM      31
# Write Byte 0 of starting Address
WR          ADDR_SPI_CORE_1_GENERAL_DMA_1_REGISTERS_GENERAL_DMA_1_START_TABLE_ADDR_BYTE0 4C
# Enable DMA
WR          ADDR_SPI_CORE_1_GENERAL_DMA_1_REGISTERS_GENERAL_DMA_1_CONTROL0 01
# Write Next_TX bit
WRMASK      ADDR_SPI_CORE_1_GENERAL_DMA_1_REGISTERS_GENERAL_DMA_1_CONTROL1 01 01
# Wait for Completion
RDWAIT      ADDR_SPI_CORE_1_GENERAL_DMA_1_REGISTERS_GENERAL_DMA_1_STATUS_FLAGS 07 07
# Disable DMA
WRMASK      ADDR_SPI_CORE_1_GENERAL_DMA_1_REGISTERS_GENERAL_DMA_1_CONTROL0 00 01  
# Set DMA debug flag
WRMASK      ADDR_SPI_TX2_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_10 08 08 
RETURN
