# ########## RX1 STREM ###########

# Set INT_RX_ENABLE bit high attached to delay enable with enableRiseToAnalogOnDelay
STREAM      0
# Set INT_RX_ENABLE high
WRMASK      ADDR_SPI_RX1_CORE_PROGRAMMABLE_DELAYED_ENABLE_REGISTERS_RX_INT_DELAY_ENABLE 02 02
RD          R0 ADDR_SPI_RXB1_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_4
CONDCALL    30                  # Call LDO Power Up stream
RD          R0 ADDR_SPI_RXB1_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_5
CONDCALL    31                  # Call PLL Power Up stream
$IfRx1IntLo$ RD R0 ADDR_SPI_RXB1_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_6
$IfRx1IntLo$ CONDCALL 02        # Call PLL retune Pre VCO cal stream
RETURN


# Set INT_RX_ENABLE bit low attached to delay enable with enableFallToOffDelay
STREAM      1
WRMASK      ADDR_SPI_RX1_CORE_PROGRAMMABLE_DELAYED_ENABLE_REGISTERS_RX_INT_DELAY_ENABLE 00 02
RETURN


# DMA Power up Config A (Pre-VCO Cal)
STREAM      2
# Write Byte 0 of starting Address
WR          ADDR_SPI_CORE_1_GENERAL_DMA_2_REGISTERS_GENERAL_DMA_2_START_TABLE_ADDR_BYTE0 00
# Enable DMA
WR          ADDR_SPI_CORE_1_GENERAL_DMA_2_REGISTERS_GENERAL_DMA_2_CONTROL0 01
# Write Next_RX bit
WRMASK      ADDR_SPI_CORE_1_GENERAL_DMA_2_REGISTERS_GENERAL_DMA_2_CONTROL1 02 02
# Wait for Completion
RDWAIT      ADDR_SPI_CORE_1_GENERAL_DMA_2_REGISTERS_GENERAL_DMA_2_STATUS_FLAGS 07 07
# Disable DMA
WRMASK      ADDR_SPI_CORE_1_GENERAL_DMA_2_REGISTERS_GENERAL_DMA_2_CONTROL0 00 01
# Wait for PLL lock
WAIT        $PllLockWait$
# Set DMA debug flag
WRMASK      ADDR_SPI_RXB1_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_10 01 01
RETURN


# DMA Power up Config B (Post-VCO Cal and PLL Path Config and Power Up)
STREAM      3
# Write Byte 0 of starting Address
WR          ADDR_SPI_CORE_1_GENERAL_DMA_2_REGISTERS_GENERAL_DMA_2_START_TABLE_ADDR_BYTE0 04
# Enable DMA
WR          ADDR_SPI_CORE_1_GENERAL_DMA_2_REGISTERS_GENERAL_DMA_2_CONTROL0 01
# Write Next_RX bit
WRMASK      ADDR_SPI_CORE_1_GENERAL_DMA_2_REGISTERS_GENERAL_DMA_2_CONTROL1 02 02
# Wait for Completion
RDWAIT      ADDR_SPI_CORE_1_GENERAL_DMA_2_REGISTERS_GENERAL_DMA_2_STATUS_FLAGS 07 07
# Disable DMA
WRMASK      ADDR_SPI_CORE_1_GENERAL_DMA_2_REGISTERS_GENERAL_DMA_2_CONTROL0 00 01
# Set DMA debug flag and clear DMA debug flag from power down stream
WRMASK      ADDR_SPI_RXB1_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_10 02 12
RETURN


# DMA Power Down Config (PLL path power down)    
STREAM      4
# Write Byte 0 of starting Address
WR          ADDR_SPI_CORE_1_GENERAL_DMA_2_REGISTERS_GENERAL_DMA_2_START_TABLE_ADDR_BYTE0 08
# Enable DMA
WR          ADDR_SPI_CORE_1_GENERAL_DMA_2_REGISTERS_GENERAL_DMA_2_CONTROL0 01
# Write Next_RX bit
WRMASK      ADDR_SPI_CORE_1_GENERAL_DMA_2_REGISTERS_GENERAL_DMA_2_CONTROL1 02 02
# Wait for Completion
RDWAIT      ADDR_SPI_CORE_1_GENERAL_DMA_2_REGISTERS_GENERAL_DMA_2_STATUS_FLAGS 07 07
# Disable DMA
WRMASK      ADDR_SPI_CORE_1_GENERAL_DMA_2_REGISTERS_GENERAL_DMA_2_CONTROL0 00 01   
# Set DMA debug flag and clear DMA debug flags from power up stream
WR          ADDR_SPI_RXB1_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_10 10
RETURN


# RX Hop Edge
STREAM      5
TIMEOUT     FFFF
# Mask ADC output
WRMASK      ADDR_SPI_RX1_CORE_RX_DATAPATH_CONFIG_RX_DATAPATH_FORCE_ZERO 01 01
# Disable RX algorithms
CALL        19
# Power down RX LO mux buffer
WRMASK      ADDR_SPI_CORE_1_ANALOG_REGISTERS_RX1_LO_REG 04 04
# Check if SOFTWARE_SPARE_7 is 1, call stream 2F.
RD          R0 ADDR_SPI_RXB1_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_7
CONDCALL    2F
# RX ENABLE FALL DURING HOP MODE
CALL        0A
# Interrupt ARM: streamProc_rx1HopEdgeHandler()
INTERRUPT   08
RETURN


# RX Hop Edge During RX High
STREAM      6
RETURN


# RX ENABLE RISE STREAM
STREAM      7
TIMEOUT     FFFF
#WR         ADDR_SPI_RXB1_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_11 01
# Assert SPI GPIO Bit 2 High
#WRMASK     ADDR_SPI_CORE_GPIO_1P8V_CONTROL_GPIO_1P8V_SPI_SOURCE_BYTE0 04 04
# Bypass stream 00 in Frequency Hopping mode
RD          R0 ADDR_SPI_CORE_1_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_0
LD          R1 01
XOR         R0 R1
CONDCALL    00              # Set INT_RX_ENABLE bit high
RETURN


# RX ENABLE RISE DURING HOP MODE STREAM
STREAM      8
RETURN


# RX ENABLE FALL STREAM
STREAM      9
#WR         ADDR_SPI_RXB1_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_11 10
# Assert SPI GPIO Bit 2 High
#WRMASK     ADDR_SPI_CORE_GPIO_1P8V_CONTROL_GPIO_1P8V_SPI_SOURCE_BYTE0 04 04
# Bypass stream 01 in Frequency Hopping mode
RD          R0 ADDR_SPI_CORE_1_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_0
LD          R1 01
XOR         R0 R1
CONDCALL    01              # Set INT_RX_ENABLE bit low
RETURN


# RX ENABLE FALL DURING HOP MODE
STREAM      0A
# Set INT_RX_ENABLE bit according to SOFTWARE_SPARE_7 attached to delay enable with zero delay
RD          R0 ADDR_SPI_RX1_CORE_PROGRAMMABLE_DELAYED_ENABLE_REGISTERS_RX_INT_DELAY_ENABLE
LD          R1 FD
AND         R0 R1
RD          R1 ADDR_SPI_RXB1_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_7
OR          R0 R1
WRA         R0 ADDR_SPI_RX1_CORE_PROGRAMMABLE_DELAYED_ENABLE_REGISTERS_RX_INT_DELAY_ENABLE
RETURN


# ORX ENABLE RISE STREAM
STREAM      0B
# Interrupt ARM: streamProc_orx1EnableRiseHandler()
INTERRUPT   04
RETURN


# EXT LOOPBACK RISE STREAM
STREAM      0C
RETURN


# INT LOOPBACK RISE STREAM
STREAM      0D
RETURN


# ORX ENABLE FALL STREAM
STREAM      0E
# Set generic interrupt spare register bit
WRMASK      ADDR_SPI_RXB1_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_8 02 02
# Interrupt ARM: streamProc_rx1GenericStreamHandler()
INTERRUPT   02
RETURN


# EXT LOOPBACK FALL STREAM
STREAM      0F
RETURN


# INT LOOPBACK FALL STREAM
STREAM      10
RETURN


# RX_INT_DELAYED1_ENABLE RISE (SPI BIT) (Set LNA power up GPIO pin)
STREAM      11
#WRMASK     ADDR_SPI_RXB1_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_11 08 08
# Assert SPI GPIO Bit 2 Low
#WRMASK     ADDR_SPI_CORE_GPIO_1P8V_CONTROL_GPIO_1P8V_SPI_SOURCE_BYTE0 00 04
RETURN


# INT_ORX_DELAYED_ENABLE RISE (SPI_BIT)
STREAM      12
RETURN


# RX_INT_DELAYED0_ENABLE RISE (SPI BIT)
STREAM      13
# Unmask datapath from interface
WR          ADDR_SPI_RX1_CORE_RX_DATAPATH_CONFIG_RX_DATAPATH_FORCE_ZERO 00
# Reset SCIC (ADRV9003-1374)
WRMASK      ADDR_SPI_RX1_CORE_RX_NBFIC_REGISTERS_RX_ALG_NBFIC_OBS_SCIC_RESET 01 01
WRMASK      ADDR_SPI_RX1_CORE_RX_NBFIC_REGISTERS_RX_ALG_NBFIC_OBS_SCIC_RESET 00 01
CALL        25              # Enable algorithms
# Interrupt ARM: streamProc_rx1EnableRiseHandler()
INTERRUPT   01
#WRMASK     ADDR_SPI_RXB1_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_11 04 04
RETURN


#INT_RX_DELAYED_ENABLE RISE (SPI BIT)
STREAM      14
TIMEOUT     FFFF
# Set bit int_delay_1_enable attached to delay enable with rxEnableRiseToOnDelay - rxEnableRiseToAnaOnDelay
WRMASK      ADDR_SPI_RX1_CORE_PROGRAMMABLE_DELAYED_ENABLE_REGISTERS_RX_INT_DELAY_ENABLE 08 08
#INTERRUPT   10
$IfRx1IntLo$ RD R0 ADDR_SPI_RXB1_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_1
$IfRx1IntLo$ CONDCALL 02        # Call PLL retune Pre VCO cal stream
# Bypass stream 03 in Frequency Hopping mode
RD          R0 ADDR_SPI_CORE_1_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_0
LD          R1 01
XOR         R0 R1
CONDCALL    03                  # Call PLL Post VCO cal stream, LO mux, LO gen, LO path power up
# Enable magnitude compensation PFIR
WRMASK      ADDR_SPI_RX1_CORE_RX_DATAPATH_CONFIG_RX_NBDEM_ENABLE_1 04 04
# Enable the HP ADC and LP ADC clocks
WRMASK      ADDR_SPI_CORE_1_ANALOG_SPARE_REGISTERS_ANALOG_SPARE_REG_8 00 03
# Enable the Clock Gen Output Buffer
WR          ADDR_SPI_RX1_CORE_CHANNEL_CONFIGURATION_RX_CLOCK_CONFIG_0 01
# Enable positive and negatve phase of the data clock
WRMASK      ADDR_SPI_CORE_1_ANALOG_SPARE_REGISTERS_ANALOG_SPARE_REG_1 07 07
$IfRx1A$    CALL 1C             # Power up RX1A FE
$IfNoRx1A$  CALL 1D             # Power up RX1B FE
# Power up TIA
WR          ADDR_SPI_RX1_ANA_POWER_DOWN_REGISTERS_ORX_PD 00
# Read ADC_Switching flag
RD          R0 ADDR_SPI_RXB1_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_9
CONDCALL    20                  # Power up HP ADC
# Toggle the value in R0
LD          R1 01
XOR         R0 R1
CONDCALL    21                  # else, Power up LP ADC
# Select PFIR Bank to BANK A
WRMASK      ADDR_SPI_CORE_MAG_CONFIG_MAG_SEL0 00 30
# Read PFIR Bank in use (could change dynamically) and select bank appropriately
RD          R1 ADDR_SPI_RXB1_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_3
WRA         R1 ADDR_SPI_CORE_RX1_DATAPATH_CONFIG_CORE_RX1_PFIR_MODE_MAPPING
#Enable QEC Clocks
WRMASK      ADDR_SPI_CORE_2_CORE_RXQEC_REGISTERS_CORE_RXQEC_CONTROL0 40 40
# Select RX datapath  Profile 
WRMASK      ADDR_SPI_RX1_CORE_RX_DATAPATH_CONFIG_ORX_PROFILE_SEL 00 01
# Enable datapath clocks
WR          ADDR_SPI_RX1_CORE_RX_DATAPATH_CONFIG_ALL_RX_ENABLE 01
# Power up RX mixer LO buffer
WR          ADDR_SPI_RX1_ANA_POWER_DOWN_REGISTERS_ORX1_PD 00
# Flush datapath filters inside RXQEC block
WRMASK      ADDR_SPI_CORE_RX_QEC_REGISTERS_RXQEC_SW_RESET 01 01
WRMASK      ADDR_SPI_CORE_RX_QEC_REGISTERS_RXQEC_SW_RESET 00 01
# Wait 3us for analog to settle
WAIT        $Delay_1us$
WAIT        $Delay_1us$
WAIT        $Delay_1us$
CALL        24                  # Configure algorithms
# Bypass stream 26 in Frequency Hopping mode
RD          R0 ADDR_SPI_CORE_1_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_0
LD          R1 01
XOR         R0 R1
CONDCALL    26
RETURN


#INT_RX_DELAYED_ENABLE FALL (SPI BIT)
STREAM      15
TIMEOUT     0FFF
# Assert SPI GPIO Bit 2 Low
#WRMASK     ADDR_SPI_CORE_GPIO_1P8V_CONTROL_GPIO_1P8V_SPI_SOURCE_BYTE0 00 04
# Reset bit int_delay_0_enable and int_delay_1_enable
WRMASK      ADDR_SPI_RX1_CORE_PROGRAMMABLE_DELAYED_ENABLE_REGISTERS_RX_INT_DELAY_ENABLE 00 0C
#INTERRUPT   20
# Mask ADC from datapath
WR          ADDR_SPI_RX1_CORE_RX_DATAPATH_CONFIG_RX_DATAPATH_FORCE_ZERO 01
# Disable magnitude compensation PFIR
WRMASK      ADDR_SPI_RX1_CORE_RX_DATAPATH_CONFIG_RX_NBDEM_ENABLE_1 00 04
CALL        19                  # Disable RX algorithms
# Read ADC_Switching flag
RD          R0 ADDR_SPI_RXB1_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_9
CONDCALL    22                  # Power down HP ADC
# Toggle the value in R0
LD          R1 01
XOR         R0 R1
CONDCALL    23                  # else, Power down LP ADC 
$IfRx1A$    CALL 1E             # Power down RX1A FE
$IfNoRx1A$  CALL 1F             # Power down RX1B FE
# Power down TIA
WR          ADDR_SPI_RX1_ANA_POWER_DOWN_REGISTERS_ORX_PD 07
#Disable RX QEC clocks
WRMASK      ADDR_SPI_CORE_2_CORE_RXQEC_REGISTERS_CORE_RXQEC_CONTROL0 00 40
# Disable the HP ADC and LPADC clocks
WRMASK      ADDR_SPI_CORE_1_ANALOG_SPARE_REGISTERS_ANALOG_SPARE_REG_8 03 03
# Disable the Clock Gen Output Buffer
WR          ADDR_SPI_RX1_CORE_CHANNEL_CONFIGURATION_RX_CLOCK_CONFIG_0 00
# Disable positive and negative phase of the data clock
WRMASK      ADDR_SPI_CORE_1_ANALOG_SPARE_REGISTERS_ANALOG_SPARE_REG_1 00 07 
CALL        04                  # DMA Power Down PLL path
#WRMASK     ADDR_SPI_RXB1_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_11 20 20
RETURN 


# INT_ORX_DELAYED_ENABLE RISE (SPI BIT)
STREAM      16
RETURN


# RX_INT_DELAYED0_ENABLE FALL (SPI_BIT)
STREAM      17
# Mask datapath from interface
WR          ADDR_SPI_RX1_CORE_RX_DATAPATH_CONFIG_RX_DATAPATH_FORCE_ZERO 11
# Toggle Global Reset
WRMASK      ADDR_SPI_RX1_CORE_RX_DATAPATH_CONFIG_RX_DP_RESET 01 01
WRMASK      ADDR_SPI_RX1_CORE_RX_DATAPATH_CONFIG_RX_DP_RESET 00 01
# Disable RX datapath clock
WR          ADDR_SPI_RX1_CORE_RX_DATAPATH_CONFIG_ALL_RX_ENABLE 00
# Set generic interrupt spare register bit
WRMASK      ADDR_SPI_RXB1_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_8 01 01
# Interrupt ARM: streamProc_rx1GenericStreamHandler()
INTERRUPT   02
#WRMASK     ADDR_SPI_RXB1_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_11 40 40
RETURN


# RX_INT_DELAYED1_ENABLE FALL (SPI_BIT)
STREAM      18
#WRMASK     ADDR_SPI_RXB1_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_11 80 80
RETURN   


# Disable RX Algorithms
STREAM      19
# Mask BBDC
WR          ADDR_SPI_RXB1_CORE_DIGITAL_DC_OFFSET_CONTROL_REGISTERS_DIGITAL_DC_OFFSET_DECIMATE 21 
# Disable BBDC, RFDC, AGC, RSSI  
WR          ADDR_SPI_RX1_CORE_PROGRAMMABLE_DELAYED_ENABLE_REGISTERS_HW_DELAY_ENABLE_1 00
# Disable RXQEC_OBS, FIC_OBS, HD2_OBS
WR          ADDR_SPI_RX1_CORE_PROGRAMMABLE_DELAYED_ENABLE_REGISTERS_HW_DELAY_ENABLE_0 00
#WRMASK     ADDR_SPI_CORE_RADIO_CONTROL_REGISTERS_ENABLES_FOR_STREAMPROC_RX1 00 01
# Clear RX1 QEC mutex debug bit
WRMASK      ADDR_SPI_CORE_1_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_7  00  10
RETURN


STREAM      1A
RETURN


STREAM      1B
RETURN


# Power up RX1A
STREAM      1C
# Power down ORX, ILB mixers
WR          ADDR_SPI_RX1_ANA_POWER_DOWN_REGISTERS_ORX2_PD 07
WR          ADDR_SPI_RX1_ANA_POWER_DOWN_REGISTERS_LB1_PD  07
# Select RX mixer
WR          ADDR_SPI_RX1_ANA_ORX_FE_REGISTERS_ORX_BB_MUX 02
# Power up LO Delay
WRMASK      ADDR_SPI_RX1_ANA_LO_DELAY_REGISTERS_ORX1_LO_DELAY_CORR_CONTROL_1 00 10
# Power up RX mixer
WR          ADDR_SPI_RX1_ANA_POWER_DOWN_REGISTERS_ORX1_PD 02
RETURN


# Power up RX1B
STREAM      1D
# Power down ORX, ILB mixers
WR          ADDR_SPI_RX1_ANA_POWER_DOWN_REGISTERS_ORX1_PD 07
WR          ADDR_SPI_RX1_ANA_POWER_DOWN_REGISTERS_LB1_PD 07
# Select RX mixer
WR          ADDR_SPI_RX1_ANA_ORX_FE_REGISTERS_ORX_BB_MUX 01
# Power up LO Delay
WRMASK      ADDR_SPI_RX1_ANA_LO_DELAY_REGISTERS_ORX2_LO_DELAY_CORR_CONTROL_1 00 10
# Power up RX mixer
WR          ADDR_SPI_RX1_ANA_POWER_DOWN_REGISTERS_ORX2_PD 02
RETURN  


# Power down RX1A
STREAM      1E
# Power down LO buffer
WR          ADDR_SPI_RX1_ANA_POWER_DOWN_REGISTERS_ORX1_PD 02
# Power down LO Delay
WRMASK      ADDR_SPI_RX1_ANA_LO_DELAY_REGISTERS_ORX1_LO_DELAY_CORR_CONTROL_1 10 10
# Power down FE and Capdac	
WR          ADDR_SPI_RX1_ANA_POWER_DOWN_REGISTERS_ORX1_PD 07
# Power down RX mux
WR          ADDR_SPI_RX1_ANA_ORX_FE_REGISTERS_ORX_BB_MUX 03   
RETURN


# Power down RX1B
STREAM      1F
# Power down LO buffer
WR          ADDR_SPI_RX1_ANA_POWER_DOWN_REGISTERS_ORX2_PD 02
# Power down LO Delay
WRMASK      ADDR_SPI_RX1_ANA_LO_DELAY_REGISTERS_ORX2_LO_DELAY_CORR_CONTROL_1 10 10
# Power down FE and Capdac	
WR          ADDR_SPI_RX1_ANA_POWER_DOWN_REGISTERS_ORX2_PD 07
# Power down RX mux
WR          ADDR_SPI_RX1_ANA_ORX_FE_REGISTERS_ORX_BB_MUX 03   
RETURN


# Power up HP ADC
STREAM      20
# Disable the LP ADC clock
WRMASK      ADDR_SPI_CORE_1_ANALOG_SPARE_REGISTERS_ANALOG_SPARE_REG_8 02 02
# Enable ADC Startup Reset before Power Up
WRMASK      ADDR_SPI_RX1_CORE_RX_OVERLOAD_RESET_DETECTION_REGISTERS_RX_ADC_OVERLOAD_RESET_THRESHOLD 00 80
# Assert adc_rst_dc, adc_dac_bypass_rf and de-assert adc_pd_dacs-delay, adc_pd_bias
WR          ADDR_SPI_RX1_ADC_REGMAP1_ADC_PD 60
# Wait for 1us
WAIT        $Delay_1us$
# Assert adc_rst_dc, adc_dac_bypass_rf, adc_pd_dacs_delay, adc_pd_bias
WR          ADDR_SPI_RX1_ADC_REGMAP1_ADC_PD 00
# Release ADC Startup 
WRMASK      ADDR_SPI_RX1_CORE_RX_OVERLOAD_RESET_DETECTION_REGISTERS_RX_ADC_OVERLOAD_RESET_THRESHOLD 80 80 
# Select Rx ADC Profile (HP ADC)
WR          ADDR_SPI_RX1_CORE_CHANNEL_CONFIGURATION_RX_ADC_PROFILE 00
# Select TIA Profile (HP ADC)
WRMASK      ADDR_SPI_RXB1_CORE_AGC_GENERAL_SETUP_REGISTERS_RX_TIA_PROFILE 01 07
RETURN


# Power up LP ADC
STREAM      21
# Disable the HP ADC clock
WRMASK      ADDR_SPI_CORE_1_ANALOG_SPARE_REGISTERS_ANALOG_SPARE_REG_8 01 01
# Enable ana and dig cal blocks, adc bias block, channel I&Q ADC clocks channel I&Q analog front end 
WR          ADDR_SPI_RX1_ADC_LP_VCOADC_ANA_POWER_DOWN_REG DF
# Wait for 4 us
WAIT        $Delay_1us$
WAIT        $Delay_1us$
WAIT        $Delay_1us$
WAIT        $Delay_1us$
# Enable clock for VCO ADC digital
WRMASK      ADDR_SPI_RX1_ADC_LP_VCOADC_DIG_CAL_EN 80 80
#Set TIA Profile (LP ADC)
WRMASK      ADDR_SPI_RXB1_CORE_AGC_GENERAL_SETUP_REGISTERS_RX_TIA_PROFILE 00 07
RETURN


# Power down HP ADC
STREAM      22
##force ADC Reset
WRMASK      ADDR_SPI_RX1_CORE_RX_OVERLOAD_RESET_DETECTION_REGISTERS_RX_ADC_OVERLOAD_RESET_SIZE 80 80
## Toggle adc_flash_reset_mode
RD          R0 ADDR_SPI_RX1_ADC_REGMAP1_ADC_FLASH_CAL_CTRL
LD          R1 10
XOR         R0 R1
WRA         R0 ADDR_SPI_RX1_ADC_REGMAP1_ADC_FLASH_CAL_CTRL
WRA         R0 ADDR_SPI_RX1_ADC_REGMAP1_ADC_FLASH_CAL_CTRL 
# wait 10 cycles with ARM @184.32MHz or ~52ns as per Rama's stream low simulation. Reuse Delay_80ns tag to wait a little longer.
WAIT        $Delay_80ns$
# Release ADC reset
WRMASK      ADDR_SPI_RX1_CORE_RX_OVERLOAD_RESET_DETECTION_REGISTERS_RX_ADC_OVERLOAD_RESET_THRESHOLD 80 80
# Power down HP ADC
WR          ADDR_SPI_RX1_ADC_REGMAP1_ADC_PD 7F
# Clear Force ADC reset
WRMASK      ADDR_SPI_RX1_CORE_RX_OVERLOAD_RESET_DETECTION_REGISTERS_RX_ADC_OVERLOAD_RESET_SIZE 00 80
RETURN 


# Power Down LP ADC
STREAM      23
# Disable ana and dig cal blocks, adc bias block, channel I&Q ADC clocks channel I&Q analog front end 
WR          ADDR_SPI_RX1_ADC_LP_VCOADC_ANA_POWER_DOWN_REG 00
# Disable clock for VCO ADC digital
WRMASK      ADDR_SPI_RX1_ADC_LP_VCOADC_DIG_CAL_EN 00 80    
RETURN


# Configure RX Algorithms
STREAM      24
#####Configure Algorithms#######
# Set radio states (BBDC, NBFIC, AGC, RFDC)
WR          ADDR_SPI_RX1_CORE_CHANNEL_CONFIGURATION_RX_CHAN_FUNCS_RADIO_STATES 00
# RX TIA Fc and Fine Tune
WRMASK      ADDR_SPI_RX1_ANA_ORX_TIA_CONFIGURATION_REGISTERS_ORXTIA_TUNER_MODE 01 01
# RX TIA Fc and Fine Tune
WRMASK      ADDR_SPI_RX1_ANA_ORX_TIA_CONFIGURATION_REGISTERS_ORXTIA_TUNER_MODE 00 01
##### QEC Mutual Exclusion #####
# Keep reading main SP semaphore 15 until getting locked
RDWAIT      ADDR_SPI_CORE_STREAM_PROC_REGISTERS_SEMAPHORE15  00  80
# QEC Mutual Exclusion 
WRMASK      ADDR_SPI_CORE_RADIO_CONTROL_REGISTERS_ENABLES_FOR_STREAMPROC_RX2  00  20
# Set RX QEC Profile
WRMASK      ADDR_SPI_CORE_RADIO_CONTROL_REGISTERS_ENABLES_FOR_STREAMPROC_RX1  01  07
# Release semaphore by writing 0 to "core.semaphore15_lock" bit
WR          ADDR_SPI_CORE_STREAM_PROC_REGISTERS_SEMAPHORE15  00
# Set RX1 QEC mutex debug bit
WRMASK      ADDR_SPI_CORE_1_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_7  10  10
##### QEC Mutual Exclusion #####
# NB FIC
#WRMASK     ADDR_SPI_RX1_CORE_RX_NBFIC_REGISTERS_RX_NBF_OBS_CONTROL1 02 02
# Use spare register 2 bit1 to control RX_NBF_PGOBS_DSEL (NSS-1644)
RD          R0 ADDR_SPI_RXB1_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_2
LD          R1 02
AND         R0 R1
R2          = R0
RD          R0 ADDR_SPI_RX1_CORE_RX_NBFIC_REGISTERS_RX_NBF_OBS_CONTROL1
LD          R1 FD
AND         R0 R1
OR          R0 R2
WRA         R0 ADDR_SPI_RX1_CORE_RX_NBFIC_REGISTERS_RX_NBF_OBS_CONTROL1
RETURN


# Enable RX Algorithms
STREAM      25
# Unmask BBDC
WR          ADDR_SPI_RXB1_CORE_DIGITAL_DC_OFFSET_CONTROL_REGISTERS_DIGITAL_DC_OFFSET_DECIMATE 01 
# Enable BBDC, RFDC, AGC, RSSI
WR          ADDR_SPI_RX1_CORE_PROGRAMMABLE_DELAYED_ENABLE_REGISTERS_HW_DELAY_ENABLE_1 0F
# Enable RXQEC_OBS, FIC_OBS, HD2_OBS
WR          ADDR_SPI_RX1_CORE_PROGRAMMABLE_DELAYED_ENABLE_REGISTERS_HW_DELAY_ENABLE_0 0B
RETURN


STREAM      26
# Set bit int_delay_0_enable
WRMASK      ADDR_SPI_RX1_CORE_PROGRAMMABLE_DELAYED_ENABLE_REGISTERS_RX_INT_DELAY_ENABLE 04 04
# Unmask datapath from ADC
WR          ADDR_SPI_RX1_CORE_RX_DATAPATH_CONFIG_RX_DATAPATH_FORCE_ZERO 10
#WRMASK     ADDR_SPI_RXB1_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_11 02 02
RETURN

STREAM      27
RETURN

STREAM      28
RETURN

STREAM      29
RETURN

STREAM      2A
RETURN

STREAM      2B
RETURN

STREAM      2C
RETURN

STREAM      2D
RETURN

STREAM      2E
RETURN


# To be called by RX Hop Edge Stream 5
STREAM      2F
# DMA Power up Config B (Post-VCO Cal and PLL Path Config and Power Up)
CALL        03
# Unmask datapath from interface
WR          ADDR_SPI_RX1_CORE_RX_DATAPATH_CONFIG_RX_DATAPATH_FORCE_ZERO 00
CALL        25
INTERRUPT   01
RETURN


# DMA Power up Config C (LDO Power Up)
STREAM      30
# Write Byte 0 of starting Address
WR          ADDR_SPI_CORE_1_GENERAL_DMA_2_REGISTERS_GENERAL_DMA_2_START_TABLE_ADDR_BYTE0 30
# Enable DMA
WR          ADDR_SPI_CORE_1_GENERAL_DMA_2_REGISTERS_GENERAL_DMA_2_CONTROL0 01
# Write Next_RX bit
WRMASK      ADDR_SPI_CORE_1_GENERAL_DMA_2_REGISTERS_GENERAL_DMA_2_CONTROL1 02 02
# Wait for Completion
RDWAIT      ADDR_SPI_CORE_1_GENERAL_DMA_2_REGISTERS_GENERAL_DMA_2_STATUS_FLAGS 07 07
# Disable DMA
WRMASK      ADDR_SPI_CORE_1_GENERAL_DMA_2_REGISTERS_GENERAL_DMA_2_CONTROL0 00 01
# Wait for LDO power up
WAIT        $LdoPowerUpWait$
# Set DMA debug flag
WRMASK      ADDR_SPI_RXB1_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_10 04 04 
RETURN     


# DMA Power up Config D (PLL Power Up)
STREAM      31
# Write Byte 0 of starting Address
WR          ADDR_SPI_CORE_1_GENERAL_DMA_2_REGISTERS_GENERAL_DMA_2_START_TABLE_ADDR_BYTE0 34
# Enable DMA
WR          ADDR_SPI_CORE_1_GENERAL_DMA_2_REGISTERS_GENERAL_DMA_2_CONTROL0 01
# Write Next_RX bit
WRMASK      ADDR_SPI_CORE_1_GENERAL_DMA_2_REGISTERS_GENERAL_DMA_2_CONTROL1 02 02
# Wait for Completion
RDWAIT      ADDR_SPI_CORE_1_GENERAL_DMA_2_REGISTERS_GENERAL_DMA_2_STATUS_FLAGS 07 07
# Disable DMA
WRMASK      ADDR_SPI_CORE_1_GENERAL_DMA_2_REGISTERS_GENERAL_DMA_2_CONTROL0 00 01   
# Set DMA debug flag
WRMASK      ADDR_SPI_RXB1_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_10 08 08  
RETURN
