# ########## MAIN STREM ###########
STREAM      0
RETURN


# Trigger DMA transfer for core DMA
STREAM      1
# Load DMA Start Address
RD          R1 ADDR_SPI_CORE_1_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_4    # Byte 3
WRA         R1 ADDR_SPI_CORE_DMA_REGISTERS_DMA_START_TABLE_ADDR_BYTE3
RD          R1 ADDR_SPI_CORE_1_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_5    # Byte 2
WRA         R1 ADDR_SPI_CORE_DMA_REGISTERS_DMA_START_TABLE_ADDR_BYTE2
RD          R1 ADDR_SPI_CORE_1_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_6    # Byte 1
WRA         R1 ADDR_SPI_CORE_DMA_REGISTERS_DMA_START_TABLE_ADDR_BYTE1
RD          R1 ADDR_SPI_CORE_1_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_7    # Byte 0
WRA         R1 ADDR_SPI_CORE_DMA_REGISTERS_DMA_START_TABLE_ADDR_BYTE0
# Enable DMA
WR          ADDR_SPI_CORE_DMA_REGISTERS_DMA_CONTROL0 01
RETURN


# Wait for PLL Lock
STREAM      2
WAIT        $PllLockWait$
RETURN


STREAM      3
RETURN


STREAM      4
RETURN


# RF PLL1 LOCK RISE
STREAM      5
RETURN


STREAM      6
RETURN

# RF PLL2 LOCK RISE
STREAM      7
RETURN


STREAM      8
RETURN


# AUX PLL LOCK RISE
STREAM      9
RETURN


STREAM      A
RETURN


# MONITOR RISE
STREAM      B
RETURN


# MONITOR FALL
STREAM      C
RETURN


# GP INTERRUPT RISE
STREAM      D
RETURN


# GPIO 0 ENABLE RISE
STREAM      E
RETURN


# GPIO 0 ENABLE FALL
STREAM      F
RETURN


# GPIO 1 ENABLE RISE
STREAM      10
RETURN


# GPIO 1 ENABLE FALL
STREAM      11
RETURN


# GPIO 2 ENABLE RISE
STREAM      12
RETURN


# GPIO 2 ENABLE FALL
STREAM      13
RETURN


# GPIO 3 ENABLE RISE
STREAM      14
RETURN


# GPIO 3 ENABLE FALL
STREAM      15
RETURN


# INT_DELAYED_ENABLE_RISE
STREAM      16
RETURN


# INT_DELAYED_ENABLE_FALL
STREAM      17
RETURN


# Hop_edge_0
STREAM      18
TIMEOUT     FFFF
# Switch A/B
# Toggle main_hop_1_toggle and main_hop_2_toggle
RD          R0  ADDR_SPI_CORE_2_PROGRAMMABLE_DELAYED_ENABLE_REGISTERS_MAIN_ENABLE
LD          R1  03
XOR         R0  R1
WRA         R0  ADDR_SPI_CORE_2_PROGRAMMABLE_DELAYED_ENABLE_REGISTERS_MAIN_ENABLE
# Start DMA 0x50 (LO power down and PLL retune)
# Write Byte 0 of starting Address
WR          ADDR_SPI_CORE_DMA_REGISTERS_DMA_START_TABLE_ADDR_BYTE0  50
# Enable DMA
WR          ADDR_SPI_CORE_DMA_REGISTERS_DMA_CONTROL0      01
# Write Next_TX bit (???)
WRMASK      ADDR_SPI_CORE_DMA_REGISTERS_DMA_CONTROL1      01  01
# Wait for Completion
RDWAIT      ADDR_SPI_CORE_DMA_REGISTERS_DMA_STATUS_FLAGS  07  07
# Disable DMA
WRMASK      ADDR_SPI_CORE_DMA_REGISTERS_DMA_CONTROL0      00  01
# Read CORE_1.SOFTWARE_SPARE_5. If 1, wait for PLL retune (non-LO muxing mode)
$IfTx1IntLo$ RD R0  ADDR_SPI_CORE_1_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_5
$IfTx1IntLo$ CONDCALL 02
#Start DMA 0x58 (LO Powerup)
# Write Byte 0 of starting Address
WR          ADDR_SPI_CORE_DMA_REGISTERS_DMA_START_TABLE_ADDR_BYTE0  54
# Enable DMA
WR          ADDR_SPI_CORE_DMA_REGISTERS_DMA_CONTROL0      01
# Write Next_TX bit (???)
WRMASK      ADDR_SPI_CORE_DMA_REGISTERS_DMA_CONTROL1      01  01
# Wait for Completion
RDWAIT      ADDR_SPI_CORE_DMA_REGISTERS_DMA_STATUS_FLAGS  07  07
# Disable DMA
WRMASK      ADDR_SPI_CORE_DMA_REGISTERS_DMA_CONTROL0      00  01
# Interrupt ARM: streamProc_mainHopEdgeHandler()
INTERRUPT   01
RETURN


# Hop_edge_1
STREAM      19
RETURN     

  
# Hop_edge_2 (Current compiler generates error if stream 26 is included)
#STREAM     1A
#RETURN 


# Hop_edge_3 (Current compiler generates error if stream 27 is included)
#STREAM     1B
#RETURN 