Sample behavioral waveforms for design file pll1.v

The following waveforms show the behavior of altpll megafunction for the chosen set of parameters in design pll1.v. The design pll1.v has Cyclone AUTO pll configured in NORMAL mode The primary clock input to the PLL is INCLK0, with clock period 20833 ps. Output port LOCKED will go high when the PLL locks to the input clock.