This folder contains the Quartus II project file (CED1.qpf) used to create the 
hex file (CED1.hexout). This hex file is used to program the FPGA on CED1 PCB 
in order for it to work with the AD7760_62_63 evaluation PCB. The verilog source 
files can be found in the source subdirectory. The functions provided by 
ADI_CED1a.dll can be used to interface to the evaluation system. A commented 
C program showing how to call these functions in the context of this 
evaluation system is located in the example interface code subdirectory. 
Persons wishing to implement a program in another language should use the code 
as reference.



