| Linduino 1.3.0 Linear Technology Arduino-Compatible Demonstration Board

LTC4155_reg_defs.h
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1 /*!
2 LTC4155: Dual-Input Power Manager / 3.5A Li-Ion Battery Charger with I²C Control and USB OTG
3
4 @verbatim
5 The LTC®4155 is a 15 watt I²C controlled power manager with PowerPath™ instant-
6 on operation, high efficiency switching battery charging and USB compatibility.
7 The LTC4155 seamlessly manages power distribution from two 5V sources, such as a
8 USB port and a wall adapter, to a single-cell rechargeable Lithium-Ion/Polymer
9 battery and a system load.
10 @endverbatim
11
12 http://www.linear.com/product/LTC4155
13
14 http://www.linear.com/product/LTC4155#demoboards
15
16
17 Copyright 2018(c) Analog Devices, Inc.
18
19 All rights reserved.
20
21 Redistribution and use in source and binary forms, with or without
22 modification, are permitted provided that the following conditions are met:
23 - Redistributions of source code must retain the above copyright
24 notice, this list of conditions and the following disclaimer.
25 - Redistributions in binary form must reproduce the above copyright
26 notice, this list of conditions and the following disclaimer in
27 the documentation and/or other materials provided with the
28 distribution.
29 - Neither the name of Analog Devices, Inc. nor the names of its
30 contributors may be used to endorse or promote products derived
31 from this software without specific prior written permission.
32 - The use of this software may or may not infringe the patent rights
33 of one or more patent holders. This license does not release you
34 from the requirement that you obtain separate licenses from these
35 patent holders to use this software.
36 - Use of the software either in source or binary form, must be run
37 on or directly connected to an Analog Devices Inc. component.
38
39 THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
40 IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
41 MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
42 IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
43 INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
44 LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
45 SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
46 CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
47 OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
48 OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
49
50 Generated on: 2016-01-19
51 */
52
53 /*! @file
54 * @ingroup LTC4155
55 * @brief LTC4155 Register Map Definition Header
56 *
57 *
58 * This file contains LTC4155 definitions for each command_code as well as
59 * each individual bit field for the case when a register contains multiple
60 * bit-packed fields smaller than the register width.
61 * Each bit field name is prepended with LTC4155_.
62 * Each bit field has individual definitions for its _SIZE, _OFFSET (LSB) and _MASK,
63 * as well as the three fields stored in a single 16-bit word for use with the access
64 * functions provided by LTC4155.c and LTC4155.h.
65 * In the case that the bit field contents represent an enumeration, _PRESET
66 * definitions exists to translate from human readable format to the encoded value.
67 * See @ref LTC4155_register_map for detailed descriptions of each bit field.
68 */
69
70 /*! @defgroup LTC4155_register_map LTC4155 Register Map Definitions
71 * @ingroup LTC4155
72 */
73
74 #ifndef LTC4155_REG_DEFS_H_
75 #define LTC4155_REG_DEFS_H_
76
77 #define LTC4155_ADDR_09 0x9 //!<LTC4155 I2C address in 7-bit format
78 /*! @defgroup LTC4155_REG0 REG0
79 * @ingroup LTC4155_register_map
80 * @brief REG0 Register
81 *
82 * | 7 | 6 | 5 | 4:0 |
83 * |:------------------:|:------------------:|:--------------:|:-------:|
84 * | DISABLE_INPUT_UVCL | EN_BAT_CONDITIONER | LOCKOUT_ID_PIN | USBILIM |
85 *
86 * - CommandCode: 0x00
87 * - Contains Bit Fields:
88 * + @ref LTC4155_DISABLE_INPUT_UVCL "DISABLE_INPUT_UVCL" : Disables automatic power reduction in response to low input voltage.
89 * + @ref LTC4155_EN_BAT_CONDITIONER "EN_BAT_CONDITIONER" : Enables autonomous Overtemperature Battery Conditioner Load when the thermistor temperature exceeds 60°C.
90 * + @ref LTC4155_LOCKOUT_ID_PIN "LOCKOUT_ID_PIN" : Disables autonomous USB OTG operation when the ID pin is grounded by an appropriate USB cable.
91 * + @ref LTC4155_USBILIM "USBILIM" : USB total input current limit setting. Register contents will be modified by the LTC4155 upon certain events. See the datasheet section Input Current Regulation.
92 */
93
94 //!@{
95 #define LTC4155_REG0_SUBADDR 0x00
96 #define LTC4155_REG0 (0 << 12 | (16 - 1) << 8 | LTC4155_REG0_SUBADDR)
97 //!@}
98 /*! @defgroup LTC4155_DISABLE_INPUT_UVCL DISABLE_INPUT_UVCL
99 * @ingroup LTC4155_register_map
100 * @brief DISABLE_INPUT_UVCL Bit Field
101 *
102 * Disables automatic power reduction in response to low input voltage.
103 * - Register: @ref LTC4155_REG0 "REG0"
104 * - CommandCode: 0x00
105 * - Size: 1
106 * - Offset: 7
107 * - MSB: 7
108 * - MASK: 0x80
109 * - Access: R/W
110 * - Default: 0
111 */
112 //!@{
113 #define LTC4155_DISABLE_INPUT_UVCL_SUBADDR LTC4155_REG0_SUBADDR //!< @ref LTC4155_DISABLE_INPUT_UVCL "DISABLE_INPUT_UVCL"
114 #define LTC4155_DISABLE_INPUT_UVCL_SIZE 1
115 #define LTC4155_DISABLE_INPUT_UVCL_OFFSET 7
116 #define LTC4155_DISABLE_INPUT_UVCL_MASK 0x80
117 #define LTC4155_DISABLE_INPUT_UVCL (LTC4155_DISABLE_INPUT_UVCL_OFFSET << 12 | (LTC4155_DISABLE_INPUT_UVCL_SIZE - 1) << 8 | LTC4155_DISABLE_INPUT_UVCL_SUBADDR)
118 //!@}
119 /*! @defgroup LTC4155_EN_BAT_CONDITIONER EN_BAT_CONDITIONER
120 * @ingroup LTC4155_register_map
121 * @brief EN_BAT_CONDITIONER Bit Field
122 *
123 * Enables autonomous Overtemperature Battery Conditioner Load when the thermistor temperature exceeds 60°C.
124 * - Register: @ref LTC4155_REG0 "REG0"
125 * - CommandCode: 0x00
126 * - Size: 1
127 * - Offset: 6
128 * - MSB: 6
129 * - MASK: 0x40
130 * - Access: R/W
131 * - Default: 0
132 */
133 //!@{
134 #define LTC4155_EN_BAT_CONDITIONER_SUBADDR LTC4155_REG0_SUBADDR //!< @ref LTC4155_EN_BAT_CONDITIONER "EN_BAT_CONDITIONER"
135 #define LTC4155_EN_BAT_CONDITIONER_SIZE 1
136 #define LTC4155_EN_BAT_CONDITIONER_OFFSET 6
137 #define LTC4155_EN_BAT_CONDITIONER_MASK 0x40
138 #define LTC4155_EN_BAT_CONDITIONER (LTC4155_EN_BAT_CONDITIONER_OFFSET << 12 | (LTC4155_EN_BAT_CONDITIONER_SIZE - 1) << 8 | LTC4155_EN_BAT_CONDITIONER_SUBADDR)
139 //!@}
140 /*! @defgroup LTC4155_LOCKOUT_ID_PIN LOCKOUT_ID_PIN
141 * @ingroup LTC4155_register_map
142 * @brief LOCKOUT_ID_PIN Bit Field
143 *
144 * Disables autonomous USB OTG operation when the ID pin is grounded by an appropriate USB cable.
145 * - Register: @ref LTC4155_REG0 "REG0"
146 * - CommandCode: 0x00
147 * - Size: 1
148 * - Offset: 5
149 * - MSB: 5
150 * - MASK: 0x20
151 * - Access: R/W
152 * - Default: 0
153 */
154 //!@{
155 #define LTC4155_LOCKOUT_ID_PIN_SUBADDR LTC4155_REG0_SUBADDR //!< @ref LTC4155_LOCKOUT_ID_PIN "LOCKOUT_ID_PIN"
156 #define LTC4155_LOCKOUT_ID_PIN_SIZE 1
157 #define LTC4155_LOCKOUT_ID_PIN_OFFSET 5
158 #define LTC4155_LOCKOUT_ID_PIN_MASK 0x20
159 #define LTC4155_LOCKOUT_ID_PIN (LTC4155_LOCKOUT_ID_PIN_OFFSET << 12 | (LTC4155_LOCKOUT_ID_PIN_SIZE - 1) << 8 | LTC4155_LOCKOUT_ID_PIN_SUBADDR)
160 //!@}
161 /*! @defgroup LTC4155_USBILIM USBILIM
162 * @ingroup LTC4155_register_map
163 * @brief USBILIM Bit Field
164 *
165 * USB total input current limit setting. Register contents will be modified by the LTC4155 upon certain events. See the datasheet section Input Current Regulation.
166 * - Register: @ref LTC4155_REG0 "REG0"
167 * - CommandCode: 0x00
168 * - Size: 5
169 * - Offset: 0
170 * - MSB: 4
171 * - MASK: 0x1F
172 * - Access: R/W
173 * - Default: n/a
174 */
175 //!@{
176 #define LTC4155_USBILIM_SUBADDR LTC4155_REG0_SUBADDR //!< @ref LTC4155_USBILIM "USBILIM"
177 #define LTC4155_USBILIM_SIZE 5
178 #define LTC4155_USBILIM_OFFSET 0
179 #define LTC4155_USBILIM_MASK 0x1F
180 #define LTC4155_USBILIM (LTC4155_USBILIM_OFFSET << 12 | (LTC4155_USBILIM_SIZE - 1) << 8 | LTC4155_USBILIM_SUBADDR)
181 #define LTC4155_USBILIM_PRESET__100MA 0x0
182 #define LTC4155_USBILIM_PRESET__500MA 0x1
183 #define LTC4155_USBILIM_PRESET__600MA 0x2
184 #define LTC4155_USBILIM_PRESET__700MA 0x3
185 #define LTC4155_USBILIM_PRESET__800MA 0x4
186 #define LTC4155_USBILIM_PRESET__900MA 0x5
187 #define LTC4155_USBILIM_PRESET__1P00A 0x6
188 #define LTC4155_USBILIM_PRESET__1P25A 0x7
189 #define LTC4155_USBILIM_PRESET__1P50A 0x8
190 #define LTC4155_USBILIM_PRESET__1P75A 0x9
191 #define LTC4155_USBILIM_PRESET__2P00A 0xA
192 #define LTC4155_USBILIM_PRESET__2P25A 0xB
193 #define LTC4155_USBILIM_PRESET__2P50A 0xC
194 #define LTC4155_USBILIM_PRESET__2P75A 0xD
195 #define LTC4155_USBILIM_PRESET__3P00A 0xE
196 #define LTC4155_USBILIM_PRESET__2P5MA_SUSPEND 0xF
197 #define LTC4155_USBILIM_PRESET_CLPROG_1 0x1F
198 //!@}
199
200 /*! @defgroup LTC4155_REG1 REG1
201 * @ingroup LTC4155_register_map
202 * @brief REG1 Register
203 *
204 * | 7 | 6:5 | 4:0 |
205 * |:--------:|:-----:|:--------:|
206 * | PRIORITY | TIMER | WALLILIM |
207 *
208 * - CommandCode: 0x01
209 * - Contains Bit Fields:
210 * + @ref LTC4155_PRIORITY "PRIORITY" : Input connector priority swap setting. Setting PRIORITY will cause power to be drawn from USB when both WALL and USB power are present.
211 * + @ref LTC4155_TIMER "TIMER" : User Programmed Li-Ion charger safety timer setting. This internal timer begins at the onset of constant-voltage charging. Charging terminates at the expiration of the selected time.
212 * + @ref LTC4155_WALLILIM "WALLILIM" : WALL total input current limit setting. Register contents will be modified by the LTC4155 upon certain events. See the datasheet section Input Current Regulation.
213 */
214
215 //!@{
216 #define LTC4155_REG1_SUBADDR 0x01
217 #define LTC4155_REG1 (0 << 12 | (16 - 1) << 8 | LTC4155_REG1_SUBADDR)
218 //!@}
219 /*! @defgroup LTC4155_PRIORITY PRIORITY
220 * @ingroup LTC4155_register_map
221 * @brief PRIORITY Bit Field
222 *
223 * Input connector priority swap setting. Setting PRIORITY will cause power to be drawn from USB when both WALL and USB power are present.
224 * - Register: @ref LTC4155_REG1 "REG1"
225 * - CommandCode: 0x01
226 * - Size: 1
227 * - Offset: 7
228 * - MSB: 7
229 * - MASK: 0x80
230 * - Access: R/W
231 * - Default: 0
232 */
233 //!@{
234 #define LTC4155_PRIORITY_SUBADDR LTC4155_REG1_SUBADDR //!< @ref LTC4155_PRIORITY "PRIORITY"
235 #define LTC4155_PRIORITY_SIZE 1
236 #define LTC4155_PRIORITY_OFFSET 7
237 #define LTC4155_PRIORITY_MASK 0x80
238 #define LTC4155_PRIORITY (LTC4155_PRIORITY_OFFSET << 12 | (LTC4155_PRIORITY_SIZE - 1) << 8 | LTC4155_PRIORITY_SUBADDR)
239 #define LTC4155_PRIORITY_PRESET_WALL 0x0
240 #define LTC4155_PRIORITY_PRESET_USB 0x1
241 //!@}
242 /*! @defgroup LTC4155_TIMER TIMER
243 * @ingroup LTC4155_register_map
244 * @brief TIMER Bit Field
245 *
246 * User Programmed Li-Ion charger safety timer setting. This internal timer begins at the onset of constant-voltage charging. Charging terminates at the expiration of the selected time.
247 * - Register: @ref LTC4155_REG1 "REG1"
248 * - CommandCode: 0x01
249 * - Size: 2
250 * - Offset: 5
251 * - MSB: 6
252 * - MASK: 0x60
253 * - Access: R/W
254 * - Default: 0
255 */
256 //!@{
257 #define LTC4155_TIMER_SUBADDR LTC4155_REG1_SUBADDR //!< @ref LTC4155_TIMER "TIMER"
258 #define LTC4155_TIMER_SIZE 2
259 #define LTC4155_TIMER_OFFSET 5
260 #define LTC4155_TIMER_MASK 0x60
261 #define LTC4155_TIMER (LTC4155_TIMER_OFFSET << 12 | (LTC4155_TIMER_SIZE - 1) << 8 | LTC4155_TIMER_SUBADDR)
262 #define LTC4155_TIMER_PRESET__4_HOUR 0x0
263 #define LTC4155_TIMER_PRESET__8_HOUR_OR_COVERX 0x1
264 #define LTC4155_TIMER_PRESET__1_HOUR 0x2
265 #define LTC4155_TIMER_PRESET__2_HOUR 0x3
266 //!@}
267 /*! @defgroup LTC4155_WALLILIM WALLILIM
268 * @ingroup LTC4155_register_map
269 * @brief WALLILIM Bit Field
270 *
271 * WALL total input current limit setting. Register contents will be modified by the LTC4155 upon certain events. See the datasheet section Input Current Regulation.
272 * - Register: @ref LTC4155_REG1 "REG1"
273 * - CommandCode: 0x01
274 * - Size: 5
275 * - Offset: 0
276 * - MSB: 4
277 * - MASK: 0x1F
278 * - Access: R/W
279 * - Default: n/a
280 */
281 //!@{
282 #define LTC4155_WALLILIM_SUBADDR LTC4155_REG1_SUBADDR //!< @ref LTC4155_WALLILIM "WALLILIM"
283 #define LTC4155_WALLILIM_SIZE 5
284 #define LTC4155_WALLILIM_OFFSET 0
285 #define LTC4155_WALLILIM_MASK 0x1F
286 #define LTC4155_WALLILIM (LTC4155_WALLILIM_OFFSET << 12 | (LTC4155_WALLILIM_SIZE - 1) << 8 | LTC4155_WALLILIM_SUBADDR)
287 #define LTC4155_WALLILIM_PRESET__100MA 0x0
288 #define LTC4155_WALLILIM_PRESET__500MA 0x1
289 #define LTC4155_WALLILIM_PRESET__600MA 0x2
290 #define LTC4155_WALLILIM_PRESET__700MA 0x3
291 #define LTC4155_WALLILIM_PRESET__800MA 0x4
292 #define LTC4155_WALLILIM_PRESET__900MA 0x5
293 #define LTC4155_WALLILIM_PRESET__1P00A 0x6
294 #define LTC4155_WALLILIM_PRESET__1P25A 0x7
295 #define LTC4155_WALLILIM_PRESET__1P50A 0x8
296 #define LTC4155_WALLILIM_PRESET__1P75A 0x9
297 #define LTC4155_WALLILIM_PRESET__2P00A 0xA
298 #define LTC4155_WALLILIM_PRESET__2P25A 0xB
299 #define LTC4155_WALLILIM_PRESET__2P50A 0xC
300 #define LTC4155_WALLILIM_PRESET__2P75A 0xD
301 #define LTC4155_WALLILIM_PRESET__3P00A 0xE
302 #define LTC4155_WALLILIM_PRESET__2P5MA_SUSPEND 0xF
303 #define LTC4155_WALLILIM_PRESET_CLPROG_1 0x1F
304 //!@}
305
306 /*! @defgroup LTC4155_REG2 REG2
307 * @ingroup LTC4155_register_map
308 * @brief REG2 Register
309 *
310 * | 7:4 | 3:2 | 1:0 |
311 * |:-------:|:------:|:-----:|
312 * | ICHARGE | VFLOAT | CXSET |
313 *
314 * - CommandCode: 0x02
315 * - Contains Bit Fields:
316 * + @ref LTC4155_ICHARGE "ICHARGE" : Battery charger current limit setting.
317 * + @ref LTC4155_VFLOAT "VFLOAT" : Battery charge voltage setting.
318 * + @ref LTC4155_CXSET "CXSET" : End-of-Charge indication current threshold setting. This threshold can also be used for charge termination if TIMER is set to 8_Hour_or_CoverX.
319 */
320
321 //!@{
322 #define LTC4155_REG2_SUBADDR 0x02
323 #define LTC4155_REG2 (0 << 12 | (16 - 1) << 8 | LTC4155_REG2_SUBADDR)
324 //!@}
325 /*! @defgroup LTC4155_ICHARGE ICHARGE
326 * @ingroup LTC4155_register_map
327 * @brief ICHARGE Bit Field
328 *
329 * Battery charger current limit setting.
330 * - Register: @ref LTC4155_REG2 "REG2"
331 * - CommandCode: 0x02
332 * - Size: 4
333 * - Offset: 4
334 * - MSB: 7
335 * - MASK: 0xF0
336 * - Access: R/W
337 * - Default: 0xF
338 */
339 //!@{
340 #define LTC4155_ICHARGE_SUBADDR LTC4155_REG2_SUBADDR //!< @ref LTC4155_ICHARGE "ICHARGE"
341 #define LTC4155_ICHARGE_SIZE 4
342 #define LTC4155_ICHARGE_OFFSET 4
343 #define LTC4155_ICHARGE_MASK 0xF0
344 #define LTC4155_ICHARGE (LTC4155_ICHARGE_OFFSET << 12 | (LTC4155_ICHARGE_SIZE - 1) << 8 | LTC4155_ICHARGE_SUBADDR)
345 #define LTC4155_ICHARGE_PRESET_CHARGER_DISABLED 0x0
346 #define LTC4155_ICHARGE_PRESET__12P50PCT 0x1
347 #define LTC4155_ICHARGE_PRESET__18P75PCT 0x2
348 #define LTC4155_ICHARGE_PRESET__25P00PCT 0x3
349 #define LTC4155_ICHARGE_PRESET__31P25PCT 0x4
350 #define LTC4155_ICHARGE_PRESET__37P50PCT 0x5
351 #define LTC4155_ICHARGE_PRESET__43P75PCT 0x6
352 #define LTC4155_ICHARGE_PRESET__50P00PCT 0x7
353 #define LTC4155_ICHARGE_PRESET__56P25PCT 0x8
354 #define LTC4155_ICHARGE_PRESET__62P50PCT 0x9
355 #define LTC4155_ICHARGE_PRESET__68P75PCT 0xA
356 #define LTC4155_ICHARGE_PRESET__75P00PCT 0xB
357 #define LTC4155_ICHARGE_PRESET__81P25PCT 0xC
358 #define LTC4155_ICHARGE_PRESET__87P50PCT 0xD
359 #define LTC4155_ICHARGE_PRESET__93P75PCT 0xE
360 #define LTC4155_ICHARGE_PRESET__100P0PCT 0xF
361 //!@}
362 /*! @defgroup LTC4155_VFLOAT VFLOAT
363 * @ingroup LTC4155_register_map
364 * @brief VFLOAT Bit Field
365 *
366 * Battery charge voltage setting.
367 * - Register: @ref LTC4155_REG2 "REG2"
368 * - CommandCode: 0x02
369 * - Size: 2
370 * - Offset: 2
371 * - MSB: 3
372 * - MASK: 0x0C
373 * - Access: R/W
374 * - Default: 0
375 */
376 //!@{
377 #define LTC4155_VFLOAT_SUBADDR LTC4155_REG2_SUBADDR //!< @ref LTC4155_VFLOAT "VFLOAT"
378 #define LTC4155_VFLOAT_SIZE 2
379 #define LTC4155_VFLOAT_OFFSET 2
380 #define LTC4155_VFLOAT_MASK 0x0C
381 #define LTC4155_VFLOAT (LTC4155_VFLOAT_OFFSET << 12 | (LTC4155_VFLOAT_SIZE - 1) << 8 | LTC4155_VFLOAT_SUBADDR)
382 #define LTC4155_VFLOAT_PRESET__4P05V 0x0
383 #define LTC4155_VFLOAT_PRESET__4P10V 0x1
384 #define LTC4155_VFLOAT_PRESET__4P15V 0x2
385 #define LTC4155_VFLOAT_PRESET__4P20V 0x3
386 //!@}
387 /*! @defgroup LTC4155_CXSET CXSET
388 * @ingroup LTC4155_register_map
389 * @brief CXSET Bit Field
390 *
391 * End-of-Charge indication current threshold setting. This threshold can also be used for charge termination if TIMER is set to 8_Hour_or_CoverX.
392 * - Register: @ref LTC4155_REG2 "REG2"
393 * - CommandCode: 0x02
394 * - Size: 2
395 * - Offset: 0
396 * - MSB: 1
397 * - MASK: 0x03
398 * - Access: R/W
399 * - Default: 0
400 */
401 //!@{
402 #define LTC4155_CXSET_SUBADDR LTC4155_REG2_SUBADDR //!< @ref LTC4155_CXSET "CXSET"
403 #define LTC4155_CXSET_SIZE 2
404 #define LTC4155_CXSET_OFFSET 0
405 #define LTC4155_CXSET_MASK 0x03
406 #define LTC4155_CXSET (LTC4155_CXSET_OFFSET << 12 | (LTC4155_CXSET_SIZE - 1) << 8 | LTC4155_CXSET_SUBADDR)
407 #define LTC4155_CXSET_PRESET__10PCT 0x0
408 #define LTC4155_CXSET_PRESET__20PCT 0x1
409 #define LTC4155_CXSET_PRESET__2PCT 0x2
410 #define LTC4155_CXSET_PRESET__5PCT 0x3
411 //!@}
412
413 /*! @defgroup LTC4155_REG3 REG3
414 * @ingroup LTC4155_register_map
415 * @brief REG3 Register
416 *
417 * | 7:5 | 4 | 3 | 2:1 | 0 |
418 * |:--------------:|:-------------:|:-----------:|:-------:|:------:|
419 * | CHARGER_STATUS | ID_PIN_DETECT | OTG_ENABLED | NTCSTAT | LOWBAT |
420 *
421 * - CommandCode: 0x03
422 * - Contains Bit Fields:
423 * + @ref LTC4155_CHARGER_STATUS "CHARGER_STATUS" : Battery charger status.
424 * + @ref LTC4155_ID_PIN_DETECT "ID_PIN_DETECT" : On-the-Go boost ID pin detection status.
425 * + @ref LTC4155_OTG_ENABLED "OTG_ENABLED" : On-the-Go boost converter enable status.
426 * + @ref LTC4155_NTCSTAT "NTCSTAT" : Thermistor reading status.
427 * + @ref LTC4155_LOWBAT "LOWBAT" : Battery below ~2.8V or charger disabled.
428 */
429
430 //!@{
431 #define LTC4155_REG3_SUBADDR 0x03
432 #define LTC4155_REG3 (0 << 12 | (16 - 1) << 8 | LTC4155_REG3_SUBADDR)
433 //!@}
434 /*! @defgroup LTC4155_CHARGER_STATUS CHARGER_STATUS
435 * @ingroup LTC4155_register_map
436 * @brief CHARGER_STATUS Bit Field
437 *
438 * Battery charger status.
439 * - Register: @ref LTC4155_REG3 "REG3"
440 * - CommandCode: 0x03
441 * - Size: 3
442 * - Offset: 5
443 * - MSB: 7
444 * - MASK: 0xE0
445 * - Access: R
446 * - Default: n/a
447 */
448 //!@{
449 #define LTC4155_CHARGER_STATUS_SUBADDR LTC4155_REG3_SUBADDR //!< @ref LTC4155_CHARGER_STATUS "CHARGER_STATUS"
450 #define LTC4155_CHARGER_STATUS_SIZE 3
451 #define LTC4155_CHARGER_STATUS_OFFSET 5
452 #define LTC4155_CHARGER_STATUS_MASK 0xE0
453 #define LTC4155_CHARGER_STATUS (LTC4155_CHARGER_STATUS_OFFSET << 12 | (LTC4155_CHARGER_STATUS_SIZE - 1) << 8 | LTC4155_CHARGER_STATUS_SUBADDR)
454 #define LTC4155_CHARGER_STATUS_PRESET_CHARGER_OFF 0x0
455 #define LTC4155_CHARGER_STATUS_PRESET_LOW_BAT 0x1
456 #define LTC4155_CHARGER_STATUS_PRESET_CONSTANT_CURRENT 0x2
457 #define LTC4155_CHARGER_STATUS_PRESET_CONSTANT_VOLTAGE_I_GREATER_THAN_COVERX 0x3
458 #define LTC4155_CHARGER_STATUS_PRESET_CONSTANT_VOLTAGE_I_LESS_THAN_COVERX 0x4
459 #define LTC4155_CHARGER_STATUS_PRESET_NTC_TOO_WARM_TO_CHARGE 0x5
460 #define LTC4155_CHARGER_STATUS_PRESET_NTC_TOO_COLD_TO_CHARGE 0x6
461 #define LTC4155_CHARGER_STATUS_PRESET_NTC_CRITICALLY_HOT 0x7
462 //!@}
463 /*! @defgroup LTC4155_ID_PIN_DETECT ID_PIN_DETECT
464 * @ingroup LTC4155_register_map
465 * @brief ID_PIN_DETECT Bit Field
466 *
467 * On-the-Go boost ID pin detection status.
468 * - Register: @ref LTC4155_REG3 "REG3"
469 * - CommandCode: 0x03
470 * - Size: 1
471 * - Offset: 4
472 * - MSB: 4
473 * - MASK: 0x10
474 * - Access: R
475 * - Default: n/a
476 */
477 //!@{
478 #define LTC4155_ID_PIN_DETECT_SUBADDR LTC4155_REG3_SUBADDR //!< @ref LTC4155_ID_PIN_DETECT "ID_PIN_DETECT"
479 #define LTC4155_ID_PIN_DETECT_SIZE 1
480 #define LTC4155_ID_PIN_DETECT_OFFSET 4
481 #define LTC4155_ID_PIN_DETECT_MASK 0x10
482 #define LTC4155_ID_PIN_DETECT (LTC4155_ID_PIN_DETECT_OFFSET << 12 | (LTC4155_ID_PIN_DETECT_SIZE - 1) << 8 | LTC4155_ID_PIN_DETECT_SUBADDR)
483 //!@}
484 /*! @defgroup LTC4155_OTG_ENABLED OTG_ENABLED
485 * @ingroup LTC4155_register_map
486 * @brief OTG_ENABLED Bit Field
487 *
488 * On-the-Go boost converter enable status.
489 * - Register: @ref LTC4155_REG3 "REG3"
490 * - CommandCode: 0x03
491 * - Size: 1
492 * - Offset: 3
493 * - MSB: 3
494 * - MASK: 0x08
495 * - Access: R
496 * - Default: n/a
497 */
498 //!@{
499 #define LTC4155_OTG_ENABLED_SUBADDR LTC4155_REG3_SUBADDR //!< @ref LTC4155_OTG_ENABLED "OTG_ENABLED"
500 #define LTC4155_OTG_ENABLED_SIZE 1
501 #define LTC4155_OTG_ENABLED_OFFSET 3
502 #define LTC4155_OTG_ENABLED_MASK 0x08
503 #define LTC4155_OTG_ENABLED (LTC4155_OTG_ENABLED_OFFSET << 12 | (LTC4155_OTG_ENABLED_SIZE - 1) << 8 | LTC4155_OTG_ENABLED_SUBADDR)
504 //!@}
505 /*! @defgroup LTC4155_NTCSTAT NTCSTAT
506 * @ingroup LTC4155_register_map
507 * @brief NTCSTAT Bit Field
508 *
509 * Thermistor reading status.
510 * - Register: @ref LTC4155_REG3 "REG3"
511 * - CommandCode: 0x03
512 * - Size: 2
513 * - Offset: 1
514 * - MSB: 2
515 * - MASK: 0x06
516 * - Access: R
517 * - Default: n/a
518 */
519 //!@{
520 #define LTC4155_NTCSTAT_SUBADDR LTC4155_REG3_SUBADDR //!< @ref LTC4155_NTCSTAT "NTCSTAT"
521 #define LTC4155_NTCSTAT_SIZE 2
522 #define LTC4155_NTCSTAT_OFFSET 1
523 #define LTC4155_NTCSTAT_MASK 0x06
524 #define LTC4155_NTCSTAT (LTC4155_NTCSTAT_OFFSET << 12 | (LTC4155_NTCSTAT_SIZE - 1) << 8 | LTC4155_NTCSTAT_SUBADDR)
525 #define LTC4155_NTCSTAT_PRESET_NORMAL 0x0
526 #define LTC4155_NTCSTAT_PRESET_TOO_COLD 0x1
527 #define LTC4155_NTCSTAT_PRESET_TOO_WARM 0x2
528 #define LTC4155_NTCSTAT_PRESET_HOT_FAULT 0x3
529 //!@}
530 /*! @defgroup LTC4155_LOWBAT LOWBAT
531 * @ingroup LTC4155_register_map
532 * @brief LOWBAT Bit Field
533 *
534 * Battery below ~2.8V or charger disabled.
535 * - Register: @ref LTC4155_REG3 "REG3"
536 * - CommandCode: 0x03
537 * - Size: 1
538 * - Offset: 0
539 * - MSB: 0
540 * - MASK: 0x01
541 * - Access: R
542 * - Default: n/a
543 */
544 //!@{
545 #define LTC4155_LOWBAT_SUBADDR LTC4155_REG3_SUBADDR //!< @ref LTC4155_LOWBAT "LOWBAT"
546 #define LTC4155_LOWBAT_SIZE 1
547 #define LTC4155_LOWBAT_OFFSET 0
548 #define LTC4155_LOWBAT_MASK 0x01
549 #define LTC4155_LOWBAT (LTC4155_LOWBAT_OFFSET << 12 | (LTC4155_LOWBAT_SIZE - 1) << 8 | LTC4155_LOWBAT_SUBADDR)
550 //!@}
551
552 /*! @defgroup LTC4155_REG4 REG4
553 * @ingroup LTC4155_register_map
554 * @brief REG4 Register
555 *
556 * | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
557 * |:------------:|:-----------:|:------------:|:-------------:|:-----------------:|:----------:|:---------:|:--------:|
558 * | EXT_PWR_GOOD | USBSNS_GOOD | WALLSNS_GOOD | AT_INPUT_ILIM | INPUT_UVCL_ACTIVE | OVP_ACTIVE | OTG_FAULT | BAD_CELL |
559 *
560 * - CommandCode: 0x04
561 * - Contains Bit Fields:
562 * + @ref LTC4155_EXT_PWR_GOOD "EXT_PWR_GOOD" : External power (Wall or USB) available.
563 * + @ref LTC4155_USBSNS_GOOD "USBSNS_GOOD" : USB input voltage valid.
564 * + @ref LTC4155_WALLSNS_GOOD "WALLSNS_GOOD" : WALL input voltage valid.
565 * + @ref LTC4155_AT_INPUT_ILIM "AT_INPUT_ILIM" : Input current limit control circuit engaged.
566 * + @ref LTC4155_INPUT_UVCL_ACTIVE "INPUT_UVCL_ACTIVE" : Input undervoltage limit control circuit engaged (brownout).
567 * + @ref LTC4155_OVP_ACTIVE "OVP_ACTIVE" : Overvoltage protection fault.
568 * + @ref LTC4155_OTG_FAULT "OTG_FAULT" : USB On-The-Go step-up regulator fault shutdown.
569 * + @ref LTC4155_BAD_CELL "BAD_CELL" : Battery unresponsive to charging for 30 minutes.
570 */
571
572 //!@{
573 #define LTC4155_REG4_SUBADDR 0x04
574 #define LTC4155_REG4 (0 << 12 | (16 - 1) << 8 | LTC4155_REG4_SUBADDR)
575 //!@}
576 /*! @defgroup LTC4155_EXT_PWR_GOOD EXT_PWR_GOOD
577 * @ingroup LTC4155_register_map
578 * @brief EXT_PWR_GOOD Bit Field
579 *
580 * External power (Wall or USB) available.
581 * - Register: @ref LTC4155_REG4 "REG4"
582 * - CommandCode: 0x04
583 * - Size: 1
584 * - Offset: 7
585 * - MSB: 7
586 * - MASK: 0x80
587 * - Access: R
588 * - Default: n/a
589 */
590 //!@{
591 #define LTC4155_EXT_PWR_GOOD_SUBADDR LTC4155_REG4_SUBADDR //!< @ref LTC4155_EXT_PWR_GOOD "EXT_PWR_GOOD"
592 #define LTC4155_EXT_PWR_GOOD_SIZE 1
593 #define LTC4155_EXT_PWR_GOOD_OFFSET 7
594 #define LTC4155_EXT_PWR_GOOD_MASK 0x80
595 #define LTC4155_EXT_PWR_GOOD (LTC4155_EXT_PWR_GOOD_OFFSET << 12 | (LTC4155_EXT_PWR_GOOD_SIZE - 1) << 8 | LTC4155_EXT_PWR_GOOD_SUBADDR)
596 //!@}
597 /*! @defgroup LTC4155_USBSNS_GOOD USBSNS_GOOD
598 * @ingroup LTC4155_register_map
599 * @brief USBSNS_GOOD Bit Field
600 *
601 * USB input voltage valid.
602 * - Register: @ref LTC4155_REG4 "REG4"
603 * - CommandCode: 0x04
604 * - Size: 1
605 * - Offset: 6
606 * - MSB: 6
607 * - MASK: 0x40
608 * - Access: R
609 * - Default: n/a
610 */
611 //!@{
612 #define LTC4155_USBSNS_GOOD_SUBADDR LTC4155_REG4_SUBADDR //!< @ref LTC4155_USBSNS_GOOD "USBSNS_GOOD"
613 #define LTC4155_USBSNS_GOOD_SIZE 1
614 #define LTC4155_USBSNS_GOOD_OFFSET 6
615 #define LTC4155_USBSNS_GOOD_MASK 0x40
616 #define LTC4155_USBSNS_GOOD (LTC4155_USBSNS_GOOD_OFFSET << 12 | (LTC4155_USBSNS_GOOD_SIZE - 1) << 8 | LTC4155_USBSNS_GOOD_SUBADDR)
617 //!@}
618 /*! @defgroup LTC4155_WALLSNS_GOOD WALLSNS_GOOD
619 * @ingroup LTC4155_register_map
620 * @brief WALLSNS_GOOD Bit Field
621 *
622 * WALL input voltage valid.
623 * - Register: @ref LTC4155_REG4 "REG4"
624 * - CommandCode: 0x04
625 * - Size: 1
626 * - Offset: 5
627 * - MSB: 5
628 * - MASK: 0x20
629 * - Access: R
630 * - Default: n/a
631 */
632 //!@{
633 #define LTC4155_WALLSNS_GOOD_SUBADDR LTC4155_REG4_SUBADDR //!< @ref LTC4155_WALLSNS_GOOD "WALLSNS_GOOD"
634 #define LTC4155_WALLSNS_GOOD_SIZE 1
635 #define LTC4155_WALLSNS_GOOD_OFFSET 5
636 #define LTC4155_WALLSNS_GOOD_MASK 0x20
637 #define LTC4155_WALLSNS_GOOD (LTC4155_WALLSNS_GOOD_OFFSET << 12 | (LTC4155_WALLSNS_GOOD_SIZE - 1) << 8 | LTC4155_WALLSNS_GOOD_SUBADDR)
638 //!@}
639 /*! @defgroup LTC4155_AT_INPUT_ILIM AT_INPUT_ILIM
640 * @ingroup LTC4155_register_map
641 * @brief AT_INPUT_ILIM Bit Field
642 *
643 * Input current limit control circuit engaged.
644 * - Register: @ref LTC4155_REG4 "REG4"
645 * - CommandCode: 0x04
646 * - Size: 1
647 * - Offset: 4
648 * - MSB: 4
649 * - MASK: 0x10
650 * - Access: R
651 * - Default: n/a
652 */
653 //!@{
654 #define LTC4155_AT_INPUT_ILIM_SUBADDR LTC4155_REG4_SUBADDR //!< @ref LTC4155_AT_INPUT_ILIM "AT_INPUT_ILIM"
655 #define LTC4155_AT_INPUT_ILIM_SIZE 1
656 #define LTC4155_AT_INPUT_ILIM_OFFSET 4
657 #define LTC4155_AT_INPUT_ILIM_MASK 0x10
658 #define LTC4155_AT_INPUT_ILIM (LTC4155_AT_INPUT_ILIM_OFFSET << 12 | (LTC4155_AT_INPUT_ILIM_SIZE - 1) << 8 | LTC4155_AT_INPUT_ILIM_SUBADDR)
659 //!@}
660 /*! @defgroup LTC4155_INPUT_UVCL_ACTIVE INPUT_UVCL_ACTIVE
661 * @ingroup LTC4155_register_map
662 * @brief INPUT_UVCL_ACTIVE Bit Field
663 *
664 * Input undervoltage limit control circuit engaged (brownout).
665 * - Register: @ref LTC4155_REG4 "REG4"
666 * - CommandCode: 0x04
667 * - Size: 1
668 * - Offset: 3
669 * - MSB: 3
670 * - MASK: 0x08
671 * - Access: R
672 * - Default: n/a
673 */
674 //!@{
675 #define LTC4155_INPUT_UVCL_ACTIVE_SUBADDR LTC4155_REG4_SUBADDR //!< @ref LTC4155_INPUT_UVCL_ACTIVE "INPUT_UVCL_ACTIVE"
676 #define LTC4155_INPUT_UVCL_ACTIVE_SIZE 1
677 #define LTC4155_INPUT_UVCL_ACTIVE_OFFSET 3
678 #define LTC4155_INPUT_UVCL_ACTIVE_MASK 0x08
679 #define LTC4155_INPUT_UVCL_ACTIVE (LTC4155_INPUT_UVCL_ACTIVE_OFFSET << 12 | (LTC4155_INPUT_UVCL_ACTIVE_SIZE - 1) << 8 | LTC4155_INPUT_UVCL_ACTIVE_SUBADDR)
680 //!@}
681 /*! @defgroup LTC4155_OVP_ACTIVE OVP_ACTIVE
682 * @ingroup LTC4155_register_map
683 * @brief OVP_ACTIVE Bit Field
684 *
685 * Overvoltage protection fault.
686 * - Register: @ref LTC4155_REG4 "REG4"
687 * - CommandCode: 0x04
688 * - Size: 1
689 * - Offset: 2
690 * - MSB: 2
691 * - MASK: 0x04
692 * - Access: R
693 * - Default: n/a
694 */
695 //!@{
696 #define LTC4155_OVP_ACTIVE_SUBADDR LTC4155_REG4_SUBADDR //!< @ref LTC4155_OVP_ACTIVE "OVP_ACTIVE"
697 #define LTC4155_OVP_ACTIVE_SIZE 1
698 #define LTC4155_OVP_ACTIVE_OFFSET 2
699 #define LTC4155_OVP_ACTIVE_MASK 0x04
700 #define LTC4155_OVP_ACTIVE (LTC4155_OVP_ACTIVE_OFFSET << 12 | (LTC4155_OVP_ACTIVE_SIZE - 1) << 8 | LTC4155_OVP_ACTIVE_SUBADDR)
701 //!@}
702 /*! @defgroup LTC4155_OTG_FAULT OTG_FAULT
703 * @ingroup LTC4155_register_map
704 * @brief OTG_FAULT Bit Field
705 *
706 * USB On-The-Go step-up regulator fault shutdown.
707 * - Register: @ref LTC4155_REG4 "REG4"
708 * - CommandCode: 0x04
709 * - Size: 1
710 * - Offset: 1
711 * - MSB: 1
712 * - MASK: 0x02
713 * - Access: R
714 * - Default: n/a
715 */
716 //!@{
717 #define LTC4155_OTG_FAULT_SUBADDR LTC4155_REG4_SUBADDR //!< @ref LTC4155_OTG_FAULT "OTG_FAULT"
718 #define LTC4155_OTG_FAULT_SIZE 1
719 #define LTC4155_OTG_FAULT_OFFSET 1
720 #define LTC4155_OTG_FAULT_MASK 0x02
721 #define LTC4155_OTG_FAULT (LTC4155_OTG_FAULT_OFFSET << 12 | (LTC4155_OTG_FAULT_SIZE - 1) << 8 | LTC4155_OTG_FAULT_SUBADDR)
722 //!@}
723 /*! @defgroup LTC4155_BAD_CELL BAD_CELL
724 * @ingroup LTC4155_register_map
725 * @brief BAD_CELL Bit Field
726 *
727 * Battery unresponsive to charging for 30 minutes.
728 * - Register: @ref LTC4155_REG4 "REG4"
729 * - CommandCode: 0x04
730 * - Size: 1
731 * - Offset: 0
732 * - MSB: 0
733 * - MASK: 0x01
734 * - Access: R
735 * - Default: n/a
736 */
737 //!@{
738 #define LTC4155_BAD_CELL_SUBADDR LTC4155_REG4_SUBADDR //!< @ref LTC4155_BAD_CELL "BAD_CELL"
739 #define LTC4155_BAD_CELL_SIZE 1
740 #define LTC4155_BAD_CELL_OFFSET 0
741 #define LTC4155_BAD_CELL_MASK 0x01
742 #define LTC4155_BAD_CELL (LTC4155_BAD_CELL_OFFSET << 12 | (LTC4155_BAD_CELL_SIZE - 1) << 8 | LTC4155_BAD_CELL_SUBADDR)
743 //!@}
744
745 /*! @defgroup LTC4155_REG5 REG5
746 * @ingroup LTC4155_register_map
747 * @brief REG5 Register
748 *
749 * | 7:1 | 0 |
750 * |:------:|:-----------:|
751 * | NTCVAL | NTC_WARNING |
752 *
753 * - CommandCode: 0x05
754 * - Contains Bit Fields:
755 * + @ref LTC4155_NTCVAL "NTCVAL" : NTC pin (thermistor) ADC conversion result.
756 * + @ref LTC4155_NTC_WARNING "NTC_WARNING" : Thermistor temperature out of range for battery charging.
757 */
758
759 //!@{
760 #define LTC4155_REG5_SUBADDR 0x05
761 #define LTC4155_REG5 (0 << 12 | (16 - 1) << 8 | LTC4155_REG5_SUBADDR)
762 //!@}
763 /*! @defgroup LTC4155_NTCVAL NTCVAL
764 * @ingroup LTC4155_register_map
765 * @brief NTCVAL Bit Field
766 *
767 * NTC pin (thermistor) ADC conversion result.
768 * - Register: @ref LTC4155_REG5 "REG5"
769 * - CommandCode: 0x05
770 * - Size: 7
771 * - Offset: 1
772 * - MSB: 7
773 * - MASK: 0xFE
774 * - Access: R
775 * - Default: n/a
776 */
777 //!@{
778 #define LTC4155_NTCVAL_SUBADDR LTC4155_REG5_SUBADDR //!< @ref LTC4155_NTCVAL "NTCVAL"
779 #define LTC4155_NTCVAL_SIZE 7
780 #define LTC4155_NTCVAL_OFFSET 1
781 #define LTC4155_NTCVAL_MASK 0xFE
782 #define LTC4155_NTCVAL (LTC4155_NTCVAL_OFFSET << 12 | (LTC4155_NTCVAL_SIZE - 1) << 8 | LTC4155_NTCVAL_SUBADDR)
783 //!@}
784 /*! @defgroup LTC4155_NTC_WARNING NTC_WARNING
785 * @ingroup LTC4155_register_map
786 * @brief NTC_WARNING Bit Field
787 *
788 * Thermistor temperature out of range for battery charging.
789 * - Register: @ref LTC4155_REG5 "REG5"
790 * - CommandCode: 0x05
791 * - Size: 1
792 * - Offset: 0
793 * - MSB: 0
794 * - MASK: 0x01
795 * - Access: R
796 * - Default: n/a
797 */
798 //!@{
799 #define LTC4155_NTC_WARNING_SUBADDR LTC4155_REG5_SUBADDR //!< @ref LTC4155_NTC_WARNING "NTC_WARNING"
800 #define LTC4155_NTC_WARNING_SIZE 1
801 #define LTC4155_NTC_WARNING_OFFSET 0
802 #define LTC4155_NTC_WARNING_MASK 0x01
803 #define LTC4155_NTC_WARNING (LTC4155_NTC_WARNING_OFFSET << 12 | (LTC4155_NTC_WARNING_SIZE - 1) << 8 | LTC4155_NTC_WARNING_SUBADDR)
804 //!@}
805
806 /*! @defgroup LTC4155_REG6 REG6
807 * @ingroup LTC4155_register_map
808 * @brief REG6 Register
809 *
810 * | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
811 * |:------------------:|:----------------:|:-----------------:|:--------------:|:------------------:|:---------------------:|:-----------:|:--------:|
812 * | ENABLE_CHARGER_INT | ENABLE_FAULT_INT | ENABLE_EXTPWR_INT | ENABLE_OTG_INT | ENABLE_AT_ILIM_INT | ENABLE_INPUT_UVCL_INT | REQUEST_OTG | RESERVED |
813 *
814 * Interrupt Mask Resister
815 * - CommandCode: 0x06
816 * - Contains Bit Fields:
817 * + @ref LTC4155_ENABLE_CHARGER_INT "ENABLE_CHARGER_INT" : Enable battery CHARGER_STATUS interrupts.
818 * + @ref LTC4155_ENABLE_FAULT_INT "ENABLE_FAULT_INT" : Enable OVP_ACTIVE, OTG_FAULT, BAD_CELL, and NTCSTAT = Hot_Fault interrupts.
819 * + @ref LTC4155_ENABLE_EXTPWR_INT "ENABLE_EXTPWR_INT" : Enable USBSNS_GOOD, WALLSNS_GOOD, EXT_PWR_GOOD external power available interrupts.
820 * + @ref LTC4155_ENABLE_OTG_INT "ENABLE_OTG_INT" : Enable ID_PIN_DETECT and OTG_ENABLED USB On-The-Go interrupts.
821 * + @ref LTC4155_ENABLE_AT_ILIM_INT "ENABLE_AT_ILIM_INT" : Enable AT_INPUT_ILIM interrupts.
822 * + @ref LTC4155_ENABLE_INPUT_UVCL_INT "ENABLE_INPUT_UVCL_INT" : Enable INPUT_UVCL_ACTIVE interrupts.
823 * + @ref LTC4155_REQUEST_OTG "REQUEST_OTG" : USB On-The-Go step-up voltage converter manual activation setting.
824 * + @ref LTC4155_RESERVED "RESERVED" : Always set to 0.
825 */
826
827 //!@{
828 #define LTC4155_REG6_SUBADDR 0x06
829 #define LTC4155_REG6 (0 << 12 | (16 - 1) << 8 | LTC4155_REG6_SUBADDR)
830 //!@}
831 /*! @defgroup LTC4155_ENABLE_CHARGER_INT ENABLE_CHARGER_INT
832 * @ingroup LTC4155_register_map
833 * @brief ENABLE_CHARGER_INT Bit Field
834 *
835 * Enable battery CHARGER_STATUS interrupts.
836 * - Register: @ref LTC4155_REG6 "REG6"
837 * - CommandCode: 0x06
838 * - Size: 1
839 * - Offset: 7
840 * - MSB: 7
841 * - MASK: 0x80
842 * - Access: R/W
843 * - Default: 0
844 */
845 //!@{
846 #define LTC4155_ENABLE_CHARGER_INT_SUBADDR LTC4155_REG6_SUBADDR //!< @ref LTC4155_ENABLE_CHARGER_INT "ENABLE_CHARGER_INT"
847 #define LTC4155_ENABLE_CHARGER_INT_SIZE 1
848 #define LTC4155_ENABLE_CHARGER_INT_OFFSET 7
849 #define LTC4155_ENABLE_CHARGER_INT_MASK 0x80
850 #define LTC4155_ENABLE_CHARGER_INT (LTC4155_ENABLE_CHARGER_INT_OFFSET << 12 | (LTC4155_ENABLE_CHARGER_INT_SIZE - 1) << 8 | LTC4155_ENABLE_CHARGER_INT_SUBADDR)
851 //!@}
852 /*! @defgroup LTC4155_ENABLE_FAULT_INT ENABLE_FAULT_INT
853 * @ingroup LTC4155_register_map
854 * @brief ENABLE_FAULT_INT Bit Field
855 *
856 * Enable OVP_ACTIVE, OTG_FAULT, BAD_CELL, and NTCSTAT = Hot_Fault interrupts.
857 * - Register: @ref LTC4155_REG6 "REG6"
858 * - CommandCode: 0x06
859 * - Size: 1
860 * - Offset: 6
861 * - MSB: 6
862 * - MASK: 0x40
863 * - Access: R/W
864 * - Default: 0
865 */
866 //!@{
867 #define LTC4155_ENABLE_FAULT_INT_SUBADDR LTC4155_REG6_SUBADDR //!< @ref LTC4155_ENABLE_FAULT_INT "ENABLE_FAULT_INT"
868 #define LTC4155_ENABLE_FAULT_INT_SIZE 1
869 #define LTC4155_ENABLE_FAULT_INT_OFFSET 6
870 #define LTC4155_ENABLE_FAULT_INT_MASK 0x40
871 #define LTC4155_ENABLE_FAULT_INT (LTC4155_ENABLE_FAULT_INT_OFFSET << 12 | (LTC4155_ENABLE_FAULT_INT_SIZE - 1) << 8 | LTC4155_ENABLE_FAULT_INT_SUBADDR)
872 //!@}
873 /*! @defgroup LTC4155_ENABLE_EXTPWR_INT ENABLE_EXTPWR_INT
874 * @ingroup LTC4155_register_map
875 * @brief ENABLE_EXTPWR_INT Bit Field
876 *
877 * Enable USBSNS_GOOD, WALLSNS_GOOD, EXT_PWR_GOOD external power available interrupts.
878 * - Register: @ref LTC4155_REG6 "REG6"
879 * - CommandCode: 0x06
880 * - Size: 1
881 * - Offset: 5
882 * - MSB: 5
883 * - MASK: 0x20
884 * - Access: R/W
885 * - Default: 0
886 */
887 //!@{
888 #define LTC4155_ENABLE_EXTPWR_INT_SUBADDR LTC4155_REG6_SUBADDR //!< @ref LTC4155_ENABLE_EXTPWR_INT "ENABLE_EXTPWR_INT"
889 #define LTC4155_ENABLE_EXTPWR_INT_SIZE 1
890 #define LTC4155_ENABLE_EXTPWR_INT_OFFSET 5
891 #define LTC4155_ENABLE_EXTPWR_INT_MASK 0x20
892 #define LTC4155_ENABLE_EXTPWR_INT (LTC4155_ENABLE_EXTPWR_INT_OFFSET << 12 | (LTC4155_ENABLE_EXTPWR_INT_SIZE - 1) << 8 | LTC4155_ENABLE_EXTPWR_INT_SUBADDR)
893 //!@}
894 /*! @defgroup LTC4155_ENABLE_OTG_INT ENABLE_OTG_INT
895 * @ingroup LTC4155_register_map
896 * @brief ENABLE_OTG_INT Bit Field
897 *
898 * Enable ID_PIN_DETECT and OTG_ENABLED USB On-The-Go interrupts.
899 * - Register: @ref LTC4155_REG6 "REG6"
900 * - CommandCode: 0x06
901 * - Size: 1
902 * - Offset: 4
903 * - MSB: 4
904 * - MASK: 0x10
905 * - Access: R/W
906 * - Default: 0
907 */
908 //!@{
909 #define LTC4155_ENABLE_OTG_INT_SUBADDR LTC4155_REG6_SUBADDR //!< @ref LTC4155_ENABLE_OTG_INT "ENABLE_OTG_INT"
910 #define LTC4155_ENABLE_OTG_INT_SIZE 1
911 #define LTC4155_ENABLE_OTG_INT_OFFSET 4
912 #define LTC4155_ENABLE_OTG_INT_MASK 0x10
913 #define LTC4155_ENABLE_OTG_INT (LTC4155_ENABLE_OTG_INT_OFFSET << 12 | (LTC4155_ENABLE_OTG_INT_SIZE - 1) << 8 | LTC4155_ENABLE_OTG_INT_SUBADDR)
914 //!@}
915 /*! @defgroup LTC4155_ENABLE_AT_ILIM_INT ENABLE_AT_ILIM_INT
916 * @ingroup LTC4155_register_map
917 * @brief ENABLE_AT_ILIM_INT Bit Field
918 *
919 * Enable AT_INPUT_ILIM interrupts.
920 * - Register: @ref LTC4155_REG6 "REG6"
921 * - CommandCode: 0x06
922 * - Size: 1
923 * - Offset: 3
924 * - MSB: 3
925 * - MASK: 0x08
926 * - Access: R/W
927 * - Default: 0
928 */
929 //!@{
930 #define LTC4155_ENABLE_AT_ILIM_INT_SUBADDR LTC4155_REG6_SUBADDR //!< @ref LTC4155_ENABLE_AT_ILIM_INT "ENABLE_AT_ILIM_INT"
931 #define LTC4155_ENABLE_AT_ILIM_INT_SIZE 1
932 #define LTC4155_ENABLE_AT_ILIM_INT_OFFSET 3
933 #define LTC4155_ENABLE_AT_ILIM_INT_MASK 0x08
934 #define LTC4155_ENABLE_AT_ILIM_INT (LTC4155_ENABLE_AT_ILIM_INT_OFFSET << 12 | (LTC4155_ENABLE_AT_ILIM_INT_SIZE - 1) << 8 | LTC4155_ENABLE_AT_ILIM_INT_SUBADDR)
935 //!@}
936 /*! @defgroup LTC4155_ENABLE_INPUT_UVCL_INT ENABLE_INPUT_UVCL_INT
937 * @ingroup LTC4155_register_map
938 * @brief ENABLE_INPUT_UVCL_INT Bit Field
939 *
940 * Enable INPUT_UVCL_ACTIVE interrupts.
941 * - Register: @ref LTC4155_REG6 "REG6"
942 * - CommandCode: 0x06
943 * - Size: 1
944 * - Offset: 2
945 * - MSB: 2
946 * - MASK: 0x04
947 * - Access: R/W
948 * - Default: 0
949 */
950 //!@{
951 #define LTC4155_ENABLE_INPUT_UVCL_INT_SUBADDR LTC4155_REG6_SUBADDR //!< @ref LTC4155_ENABLE_INPUT_UVCL_INT "ENABLE_INPUT_UVCL_INT"
952 #define LTC4155_ENABLE_INPUT_UVCL_INT_SIZE 1
953 #define LTC4155_ENABLE_INPUT_UVCL_INT_OFFSET 2
954 #define LTC4155_ENABLE_INPUT_UVCL_INT_MASK 0x04
955 #define LTC4155_ENABLE_INPUT_UVCL_INT (LTC4155_ENABLE_INPUT_UVCL_INT_OFFSET << 12 | (LTC4155_ENABLE_INPUT_UVCL_INT_SIZE - 1) << 8 | LTC4155_ENABLE_INPUT_UVCL_INT_SUBADDR)
956 //!@}
957 /*! @defgroup LTC4155_REQUEST_OTG REQUEST_OTG
958 * @ingroup LTC4155_register_map
959 * @brief REQUEST_OTG Bit Field
960 *
961 * USB On-The-Go step-up voltage converter manual activation setting.
962 * - Register: @ref LTC4155_REG6 "REG6"
963 * - CommandCode: 0x06
964 * - Size: 1
965 * - Offset: 1
966 * - MSB: 1
967 * - MASK: 0x02
968 * - Access: R/W
969 * - Default: 0
970 */
971 //!@{
972 #define LTC4155_REQUEST_OTG_SUBADDR LTC4155_REG6_SUBADDR //!< @ref LTC4155_REQUEST_OTG "REQUEST_OTG"
973 #define LTC4155_REQUEST_OTG_SIZE 1
974 #define LTC4155_REQUEST_OTG_OFFSET 1
975 #define LTC4155_REQUEST_OTG_MASK 0x02
976 #define LTC4155_REQUEST_OTG (LTC4155_REQUEST_OTG_OFFSET << 12 | (LTC4155_REQUEST_OTG_SIZE - 1) << 8 | LTC4155_REQUEST_OTG_SUBADDR)
977 //!@}
978 /*! @defgroup LTC4155_RESERVED RESERVED
979 * @ingroup LTC4155_register_map
980 * @brief RESERVED Bit Field
981 *
982 * Always set to 0.
983 * - Register: @ref LTC4155_REG6 "REG6"
984 * - CommandCode: 0x06
985 * - Size: 1
986 * - Offset: 0
987 * - MSB: 0
988 * - MASK: 0x01
989 * - Access: R/W
990 * - Default: 0
991 */
992 //!@{
993 #define LTC4155_RESERVED_SUBADDR LTC4155_REG6_SUBADDR //!< @ref LTC4155_RESERVED "RESERVED"
994 #define LTC4155_RESERVED_SIZE 1
995 #define LTC4155_RESERVED_OFFSET 0
996 #define LTC4155_RESERVED_MASK 0x01
997 #define LTC4155_RESERVED (LTC4155_RESERVED_OFFSET << 12 | (LTC4155_RESERVED_SIZE - 1) << 8 | LTC4155_RESERVED_SUBADDR)
998 //!@}
999
1000 /*! @defgroup LTC4155_REG7 REG7
1001 * @ingroup LTC4155_register_map
1002 * @brief REG7 Register
1003 *
1004 * | 7:0 |
1005 * |:------------:|
1006 * | ARM_SHIPMODE |
1007 *
1008 * - CommandCode: 0x07
1009 * - Contains Bit Fields:
1010 * + @ref LTC4155_ARM_SHIPMODE "ARM_SHIPMODE" : Write any data to this address to enable ship-and-store shutdown mode
1011 */
1012
1013 //!@{
1014 #define LTC4155_REG7_SUBADDR 0x07
1015 #define LTC4155_REG7 (0 << 12 | (16 - 1) << 8 | LTC4155_REG7_SUBADDR)
1016 //!@}
1017 /*! @defgroup LTC4155_ARM_SHIPMODE ARM_SHIPMODE
1018 * @ingroup LTC4155_register_map
1019 * @brief ARM_SHIPMODE Bit Field
1020 *
1021 * Write any data to this address to enable ship-and-store shutdown mode
1022 * - Register: @ref LTC4155_REG7 "REG7"
1023 * - CommandCode: 0x07
1024 * - Size: 8
1025 * - Offset: 0
1026 * - MSB: 7
1027 * - MASK: 0xFF
1028 * - Access: W
1029 * - Default: 0
1030 */
1031 //!@{
1032 #define LTC4155_ARM_SHIPMODE_SUBADDR LTC4155_REG7_SUBADDR //!< @ref LTC4155_ARM_SHIPMODE "ARM_SHIPMODE"
1033 #define LTC4155_ARM_SHIPMODE_SIZE 8
1034 #define LTC4155_ARM_SHIPMODE_OFFSET 0
1035 #define LTC4155_ARM_SHIPMODE_MASK 0xFF
1036 #define LTC4155_ARM_SHIPMODE (LTC4155_ARM_SHIPMODE_OFFSET << 12 | (LTC4155_ARM_SHIPMODE_SIZE - 1) << 8 | LTC4155_ARM_SHIPMODE_SUBADDR)
1037 #define LTC4155_ARM_SHIPMODE_PRESET_ARM 0x01
1038 //!@}
1039
1040 #endif