;;Reset = False;; ;;ReadInterface = True;; ---------------------------------------------------------- Revision History ---------------------------------------------------------- ; Version 3.6 ; Optimized HDMI mid-band PLL writes: ; 68 3E 7B ; ADI Required Write ; 68 3F 5E ; ADI Required Write ; previous values: ; 68 3E E9 ; 68 3F 46 ; ; ; Added following write to Pseudo Differential and Fully Differential CVBS scripts for Coarse Clamp Circuitry Optimization: ; F2 00 10 ; ADI Required Write ; ; ; Added the following writes to Pseudo Differential and Fully Differential CVBS scripts for Common Mode Clamps Optimization: ; F2 60 A0 ; ADI Required Write ; delay 25 ; ; ; ; The following writes were moved in the analog input scripts to optimize the configuration sequence in order to obtain the best locking time: ; ; Moved following write to right after SD core power up write (F2 0F 00 ; Exit Power Down Mode): ; F2 5X CX ; ADI Required Write ; ; Moved block of writes below after writes optimizing clamping operation: ; F2 03 42 ; Tri-S Output Drivers, PwrDwn 656 pads ; F2 04 07 ; Power-up INTRQ pad, & Enable SFL ; F2 13 00 ; ADI Required Write ; F2 17 41 ; Select SH1 ; F2 31 12 ; ADI Required Write ; ; Moved following write to after Common Mode Clamps Optimization settings: ; F2 5F A8 ; SHA gain for Div4 ; ; Moved SDP fast locking configuration writes below after writes optimizing clamping operation: ; F2 0E 80 ; ADI Required Write ; F2 D9 44 ; ADI Required Write ; F2 0E 40 ; Select User Sub Map 2 ; F2 E0 01 ; Select fast Switching Mode ; F2 0E 00 ; Required Write ; ; ; Added Pixel port Output options for Fast switch CVBS scripts ; ; ; Copied the latest writes from the HDMI and Analog scripts to the free-run scripts at the end of the overall list. ; ; ; --------------------------------------------------------------------- ; ; Version 3.4-3.5 ; Unreleased ; ; --------------------------------------------------------------------- ; Version 3.3 ; For 4:2:2 SDR Pixel output scripts only from CP core path (not SD core), added writes below for optimized channel alignment: ; 44 3E 08 ; uv_dval_inv [3] = 1'b1 (Pr, Pb timing adjust) ; E0 04 40 ; ADI Required Write ; ; Changed following HDMI setting for optimization ; 68 3E 69 ; ADI Required Write ; replaced with: ; 68 3E E9 ; ADI Required Write ; ; Changed LLC DLL phase setting from 5'b11100 to 5'b11111 ; ; Removed Diagnostic writes from Analog CVBS Single Ended scripts that had them ; E0 18 19 ; DIAG1 Diagnostic Function - Enable Upper Level Slicer Only and set slice voltage to 975mV ; E0 19 19 ; DIAG2 Diagnostic Function - Enable Upper Level Slicer Only and set slice voltage to 975mV ; ; Added writes to all Analog Input Modes scripts to optimize lock time when switching from no input to input with dark video image: ; F2 0E 80 ; ADI Required Write ; F2 9C 00 ; ADI Required Write ; F2 9C FF ; ADI Required Write ; F2 0E 00 ; ADI Required Write ; ; Added write to all HDMI input MIPI scripts for operation below 600Mbps to allow for switching between resolutions/configurations with only power-down/up before/after change along with RX reset as per the recommended sequence. ; 94 DB 10 ; ADI Required Write ; ; Changed description for SDR/DDR TTL to 4-Lane MIPI to include 480p and 576p and for SDR/DDR TTL to 2-Lane MIPI to include 480i and 576i. ; Changed from ':06-03 8-Bit SDR TTL to MIPI TX-A CSI 4-Lane - 720p,1080i - YUV422 8-Bit:' to ':06-03 8-Bit SDR TTL to MIPI TX-A CSI 4-Lane - 480p,576p,720p,1080i - YUV422 8-Bit:' ; Changed from ':07-03 8-Bit DDR TTL to MIPI TX-A CSI 4-Lane - 720p,1080i - YUV422 8-Bit:' to ':07-03 8-Bit DDR TTL to MIPI TX-A CSI 4-Lane - 480p,576p,720p,1080i - YUV422 8-Bit:' ; Changed from ':06-02 8-Bit SDR TTL to MIPI TX-A CSI 2-Lane - 480p,576p,720p,1080i - YUV422 8-Bit:' to ':06-02 8-Bit SDR TTL to MIPI TX-A CSI 2-Lane - 480i,576i,480p,576p,720p,1080i - YUV422 8-Bit:' ; Changed from ':07-02 8-Bit DDR TTL to MIPI TX-A CSI 2-Lane - 480p,576p,720p,1080i - YUV422 8-Bit:' to ':07-02 8-Bit DDR TTL to MIPI TX-A CSI 2-Lane - 480i,576i,480p,576p,720p,1080i - YUV422 8-Bit:' ; ; ; ------------------------------------------------------ ; ; Version 3.2 ; ES3 Version. Valid for ES3.0 and ES3.1 silicon. ; Identical to Version 2.6 for ES2 silicon. ; ; ---------------------------------------------------------- ; ; Version 2.6 ; ES2 Version. ; Changed ADI Recommended Write comments to ADI Required Write ; Added following new ADI Required Writes for the HDMI Receiver ; 68 98 FF ; ADI Required Write ; 68 99 E3 ; ADI Required Write ; 68 9A 00 ; ADI Required Write ; 68 9B 0A ; ADI Required Write ; 68 9D 40 ; ADI Required Write ; 68 CB 09 ; ADI Required Write ; Removed following ADI Recommended Write for HDMI Receiver ; 68 9C 00 ; ADI Recommended Write ; Changed ; E0 1D 08 - reduce LLC drv_strength to mid from max. ; E0 0C FC - LLC DLL to 28d ; Added to pixel port SD CVBS, YC, YPrPb scripts ; E0 18 19 ; DIAG1 Diagnostic Function - Enable Upper Level Slicer Only and set slice voltage to 975mV ; F2 80 51 ; ADI Required Write ; F2 81 51 ; ADI Required Write ; F2 82 68 ; ADI Required Write ; ; --------------------------------------------------------------------- ; ; Version 2.5 ; Unreleased ; ; --------------------------------------------------------------------- ; ; Version 2.4 ; ES2 Version. ; Changed write to register IO Map 0x03 - Changed from 0x96 to 0x86 in following two scripts as free-run resolution changed from 50Hz frame rate ; '01-24 HDMI to MIPI TxA CSI 4-Lane - YUV422 10-Bit, Over 600Mbps' ; '01-28 HDMI to MIPI TxA CSI 4-Lane - RGB666, Over 600Mbps' ; Added MIPI o/p freerun scripts into script Family 08 - 'Free-run Scripts' ; Added Analog Fast switchign scripts ; Added MIPI TTL Input scripts - family 6 & 7 ; Renumbered Family 11 - Free run scripts to family 8 ; Modification to MIPI scripts ; HDMI scripts - E0 00 40 ; Not added as its a default setting: 68 9C 08 ; Added - 68 CB 01 ; ADI Recommended Write ; ; --------------------------------------------------------------------- ; ; Version 2.2-2.3 ; Unreleased ; ; --------------------------------------------------------------------- ; ; Version 2.1 ; ES2 Version. ; New ADI REQUIRED WRITE (68 A3 01) ; New LLC DLL setting (E0 0C E8) ; New INV_LLC setting (E0 1D 1C) ; FreeRun scripts added ; ; --------------------------------------------------------------------- ; ; Version 2.0 ; ES2 Version. ; ; --------------------------------------------------------------------- ; ; Version 1.0 ; Initial ES1 Version ; ; ---------------------------------------------------------- ##Script Details## :Version 3.6c Oct 24th 2014 - ADV7481ES3: End ##01 HDMI Input scripts## ; Supported Formats For Script Below - 720x480p60, 720(1440)x480i60, 720x576p50, 720(1440)x576i50, 640x480(VGA)@60, 800x480(WVGA)@60 :01-01 HDMI to MIPI TxA CSI 1-Lane - YUV422 8-Bit, Up to 600Mbps: E0 FF FF ; SW reset delay 5 ; E0 01 76 ; ADI Required Write E0 05 4A ; Setting Vid_Std to 720x480p60 E0 F2 01 ; Enable I2C Read Auto-Increment E0 F3 4C ; DPLL Map Address Set to 0x4C E0 F4 44 ; CP Map Address Set to 0x44 E0 F5 68 ; HDMI RX Map Address Set to 0x68 E0 F6 6C ; EDID Map Address Set to 0x6C E0 F7 64 ; HDMI RX Repeater Map Address Set to 0x64 E0 F8 62 ; HDMI RX Infoframe Map Address Set to 0x62 E0 F9 F0 ; CBUS Map Address Set to 0xF0 E0 FA 82 ; CEC Map Address Set to 0x82 E0 FB F2 ; SDP Main Map Address Set to 0xF2 E0 FC 90 ; CSI-TXB Map Address Set to 0x90 E0 FD 94 ; CSI-TXA Map Address Set to 0x94 E0 00 40 ; Disable chip powerdown & Enable HDMI Rx block 64 40 83 ; Enable HDCP 1.1 68 00 08 ; Foreground Channel = A 68 98 FF ; ADI Required Write 68 99 A3 ; ADI Required Write 68 9A 00 ; ADI Required Write 68 9B 0A ; ADI Required Write 68 9D 40 ; ADI Required Write 68 CB 09 ; ADI Required Write 68 3D 10 ; ADI Required Write 68 3E 7B ; ADI Required Write 68 3F 5E ; ADI Required Write 68 4E FE ; ADI Required Write 68 4F 18 ; ADI Required Write 68 57 A3 ; ADI Required Write 68 58 04 ; ADI Required Write 68 85 10 ; ADI Required Write 68 83 00 ; Enable All Terminations 68 A3 01 ; ADI Required Write 68 BE 00 ; ADI Required Write 68 6C 01 ; HPA Manual Enable 68 F8 01 ; HPA Asserted 68 0F 00 ; Audio Mute Speed Set to Fastest (Smallest Step Size) E0 04 00 ; YCrCb output E0 12 F2 ; CSC Depends on ip Packets - SDR422 set E0 17 80 ; Luma & Chroma Values Can Reach 254d E0 03 86 ; CP-Insert_AV_Code 44 7C 00 ; ADI Required Write E0 0C E0 ; Enable LLC_DLL & Double LLC Timing E0 0E DD ; LLC/PIX/SPI PINS TRISTATED AUD Outputs Enabled E0 10 A0 ; Enable 4-lane CSI Tx & Pixel Port 94 00 81 ; Enable 1-lane MIPI 94 00 A1 ; Set Auto DPHY Timing 94 DB 10 ; ADI Required Write 94 D6 07 ; ADI Required Write 94 C4 0A ; ADI Required Write 94 71 33 ; ADI Required Write 94 72 11 ; ADI Required Write 94 F0 00 ; i2c_dphy_pwdn - 1'b0 94 31 82 ; ADI Required Write 94 1E 40 ; ADI Required Write 94 DA 01 ; i2c_mipi_pll_en - 1'b1 delay 2 ; 94 00 21 ; Power-up CSI-TX delay 1 ; 94 C1 2B ; ADI Required Write delay 1 ; 94 31 80 ; ADI Required Write End ; Supported Formats For Script Below - 800x600(SVGA)@60 :01-02 HDMI to MIPI TxA CSI 1-Lane - YUV422 8-Bit, Over 600Mbps: E0 FF FF ; SW reset delay 5 ; E0 01 76 ; ADI Required Write E0 05 81 ; Setting Vid_Std to 800x600(SVGA)@60 E0 F2 01 ; Enable I2C Read Auto-Increment E0 F3 4C ; DPLL Map Address Set to 0x4C E0 F4 44 ; CP Map Address Set to 0x44 E0 F5 68 ; HDMI RX Map Address Set to 0x68 E0 F6 6C ; EDID Map Address Set to 0x6C E0 F7 64 ; HDMI RX Repeater Map Address Set to 0x64 E0 F8 62 ; HDMI RX Infoframe Map Address Set to 0x62 E0 F9 F0 ; CBUS Map Address Set to 0xF0 E0 FA 82 ; CEC Map Address Set to 0x82 E0 FB F2 ; SDP Main Map Address Set to 0xF2 E0 FC 90 ; CSI-TXB Map Address Set to 0x90 E0 FD 94 ; CSI-TXA Map Address Set to 0x94 E0 00 40 ; Disable chip powerdown & Enable HDMI Rx block 64 40 83 ; Enable HDCP 1.1 68 00 08 ; Foreground Channel = A 68 98 FF ; ADI Required Write 68 99 A3 ; ADI Required Write 68 9A 00 ; ADI Required Write 68 9B 0A ; ADI Required Write 68 9D 40 ; ADI Required Write 68 CB 09 ; ADI Required Write 68 3D 10 ; ADI Required Write 68 3E 7B ; ADI Required Write 68 3F 5E ; ADI Required Write 68 4E FE ; ADI Required Write 68 4F 18 ; ADI Required Write 68 57 A3 ; ADI Required Write 68 58 04 ; ADI Required Write 68 85 10 ; ADI Required Write 68 83 00 ; Enable All Terminations 68 A3 01 ; ADI Required Write 68 BE 00 ; ADI Required Write 68 6C 01 ; HPA Manual Enable 68 F8 01 ; HPA Asserted 68 0F 00 ; Audio Mute Speed Set to Fastest (Smallest Step Size) E0 04 00 ; YCrCb output E0 12 F2 ; CSC Depends on ip Packets - SDR422 set E0 17 80 ; Luma & Chroma Values Can Reach 254d E0 03 86 ; CP-Insert_AV_Code 44 7C 00 ; ADI Required Write E0 0C E0 ; Enable LLC_DLL & Double LLC Timing E0 0E DD ; LLC/PIX/SPI PINS TRISTATED AUD Outputs Enabled E0 10 A0 ; Enable 4-lane CSI Tx & Pixel Port 94 00 81 ; Enable 1-lane MIPI 94 00 A1 ; Set Auto DPHY Timing 94 DB 13 ; ADI Required Write 94 D6 07 ; ADI Required Write 94 C4 0A ; ADI Required Write 94 71 33 ; ADI Required Write 94 72 11 ; ADI Required Write 94 F0 00 ; i2c_dphy_pwdn - 1'b0 94 31 82 ; ADI Required Write 94 1E 40 ; ADI Required Write 94 DA 01 ; i2c_mipi_pll_en - 1'b1 delay 2 ; 94 00 21 ; Power-up CSI-TX delay 1 ; 94 C1 2B ; ADI Required Write delay 1 ; 94 31 80 ; ADI Required Write End ; Supported Formats For Script Below - 720x480p60, 720(1440)x480i60, 720x576p50, 720(1440)x576i50, 640x480(VGA)@60 :01-03 HDMI to MIPI TxA CSI 1-Lane - YUV422 10-Bit, Up to 600Mbps: E0 FF FF ; SW reset delay 5 ; E0 01 76 ; ADI Required Write E0 05 4A ; Setting Vid_Std to 720x480p60 E0 F2 01 ; Enable I2C Read Auto-Increment E0 F3 4C ; DPLL Map Address Set to 0x4C E0 F4 44 ; CP Map Address Set to 0x44 E0 F5 68 ; HDMI RX Map Address Set to 0x68 E0 F6 6C ; EDID Map Address Set to 0x6C E0 F7 64 ; HDMI RX Repeater Map Address Set to 0x64 E0 F8 62 ; HDMI RX Infoframe Map Address Set to 0x62 E0 F9 F0 ; CBUS Map Address Set to 0xF0 E0 FA 82 ; CEC Map Address Set to 0x82 E0 FB F2 ; SDP Main Map Address Set to 0xF2 E0 FC 90 ; CSI-TXB Map Address Set to 0x90 E0 FD 94 ; CSI-TXA Map Address Set to 0x94 E0 00 40 ; Disable chip powerdown & Enable HDMI Rx block 64 40 83 ; Enable HDCP 1.1 68 00 08 ; Foreground Channel = A 68 98 FF ; ADI Required Write 68 99 A3 ; ADI Required Write 68 9A 00 ; ADI Required Write 68 9B 0A ; ADI Required Write 68 9D 40 ; ADI Required Write 68 CB 09 ; ADI Required Write 68 3D 10 ; ADI Required Write 68 3E 7B ; ADI Required Write 68 3F 5E ; ADI Required Write 68 4E FE ; ADI Required Write 68 4F 18 ; ADI Required Write 68 57 A3 ; ADI Required Write 68 58 04 ; ADI Required Write 68 85 10 ; ADI Required Write 68 83 00 ; Enable All Terminations 68 A3 01 ; ADI Required Write 68 BE 00 ; ADI Required Write 68 6C 01 ; HPA Manual Enable 68 F8 01 ; HPA Asserted 68 0F 00 ; Audio Mute Speed Set to Fastest (Smallest Step Size) E0 04 00 ; YCrCb output E0 12 F3 ; CSC Depends on ip Packets - SDR422 set - 10Bit E0 17 80 ; Luma & Chroma Values Can Reach 254d E0 03 86 ; CP-Insert_AV_Code 44 7C 00 ; ADI Required Write E0 0C E0 ; Enable LLC_DLL & Double LLC Timing E0 0E DD ; LLC/PIX/SPI PINS TRISTATED AUD Outputs Enabled E0 10 A0 ; Enable 4-lane CSI Tx & Pixel Port 94 00 81 ; Enable 1-lane MIPI 94 00 A1 ; Set Auto DPHY Timing 94 DB 10 ; ADI Required Write 94 D6 07 ; ADI Required Write 94 C4 0A ; ADI Required Write 94 71 33 ; ADI Required Write 94 72 11 ; ADI Required Write 94 F0 00 ; i2c_dphy_pwdn - 1'b0 94 31 82 ; ADI Required Write 94 1E 40 ; ADI Required Write 94 DA 01 ; i2c_mipi_pll_en - 1'b1 delay 2 ; 94 00 21 ; Power-up CSI-TX delay 1 ; 94 C1 2B ; ADI Required Write delay 1 ; 94 31 80 ; ADI Required Write End ; Supported Formats For Script Below - 800x600(SVGA)@60, 800x480(WVGA)@60 :01-04 HDMI to MIPI TxA CSI 1-Lane - YUV422 10-Bit, Over 600Mbps: E0 FF FF ; SW reset delay 5 ; E0 01 76 ; ADI Required Write E0 05 81 ; Setting Vid_Std to 800x600(SVGA)@60 E0 F2 01 ; Enable I2C Read Auto-Increment E0 F3 4C ; DPLL Map Address Set to 0x4C E0 F4 44 ; CP Map Address Set to 0x44 E0 F5 68 ; HDMI RX Map Address Set to 0x68 E0 F6 6C ; EDID Map Address Set to 0x6C E0 F7 64 ; HDMI RX Repeater Map Address Set to 0x64 E0 F8 62 ; HDMI RX Infoframe Map Address Set to 0x62 E0 F9 F0 ; CBUS Map Address Set to 0xF0 E0 FA 82 ; CEC Map Address Set to 0x82 E0 FB F2 ; SDP Main Map Address Set to 0xF2 E0 FC 90 ; CSI-TXB Map Address Set to 0x90 E0 FD 94 ; CSI-TXA Map Address Set to 0x94 E0 00 40 ; Disable chip powerdown & Enable HDMI Rx block 64 40 83 ; Enable HDCP 1.1 68 00 08 ; Foreground Channel = A 68 98 FF ; ADI Required Write 68 99 A3 ; ADI Required Write 68 9A 00 ; ADI Required Write 68 9B 0A ; ADI Required Write 68 9D 40 ; ADI Required Write 68 CB 09 ; ADI Required Write 68 3D 10 ; ADI Required Write 68 3E 7B ; ADI Required Write 68 3F 5E ; ADI Required Write 68 4E FE ; ADI Required Write 68 4F 18 ; ADI Required Write 68 57 A3 ; ADI Required Write 68 58 04 ; ADI Required Write 68 85 10 ; ADI Required Write 68 83 00 ; Enable All Terminations 68 A3 01 ; ADI Required Write 68 BE 00 ; ADI Required Write 68 6C 01 ; HPA Manual Enable 68 F8 01 ; HPA Asserted 68 0F 00 ; Audio Mute Speed Set to Fastest (Smallest Step Size) E0 04 00 ; YCrCb output E0 12 F3 ; CSC Depends on ip Packets - SDR422 set - 10Bit E0 17 80 ; Luma & Chroma Values Can Reach 254d E0 03 86 ; CP-Insert_AV_Code 44 7C 00 ; ADI Required Write E0 0C E0 ; Enable LLC_DLL & Double LLC Timing E0 0E DD ; LLC/PIX/SPI PINS TRISTATED AUD Outputs Enabled E0 10 A0 ; Enable 4-lane CSI Tx & Pixel Port 94 00 81 ; Enable 1-lane MIPI 94 00 A1 ; Set Auto DPHY Timing 94 DB 13 ; ADI Required Write 94 D6 07 ; ADI Required Write 94 C4 0A ; ADI Required Write 94 71 33 ; ADI Required Write 94 72 11 ; ADI Required Write 94 F0 00 ; i2c_dphy_pwdn - 1'b0 94 31 82 ; ADI Required Write 94 1E 40 ; ADI Required Write 94 DA 01 ; i2c_mipi_pll_en - 1'b1 delay 2 ; 94 00 21 ; Power-up CSI-TX delay 1 ; 94 C1 2B ; ADI Required Write delay 1 ; 94 31 80 ; ADI Required Write End ; Supported Formats For Script Below - 720x480p60, 720(1440)x480i60, 720x576p50, 720(1440)x576i50, 640x480(VGA)@60, 800x480(WVGA)@60 :01-05 HDMI to MIPI TxA CSI 1-Lane - RGB565, Up to 600Mbps: E0 FF FF ; SW reset delay 5 ; E0 01 76 ; ADI Required Write E0 05 4A ; Setting Vid_Std to 720x480p60 E0 F2 01 ; Enable I2C Read Auto-Increment E0 F3 4C ; DPLL Map Address Set to 0x4C E0 F4 44 ; CP Map Address Set to 0x44 E0 F5 68 ; HDMI RX Map Address Set to 0x68 E0 F6 6C ; EDID Map Address Set to 0x6C E0 F7 64 ; HDMI RX Repeater Map Address Set to 0x64 E0 F8 62 ; HDMI RX Infoframe Map Address Set to 0x62 E0 F9 F0 ; CBUS Map Address Set to 0xF0 E0 FA 82 ; CEC Map Address Set to 0x82 E0 FB F2 ; SDP Main Map Address Set to 0xF2 E0 FC 90 ; CSI-TXB Map Address Set to 0x90 E0 FD 94 ; CSI-TXA Map Address Set to 0x94 E0 00 40 ; Disable chip powerdown & Enable HDMI Rx block 64 40 83 ; Enable HDCP 1.1 68 00 08 ; Foreground Channel = A 68 98 FF ; ADI Required Write 68 99 A3 ; ADI Required Write 68 9A 00 ; ADI Required Write 68 9B 0A ; ADI Required Write 68 9D 40 ; ADI Required Write 68 CB 09 ; ADI Required Write 68 3D 10 ; ADI Required Write 68 3E 7B ; ADI Required Write 68 3F 5E ; ADI Required Write 68 4E FE ; ADI Required Write 68 4F 18 ; ADI Required Write 68 57 A3 ; ADI Required Write 68 58 04 ; ADI Required Write 68 85 10 ; ADI Required Write 68 83 00 ; Enable All Terminations 68 A3 01 ; ADI Required Write 68 BE 00 ; ADI Required Write 68 6C 01 ; HPA Manual Enable 68 F8 01 ; HPA Asserted 68 0F 00 ; Audio Mute Speed Set to Fastest (Smallest Step Size) E0 04 02 ; RGB Out of CP E0 12 F0 ; CSC Depends on ip Packets - SDR 444 E0 17 B8 ; Configure for RGB565 & Luma & Chroma Values Can Reach 254d E0 03 86 ; CP-Insert_AV_Code 44 7C 00 ; ADI Required Write E0 0C E0 ; Enable LLC_DLL & Double LLC Timing E0 0E DD ; LLC/PIX/SPI PINS TRISTATED AUD Outputs Enabled E0 10 A0 ; Enable 4-lane CSI Tx & Pixel Port 94 00 81 ; Enable 1-lane MIPI 94 00 A1 ; Set Auto DPHY Timing 94 DB 10 ; ADI Required Write 94 7E 98 ; ADI Required Write 94 D6 07 ; ADI Required Write 94 C4 0A ; ADI Required Write 94 71 33 ; ADI Required Write 94 72 11 ; ADI Required Write 94 F0 00 ; i2c_dphy_pwdn - 1'b0 94 31 82 ; ADI Required Write 94 1E 40 ; ADI Required Write 94 DA 01 ; i2c_mipi_pll_en - 1'b1 delay 2 ; 94 00 21 ; Power-up CSI-TX delay 1 ; 94 C1 2B ; ADI Required Write delay 1 ; 94 31 80 ; ADI Required Write End ; Supported Formats For Script Below - 800x600(SVGA)@60 :01-06 HDMI to MIPI TxA CSI 1-Lane - RGB565, Over 600Mbps: E0 FF FF ; SW reset delay 5 ; E0 01 76 ; ADI Required Write E0 05 81 ; Setting Vid_Std to 800x600(SVGA)@60 E0 F2 01 ; Enable I2C Read Auto-Increment E0 F3 4C ; DPLL Map Address Set to 0x4C E0 F4 44 ; CP Map Address Set to 0x44 E0 F5 68 ; HDMI RX Map Address Set to 0x68 E0 F6 6C ; EDID Map Address Set to 0x6C E0 F7 64 ; HDMI RX Repeater Map Address Set to 0x64 E0 F8 62 ; HDMI RX Infoframe Map Address Set to 0x62 E0 F9 F0 ; CBUS Map Address Set to 0xF0 E0 FA 82 ; CEC Map Address Set to 0x82 E0 FB F2 ; SDP Main Map Address Set to 0xF2 E0 FC 90 ; CSI-TXB Map Address Set to 0x90 E0 FD 94 ; CSI-TXA Map Address Set to 0x94 E0 00 40 ; Disable chip powerdown & Enable HDMI Rx block 64 40 83 ; Enable HDCP 1.1 68 00 08 ; Foreground Channel = A 68 98 FF ; ADI Required Write 68 99 A3 ; ADI Required Write 68 9A 00 ; ADI Required Write 68 9B 0A ; ADI Required Write 68 9D 40 ; ADI Required Write 68 CB 09 ; ADI Required Write 68 3D 10 ; ADI Required Write 68 3E 7B ; ADI Required Write 68 3F 5E ; ADI Required Write 68 4E FE ; ADI Required Write 68 4F 18 ; ADI Required Write 68 57 A3 ; ADI Required Write 68 58 04 ; ADI Required Write 68 85 10 ; ADI Required Write 68 83 00 ; Enable All Terminations 68 A3 01 ; ADI Required Write 68 BE 00 ; ADI Required Write 68 6C 01 ; HPA Manual Enable 68 F8 01 ; HPA Asserted 68 0F 00 ; Audio Mute Speed Set to Fastest (Smallest Step Size) E0 04 02 ; RGB Out of CP E0 12 F0 ; CSC Depends on ip Packets - SDR 444 E0 17 B8 ; Configure for RGB565 & Luma & Chroma Values Can Reach 254d E0 03 86 ; CP-Insert_AV_Code 44 7C 00 ; ADI Required Write E0 0C E0 ; Enable LLC_DLL & Double LLC Timing E0 0E DD ; LLC/PIX/SPI PINS TRISTATED AUD Outputs Enabled E0 10 A0 ; Enable 4-lane CSI Tx & Pixel Port 94 00 81 ; Enable 1-lane MIPI 94 00 A1 ; Set Auto DPHY Timing 94 7E 98 ; ADI Required Write 94 DB 13 ; ADI Required Write 94 D6 07 ; ADI Required Write 94 C4 0A ; ADI Required Write 94 71 33 ; ADI Required Write 94 72 11 ; ADI Required Write 94 F0 00 ; i2c_dphy_pwdn - 1'b0 94 31 82 ; ADI Required Write 94 1E 40 ; ADI Required Write 94 DA 01 ; i2c_mipi_pll_en - 1'b1 delay 2 ; 94 00 21 ; Power-up CSI-TX delay 1 ; 94 C1 2B ; ADI Required Write delay 1 ; 94 31 80 ; ADI Required Write End ; Supported Formats For Script Below - 720x480p60, 720(1440)x480i60, 720x576p50, 720(1440)x576i50, 640x480(VGA)@60, 800x480(WVGA)@60 :01-07 HDMI to MIPI TxA CSI 1-Lane - RGB666, Up to 600Mbps: E0 FF FF ; SW reset delay 5 ; E0 01 76 ; ADI Required Write E0 05 4A ; Setting Vid_Std to 720x480p60 E0 F2 01 ; Enable I2C Read Auto-Increment E0 F3 4C ; DPLL Map Address Set to 0x4C E0 F4 44 ; CP Map Address Set to 0x44 E0 F5 68 ; HDMI RX Map Address Set to 0x68 E0 F6 6C ; EDID Map Address Set to 0x6C E0 F7 64 ; HDMI RX Repeater Map Address Set to 0x64 E0 F8 62 ; HDMI RX Infoframe Map Address Set to 0x62 E0 F9 F0 ; CBUS Map Address Set to 0xF0 E0 FA 82 ; CEC Map Address Set to 0x82 E0 FB F2 ; SDP Main Map Address Set to 0xF2 E0 FC 90 ; CSI-TXB Map Address Set to 0x90 E0 FD 94 ; CSI-TXA Map Address Set to 0x94 E0 00 40 ; Disable chip powerdown & Enable HDMI Rx block 64 40 83 ; Enable HDCP 1.1 68 00 08 ; Foreground Channel = A 68 98 FF ; ADI Required Write 68 99 A3 ; ADI Required Write 68 9A 00 ; ADI Required Write 68 9B 0A ; ADI Required Write 68 9D 40 ; ADI Required Write 68 CB 09 ; ADI Required Write 68 3D 10 ; ADI Required Write 68 3E 7B ; ADI Required Write 68 3F 5E ; ADI Required Write 68 4E FE ; ADI Required Write 68 4F 18 ; ADI Required Write 68 57 A3 ; ADI Required Write 68 58 04 ; ADI Required Write 68 85 10 ; ADI Required Write 68 83 00 ; Enable All Terminations 68 A3 01 ; ADI Required Write 68 BE 00 ; ADI Required Write 68 6C 01 ; HPA Manual Enable 68 F8 01 ; HPA Asserted 68 0F 00 ; Audio Mute Speed Set to Fastest (Smallest Step Size) E0 04 02 ; RGB Out of CP E0 12 F0 ; CSC Depends on ip Packets - SDR 444 E0 17 B8 ; Configure for RGB666 & Luma & Chroma Values Can Reach 254d E0 03 86 ; CP-Insert_AV_Code 44 7C 00 ; ADI Required Write E0 0C E0 ; Enable LLC_DLL & Double LLC Timing E0 0E DD ; LLC/PIX/SPI PINS TRISTATED AUD Outputs Enabled E0 10 A0 ; Enable 4-lane CSI Tx & Pixel Port 94 00 81 ; Enable 1-lane MIPI 94 00 A1 ; Set Auto DPHY Timing 94 DB 10 ; ADI Required Write 94 D6 07 ; ADI Required Write 94 C4 0A ; ADI Required Write 94 71 33 ; ADI Required Write 94 72 11 ; ADI Required Write 94 F0 00 ; i2c_dphy_pwdn - 1'b0 94 31 82 ; ADI Required Write 94 1E 40 ; ADI Required Write 94 DA 01 ; i2c_mipi_pll_en - 1'b1 delay 2 ; 94 00 21 ; Power-up CSI-TX delay 1 ; 94 C1 2B ; ADI Required Write delay 1 ; 94 31 80 ; ADI Required Write End ; Supported Formats For Script Below - 800x600(SVGA)@60 :01-08 HDMI to MIPI TxA CSI 1-Lane - RGB666, Over 600Mbps: E0 FF FF ; SW reset delay 5 ; E0 01 76 ; ADI Required Write E0 05 81 ; Setting Vid_Std to 800x600(SVGA)@60 E0 F2 01 ; Enable I2C Read Auto-Increment E0 F3 4C ; DPLL Map Address Set to 0x4C E0 F4 44 ; CP Map Address Set to 0x44 E0 F5 68 ; HDMI RX Map Address Set to 0x68 E0 F6 6C ; EDID Map Address Set to 0x6C E0 F7 64 ; HDMI RX Repeater Map Address Set to 0x64 E0 F8 62 ; HDMI RX Infoframe Map Address Set to 0x62 E0 F9 F0 ; CBUS Map Address Set to 0xF0 E0 FA 82 ; CEC Map Address Set to 0x82 E0 FB F2 ; SDP Main Map Address Set to 0xF2 E0 FC 90 ; CSI-TXB Map Address Set to 0x90 E0 FD 94 ; CSI-TXA Map Address Set to 0x94 E0 00 40 ; Disable chip powerdown & Enable HDMI Rx block 64 40 83 ; Enable HDCP 1.1 68 00 08 ; Foreground Channel = A 68 98 FF ; ADI Required Write 68 99 A3 ; ADI Required Write 68 9A 00 ; ADI Required Write 68 9B 0A ; ADI Required Write 68 9D 40 ; ADI Required Write 68 CB 09 ; ADI Required Write 68 3D 10 ; ADI Required Write 68 3E 7B ; ADI Required Write 68 3F 5E ; ADI Required Write 68 4E FE ; ADI Required Write 68 4F 18 ; ADI Required Write 68 57 A3 ; ADI Required Write 68 58 04 ; ADI Required Write 68 85 10 ; ADI Required Write 68 83 00 ; Enable All Terminations 68 A3 01 ; ADI Required Write 68 BE 00 ; ADI Required Write 68 6C 01 ; HPA Manual Enable 68 F8 01 ; HPA Asserted 68 0F 00 ; Audio Mute Speed Set to Fastest (Smallest Step Size) E0 04 02 ; RGB Out of CP E0 12 F0 ; CSC Depends on ip Packets - SDR 444 E0 17 B8 ; Configure for RGB666 & Luma & Chroma Values Can Reach 254d E0 03 86 ; CP-Insert_AV_Code 44 7C 00 ; ADI Required Write E0 0C E0 ; Enable LLC_DLL & Double LLC Timing E0 0E DD ; LLC/PIX/SPI PINS TRISTATED AUD Outputs Enabled E0 10 A0 ; Enable 4-lane CSI Tx & Pixel Port 94 00 81 ; Enable 1-lane MIPI 94 00 A1 ; Set Auto DPHY Timing 94 DB 13 ; ADI Required Write 94 D6 07 ; ADI Required Write 94 C4 0A ; ADI Required Write 94 71 33 ; ADI Required Write 94 72 11 ; ADI Required Write 94 F0 00 ; i2c_dphy_pwdn - 1'b0 94 31 82 ; ADI Required Write 94 1E 40 ; ADI Required Write 94 DA 01 ; i2c_mipi_pll_en - 1'b1 delay 2 ; 94 00 21 ; Power-up CSI-TX delay 1 ; 94 C1 2B ; ADI Required Write delay 1 ; 94 31 80 ; ADI Required Write End ; Supported Formats For Script Below - 720(1440)x480i60, 720(1440)x576i50 :01-09 HDMI to MIPI TxA CSI 1-Lane - RGB888, Up to 600Mbps: E0 FF FF ; SW reset delay 5 ; E0 01 76 ; ADI Required Write E0 05 40 ; Setting Vid_Std to 720(1440)x480i60 E0 F2 01 ; Enable I2C Read Auto-Increment E0 F3 4C ; DPLL Map Address Set to 0x4C E0 F4 44 ; CP Map Address Set to 0x44 E0 F5 68 ; HDMI RX Map Address Set to 0x68 E0 F6 6C ; EDID Map Address Set to 0x6C E0 F7 64 ; HDMI RX Repeater Map Address Set to 0x64 E0 F8 62 ; HDMI RX Infoframe Map Address Set to 0x62 E0 F9 F0 ; CBUS Map Address Set to 0xF0 E0 FA 82 ; CEC Map Address Set to 0x82 E0 FB F2 ; SDP Main Map Address Set to 0xF2 E0 FC 90 ; CSI-TXB Map Address Set to 0x90 E0 FD 94 ; CSI-TXA Map Address Set to 0x94 E0 00 40 ; Disable chip powerdown & Enable HDMI Rx block 64 40 83 ; Enable HDCP 1.1 68 00 08 ; Foreground Channel = A 68 98 FF ; ADI Required Write 68 99 A3 ; ADI Required Write 68 9A 00 ; ADI Required Write 68 9B 0A ; ADI Required Write 68 9D 40 ; ADI Required Write 68 CB 09 ; ADI Required Write 68 3D 10 ; ADI Required Write 68 3E 7B ; ADI Required Write 68 3F 5E ; ADI Required Write 68 4E FE ; ADI Required Write 68 4F 18 ; ADI Required Write 68 57 A3 ; ADI Required Write 68 58 04 ; ADI Required Write 68 85 10 ; ADI Required Write 68 83 00 ; Enable All Terminations 68 A3 01 ; ADI Required Write 68 BE 00 ; ADI Required Write 68 6C 01 ; HPA Manual Enable 68 F8 01 ; HPA Asserted 68 0F 00 ; Audio Mute Speed Set to Fastest (Smallest Step Size) E0 04 02 ; RGB Out of CP E0 12 F0 ; CSC Depends on ip Packets - SDR 444 E0 17 80 ; Luma & Chroma Values Can Reach 254d E0 03 86 ; CP-Insert_AV_Code 44 7C 00 ; ADI Required Write E0 0C E0 ; Enable LLC_DLL & Double LLC Timing E0 0E DD ; LLC/PIX/SPI PINS TRISTATED AUD Outputs Enabled E0 10 A0 ; Enable 4-lane CSI Tx & Pixel Port 94 00 81 ; Enable 1-lane MIPI 94 00 A1 ; Set Auto DPHY Timing 94 DB 10 ; ADI Required Write 94 D6 07 ; ADI Required Write 94 C4 0A ; ADI Required Write 94 71 33 ; ADI Required Write 94 72 11 ; ADI Required Write 94 F0 00 ; i2c_dphy_pwdn - 1'b0 94 31 82 ; ADI Required Write 94 1E 40 ; ADI Required Write 94 DA 01 ; i2c_mipi_pll_en - 1'b1 delay 2 ; 94 00 21 ; Power-up CSI-TX delay 1 ; 94 C1 2B ; ADI Required Write delay 1 ; 94 31 80 ; ADI Required Write End ; Supported Formats For Script Below - 720x480p60, 720x576p50, 800x600(SVGA)@60, 640x480(VGA)@60, 800x480(WVGA)@60 :01-10 HDMI to MIPI TxA CSI 1-Lane - RGB888, Over 600Mbps: E0 FF FF ; SW reset delay 5 ; E0 01 76 ; ADI Required Write E0 05 4A ; Setting Vid_Std to 720x480p60 E0 F2 01 ; Enable I2C Read Auto-Increment E0 F3 4C ; DPLL Map Address Set to 0x4C E0 F4 44 ; CP Map Address Set to 0x44 E0 F5 68 ; HDMI RX Map Address Set to 0x68 E0 F6 6C ; EDID Map Address Set to 0x6C E0 F7 64 ; HDMI RX Repeater Map Address Set to 0x64 E0 F8 62 ; HDMI RX Infoframe Map Address Set to 0x62 E0 F9 F0 ; CBUS Map Address Set to 0xF0 E0 FA 82 ; CEC Map Address Set to 0x82 E0 FB F2 ; SDP Main Map Address Set to 0xF2 E0 FC 90 ; CSI-TXB Map Address Set to 0x90 E0 FD 94 ; CSI-TXA Map Address Set to 0x94 E0 00 40 ; Disable chip powerdown & Enable HDMI Rx block 64 40 83 ; Enable HDCP 1.1 68 00 08 ; Foreground Channel = A 68 98 FF ; ADI Required Write 68 99 A3 ; ADI Required Write 68 9A 00 ; ADI Required Write 68 9B 0A ; ADI Required Write 68 9D 40 ; ADI Required Write 68 CB 09 ; ADI Required Write 68 3D 10 ; ADI Required Write 68 3E 7B ; ADI Required Write 68 3F 5E ; ADI Required Write 68 4E FE ; ADI Required Write 68 4F 18 ; ADI Required Write 68 57 A3 ; ADI Required Write 68 58 04 ; ADI Required Write 68 85 10 ; ADI Required Write 68 83 00 ; Enable All Terminations 68 A3 01 ; ADI Required Write 68 BE 00 ; ADI Required Write 68 6C 01 ; HPA Manual Enable 68 F8 01 ; HPA Asserted 68 0F 00 ; Audio Mute Speed Set to Fastest (Smallest Step Size) E0 04 02 ; RGB Out of CP E0 12 F0 ; CSC Depends on ip Packets - SDR 444 E0 17 80 ; Luma & Chroma Values Can Reach 254d E0 03 86 ; CP-Insert_AV_Code 44 7C 00 ; ADI Required Write E0 0C E0 ; Enable LLC_DLL & Double LLC Timing E0 0E DD ; LLC/PIX/SPI PINS TRISTATED AUD Outputs Enabled E0 10 A0 ; Enable 4-lane CSI Tx & Pixel Port 94 00 81 ; Enable 1-lane MIPI 94 00 A1 ; Set Auto DPHY Timing 94 DB 13 ; ADI Required Write 94 D6 07 ; ADI Required Write 94 C4 0A ; ADI Required Write 94 71 33 ; ADI Required Write 94 72 11 ; ADI Required Write 94 F0 00 ; i2c_dphy_pwdn - 1'b0 94 31 82 ; ADI Required Write 94 1E 40 ; ADI Required Write 94 DA 01 ; i2c_mipi_pll_en - 1'b1 delay 2 ; 94 00 21 ; Power-up CSI-TX delay 1 ; 94 C1 2B ; ADI Required Write delay 1 ; 94 31 80 ; ADI Required Write End ; Supported Formats For Script Below - 720x480p60, 1280x720p60, 1920x1080i60, 720x576p50, 1280x720p50, 1920x1080i50, 800x600(SVGA)@60, 640x480(VGA)@60, 800x480(WVGA)@60, 1024x768(XGA)@60 :01-11 HDMI to MIPI TxA CSI 2-Lane - YUV422 8-Bit, Up to 600Mbps: E0 FF FF ; SW reset delay 5 ; E0 01 76 ; ADI Required Write E0 05 4A ; Setting Vid_Std to 720x480p60 E0 F2 01 ; Enable I2C Read Auto-Increment E0 F3 4C ; DPLL Map Address Set to 0x4C E0 F4 44 ; CP Map Address Set to 0x44 E0 F5 68 ; HDMI RX Map Address Set to 0x68 E0 F6 6C ; EDID Map Address Set to 0x6C E0 F7 64 ; HDMI RX Repeater Map Address Set to 0x64 E0 F8 62 ; HDMI RX Infoframe Map Address Set to 0x62 E0 F9 F0 ; CBUS Map Address Set to 0xF0 E0 FA 82 ; CEC Map Address Set to 0x82 E0 FB F2 ; SDP Main Map Address Set to 0xF2 E0 FC 90 ; CSI-TXB Map Address Set to 0x90 E0 FD 94 ; CSI-TXA Map Address Set to 0x94 E0 00 40 ; Disable chip powerdown & Enable HDMI Rx block 64 40 83 ; Enable HDCP 1.1 68 00 08 ; Foreground Channel = A 68 98 FF ; ADI Required Write 68 99 A3 ; ADI Required Write 68 9A 00 ; ADI Required Write 68 9B 0A ; ADI Required Write 68 9D 40 ; ADI Required Write 68 CB 09 ; ADI Required Write 68 3D 10 ; ADI Required Write 68 3E 7B ; ADI Required Write 68 3F 5E ; ADI Required Write 68 4E FE ; ADI Required Write 68 4F 18 ; ADI Required Write 68 57 A3 ; ADI Required Write 68 58 04 ; ADI Required Write 68 85 10 ; ADI Required Write 68 83 00 ; Enable All Terminations 68 A3 01 ; ADI Required Write 68 BE 00 ; ADI Required Write 68 6C 01 ; HPA Manual Enable 68 F8 01 ; HPA Asserted 68 0F 00 ; Audio Mute Speed Set to Fastest (Smallest Step Size) E0 04 00 ; YCrCb output E0 12 F2 ; CSC Depends on ip Packets - SDR422 set E0 17 80 ; Luma & Chroma Values Can Reach 254d E0 03 86 ; CP-Insert_AV_Code 44 7C 00 ; ADI Required Write E0 0C E0 ; Enable LLC_DLL & Double LLC Timing E0 0E DD ; LLC/PIX/SPI PINS TRISTATED AUD Outputs Enabled E0 10 A0 ; Enable 4-lane CSI Tx & Pixel Port 94 00 82 ; Enable 2-lane MIPI 94 00 A2 ; Set Auto DPHY Timing 94 DB 10 ; ADI Required Write 94 D6 07 ; ADI Required Write 94 C4 0A ; ADI Required Write 94 71 33 ; ADI Required Write 94 72 11 ; ADI Required Write 94 F0 00 ; i2c_dphy_pwdn - 1'b0 94 31 82 ; ADI Required Write 94 1E 40 ; ADI Required Write 94 DA 01 ; i2c_mipi_pll_en - 1'b1 delay 2 ; 94 00 22 ; Power-up CSI-TX delay 1 ; 94 C1 2B ; ADI Required Write delay 1 ; 94 31 80 ; ADI Required Write End ; Supported Formats For Script Below - 1280x1024(SXGA)@60 :01-12 HDMI to MIPI TxA CSI 2-Lane - YUV422 8-Bit, Over 600Mbps: E0 FF FF ; SW reset delay 5 ; E0 01 76 ; ADI Required Write E0 05 85 ; Setting Vid_Std to 1280x1024(SXGA)@60 E0 F2 01 ; Enable I2C Read Auto-Increment E0 F3 4C ; DPLL Map Address Set to 0x4C E0 F4 44 ; CP Map Address Set to 0x44 E0 F5 68 ; HDMI RX Map Address Set to 0x68 E0 F6 6C ; EDID Map Address Set to 0x6C E0 F7 64 ; HDMI RX Repeater Map Address Set to 0x64 E0 F8 62 ; HDMI RX Infoframe Map Address Set to 0x62 E0 F9 F0 ; CBUS Map Address Set to 0xF0 E0 FA 82 ; CEC Map Address Set to 0x82 E0 FB F2 ; SDP Main Map Address Set to 0xF2 E0 FC 90 ; CSI-TXB Map Address Set to 0x90 E0 FD 94 ; CSI-TXA Map Address Set to 0x94 E0 00 40 ; Disable chip powerdown & Enable HDMI Rx block 64 40 83 ; Enable HDCP 1.1 68 00 08 ; Foreground Channel = A 68 98 FF ; ADI Required Write 68 99 A3 ; ADI Required Write 68 9A 00 ; ADI Required Write 68 9B 0A ; ADI Required Write 68 9D 40 ; ADI Required Write 68 CB 09 ; ADI Required Write 68 3D 10 ; ADI Required Write 68 3E 7B ; ADI Required Write 68 3F 5E ; ADI Required Write 68 4E FE ; ADI Required Write 68 4F 18 ; ADI Required Write 68 57 A3 ; ADI Required Write 68 58 04 ; ADI Required Write 68 85 10 ; ADI Required Write 68 83 00 ; Enable All Terminations 68 A3 01 ; ADI Required Write 68 BE 00 ; ADI Required Write 68 6C 01 ; HPA Manual Enable 68 F8 01 ; HPA Asserted 68 0F 00 ; Audio Mute Speed Set to Fastest (Smallest Step Size) E0 04 00 ; YCrCb output E0 12 F2 ; CSC Depends on ip Packets - SDR422 set E0 17 80 ; Luma & Chroma Values Can Reach 254d E0 03 86 ; CP-Insert_AV_Code 44 7C 00 ; ADI Required Write E0 0C E0 ; Enable LLC_DLL & Double LLC Timing E0 0E DD ; LLC/PIX/SPI PINS TRISTATED AUD Outputs Enabled E0 10 A0 ; Enable 4-lane CSI Tx & Pixel Port 94 00 82 ; Enable 2-lane MIPI 94 00 A2 ; Set Auto DPHY Timing 94 DB 13 ; ADI Required Write 94 D6 07 ; ADI Required Write 94 C4 0A ; ADI Required Write 94 71 33 ; ADI Required Write 94 72 11 ; ADI Required Write 94 F0 00 ; i2c_dphy_pwdn - 1'b0 94 31 82 ; ADI Required Write 94 1E 40 ; ADI Required Write 94 DA 01 ; i2c_mipi_pll_en - 1'b1 delay 2 ; 94 00 22 ; Power-up CSI-TX delay 1 ; 94 C1 2B ; ADI Required Write delay 1 ; 94 31 80 ; ADI Required Write End ; Supported Formats For Script Below - 720x480p60, 720(1440)x480i60, 720x576p50, 720(1440)x576i50, 800x600(SVGA)@60, 640x480(VGA)@60, 800x480(WVGA)@60 :01-13 HDMI to MIPI TxA CSI 2-Lane - YUV422 10-Bit, Up to 600Mbps: E0 FF FF ; SW reset delay 5 ; E0 01 76 ; ADI Required Write E0 05 4A ; Setting Vid_Std to 720x480p60 E0 F2 01 ; Enable I2C Read Auto-Increment E0 F3 4C ; DPLL Map Address Set to 0x4C E0 F4 44 ; CP Map Address Set to 0x44 E0 F5 68 ; HDMI RX Map Address Set to 0x68 E0 F6 6C ; EDID Map Address Set to 0x6C E0 F7 64 ; HDMI RX Repeater Map Address Set to 0x64 E0 F8 62 ; HDMI RX Infoframe Map Address Set to 0x62 E0 F9 F0 ; CBUS Map Address Set to 0xF0 E0 FA 82 ; CEC Map Address Set to 0x82 E0 FB F2 ; SDP Main Map Address Set to 0xF2 E0 FC 90 ; CSI-TXB Map Address Set to 0x90 E0 FD 94 ; CSI-TXA Map Address Set to 0x94 E0 00 40 ; Disable chip powerdown & Enable HDMI Rx block 64 40 83 ; Enable HDCP 1.1 68 00 08 ; Foreground Channel = A 68 98 FF ; ADI Required Write 68 99 A3 ; ADI Required Write 68 9A 00 ; ADI Required Write 68 9B 0A ; ADI Required Write 68 9D 40 ; ADI Required Write 68 CB 09 ; ADI Required Write 68 3D 10 ; ADI Required Write 68 3E 7B ; ADI Required Write 68 3F 5E ; ADI Required Write 68 4E FE ; ADI Required Write 68 4F 18 ; ADI Required Write 68 57 A3 ; ADI Required Write 68 58 04 ; ADI Required Write 68 85 10 ; ADI Required Write 68 83 00 ; Enable All Terminations 68 A3 01 ; ADI Required Write 68 BE 00 ; ADI Required Write 68 6C 01 ; HPA Manual Enable 68 F8 01 ; HPA Asserted 68 0F 00 ; Audio Mute Speed Set to Fastest (Smallest Step Size) E0 04 00 ; YCrCb output E0 12 F3 ; CSC Depends on ip Packets - SDR422 set - 10Bit E0 17 80 ; Luma & Chroma Values Can Reach 254d E0 03 86 ; CP-Insert_AV_Code 44 7C 00 ; ADI Required Write E0 0C E0 ; Enable LLC_DLL & Double LLC Timing E0 0E DD ; LLC/PIX/SPI PINS TRISTATED AUD Outputs Enabled E0 10 A0 ; Enable 4-lane CSI Tx & Pixel Port 94 00 82 ; Enable 2-lane MIPI 94 00 A2 ; Set Auto DPHY Timing 94 DB 10 ; ADI Required Write 94 D6 07 ; ADI Required Write 94 C4 0A ; ADI Required Write 94 71 33 ; ADI Required Write 94 72 11 ; ADI Required Write 94 F0 00 ; i2c_dphy_pwdn - 1'b0 94 31 82 ; ADI Required Write 94 1E 40 ; ADI Required Write 94 DA 01 ; i2c_mipi_pll_en - 1'b1 delay 2 ; 94 00 22 ; Power-up CSI-TX delay 1 ; 94 C1 2B ; ADI Required Write delay 1 ; 94 31 80 ; ADI Required Write End ; Supported Formats For Script Below - 1280x720p60, 1920x1080i60, 1280x720p50, 1920x1080i50, 1024x768(XGA)@60 :01-14 HDMI to MIPI TxA CSI 2-Lane - YUV422 10-Bit, Over 600Mbps: E0 FF FF ; SW reset delay 5 ; E0 01 76 ; ADI Required Write E0 05 8C ; Setting Vid_Std to 1024x768(XGA)@60 E0 F2 01 ; Enable I2C Read Auto-Increment E0 F3 4C ; DPLL Map Address Set to 0x4C E0 F4 44 ; CP Map Address Set to 0x44 E0 F5 68 ; HDMI RX Map Address Set to 0x68 E0 F6 6C ; EDID Map Address Set to 0x6C E0 F7 64 ; HDMI RX Repeater Map Address Set to 0x64 E0 F8 62 ; HDMI RX Infoframe Map Address Set to 0x62 E0 F9 F0 ; CBUS Map Address Set to 0xF0 E0 FA 82 ; CEC Map Address Set to 0x82 E0 FB F2 ; SDP Main Map Address Set to 0xF2 E0 FC 90 ; CSI-TXB Map Address Set to 0x90 E0 FD 94 ; CSI-TXA Map Address Set to 0x94 E0 00 40 ; Disable chip powerdown & Enable HDMI Rx block 64 40 83 ; Enable HDCP 1.1 68 00 08 ; Foreground Channel = A 68 98 FF ; ADI Required Write 68 99 A3 ; ADI Required Write 68 9A 00 ; ADI Required Write 68 9B 0A ; ADI Required Write 68 9D 40 ; ADI Required Write 68 CB 09 ; ADI Required Write 68 3D 10 ; ADI Required Write 68 3E 7B ; ADI Required Write 68 3F 5E ; ADI Required Write 68 4E FE ; ADI Required Write 68 4F 18 ; ADI Required Write 68 57 A3 ; ADI Required Write 68 58 04 ; ADI Required Write 68 85 10 ; ADI Required Write 68 83 00 ; Enable All Terminations 68 A3 01 ; ADI Required Write 68 BE 00 ; ADI Required Write 68 6C 01 ; HPA Manual Enable 68 F8 01 ; HPA Asserted 68 0F 00 ; Audio Mute Speed Set to Fastest (Smallest Step Size) E0 04 00 ; YCrCb output E0 12 F3 ; CSC Depends on ip Packets - SDR422 set - 10Bit E0 17 80 ; Luma & Chroma Values Can Reach 254d E0 03 86 ; CP-Insert_AV_Code 44 7C 00 ; ADI Required Write E0 0C E0 ; Enable LLC_DLL & Double LLC Timing E0 0E DD ; LLC/PIX/SPI PINS TRISTATED AUD Outputs Enabled E0 10 A0 ; Enable 4-lane CSI Tx & Pixel Port 94 00 82 ; Enable 2-lane MIPI 94 00 A2 ; Set Auto DPHY Timing 94 DB 13 ; ADI Required Write 94 D6 07 ; ADI Required Write 94 C4 0A ; ADI Required Write 94 71 33 ; ADI Required Write 94 72 11 ; ADI Required Write 94 F0 00 ; i2c_dphy_pwdn - 1'b0 94 31 82 ; ADI Required Write 94 1E 40 ; ADI Required Write 94 DA 01 ; i2c_mipi_pll_en - 1'b1 delay 2 ; 94 00 22 ; Power-up CSI-TX delay 1 ; 94 C1 2B ; ADI Required Write delay 1 ; 94 31 80 ; ADI Required Write End ; Supported Formats For Script Below - 720x480p60, 1280x720p60, 1920x1080i60, 720x576p50, 1280x720p50, 1920x1080i50, 800x600(SVGA)@60, 640x480(VGA)@60, 800x480(WVGA)@60, 1024x768(XGA)@60 :01-15 HDMI to MIPI TxA CSI 2-Lane - RGB565, Up to 600Mbps: E0 FF FF ; SW reset delay 5 ; E0 01 76 ; ADI Required Write E0 05 4A ; Setting Vid_Std to 720x480p60 E0 F2 01 ; Enable I2C Read Auto-Increment E0 F3 4C ; DPLL Map Address Set to 0x4C E0 F4 44 ; CP Map Address Set to 0x44 E0 F5 68 ; HDMI RX Map Address Set to 0x68 E0 F6 6C ; EDID Map Address Set to 0x6C E0 F7 64 ; HDMI RX Repeater Map Address Set to 0x64 E0 F8 62 ; HDMI RX Infoframe Map Address Set to 0x62 E0 F9 F0 ; CBUS Map Address Set to 0xF0 E0 FA 82 ; CEC Map Address Set to 0x82 E0 FB F2 ; SDP Main Map Address Set to 0xF2 E0 FC 90 ; CSI-TXB Map Address Set to 0x90 E0 FD 94 ; CSI-TXA Map Address Set to 0x94 E0 00 40 ; Disable chip powerdown & Enable HDMI Rx block 64 40 83 ; Enable HDCP 1.1 68 00 08 ; Foreground Channel = A 68 98 FF ; ADI Required Write 68 99 A3 ; ADI Required Write 68 9A 00 ; ADI Required Write 68 9B 0A ; ADI Required Write 68 9D 40 ; ADI Required Write 68 CB 09 ; ADI Required Write 68 3D 10 ; ADI Required Write 68 3E 7B ; ADI Required Write 68 3F 5E ; ADI Required Write 68 4E FE ; ADI Required Write 68 4F 18 ; ADI Required Write 68 57 A3 ; ADI Required Write 68 58 04 ; ADI Required Write 68 85 10 ; ADI Required Write 68 83 00 ; Enable All Terminations 68 A3 01 ; ADI Required Write 68 BE 00 ; ADI Required Write 68 6C 01 ; HPA Manual Enable 68 F8 01 ; HPA Asserted 68 0F 00 ; Audio Mute Speed Set to Fastest (Smallest Step Size) E0 04 02 ; RGB Out of CP E0 12 F0 ; CSC Depends on ip Packets - SDR 444 E0 17 B8 ; Configure for RGB565 & Luma & Chroma Values Can Reach 254d E0 03 86 ; CP-Insert_AV_Code 44 7C 00 ; ADI Required Write E0 0C E0 ; Enable LLC_DLL & Double LLC Timing E0 0E DD ; LLC/PIX/SPI PINS TRISTATED AUD Outputs Enabled E0 10 A0 ; Enable 4-lane CSI Tx & Pixel Port 94 00 82 ; Enable 2-lane MIPI 94 00 A2 ; Set Auto DPHY Timing 94 DB 10 ; ADI Required Write 94 7E 98 ; ADI Required Write 94 D6 07 ; ADI Required Write 94 C4 0A ; ADI Required Write 94 71 33 ; ADI Required Write 94 72 11 ; ADI Required Write 94 F0 00 ; i2c_dphy_pwdn - 1'b0 94 31 82 ; ADI Required Write 94 1E 40 ; ADI Required Write 94 DA 01 ; i2c_mipi_pll_en - 1'b1 delay 2 ; 94 00 22 ; Power-up CSI-TX delay 1 ; 94 C1 2B ; ADI Required Write delay 1 ; 94 31 80 ; ADI Required Write End ; Supported Formats For Script Below - 1280x1024(SXGA)@60 :01-16 HDMI to MIPI TxA CSI 2-Lane - RGB565, Over 600Mbps: E0 FF FF ; SW reset delay 5 ; E0 01 76 ; ADI Required Write E0 05 85 ; Setting Vid_Std to 1280x1024(SXGA)@60 E0 F2 01 ; Enable I2C Read Auto-Increment E0 F3 4C ; DPLL Map Address Set to 0x4C E0 F4 44 ; CP Map Address Set to 0x44 E0 F5 68 ; HDMI RX Map Address Set to 0x68 E0 F6 6C ; EDID Map Address Set to 0x6C E0 F7 64 ; HDMI RX Repeater Map Address Set to 0x64 E0 F8 62 ; HDMI RX Infoframe Map Address Set to 0x62 E0 F9 F0 ; CBUS Map Address Set to 0xF0 E0 FA 82 ; CEC Map Address Set to 0x82 E0 FB F2 ; SDP Main Map Address Set to 0xF2 E0 FC 90 ; CSI-TXB Map Address Set to 0x90 E0 FD 94 ; CSI-TXA Map Address Set to 0x94 E0 00 40 ; Disable chip powerdown & Enable HDMI Rx block 64 40 83 ; Enable HDCP 1.1 68 00 08 ; Foreground Channel = A 68 98 FF ; ADI Required Write 68 99 A3 ; ADI Required Write 68 9A 00 ; ADI Required Write 68 9B 0A ; ADI Required Write 68 9D 40 ; ADI Required Write 68 CB 09 ; ADI Required Write 68 3D 10 ; ADI Required Write 68 3E 7B ; ADI Required Write 68 3F 5E ; ADI Required Write 68 4E FE ; ADI Required Write 68 4F 18 ; ADI Required Write 68 57 A3 ; ADI Required Write 68 58 04 ; ADI Required Write 68 85 10 ; ADI Required Write 68 83 00 ; Enable All Terminations 68 A3 01 ; ADI Required Write 68 BE 00 ; ADI Required Write 68 6C 01 ; HPA Manual Enable 68 F8 01 ; HPA Asserted 68 0F 00 ; Audio Mute Speed Set to Fastest (Smallest Step Size) E0 04 02 ; RGB Out of CP E0 12 F0 ; CSC Depends on ip Packets - SDR 444 E0 17 B8 ; Configure for RGB565 & Luma & Chroma Values Can Reach 254d E0 03 86 ; CP-Insert_AV_Code 44 7C 00 ; ADI Required Write E0 0C E0 ; Enable LLC_DLL & Double LLC Timing E0 0E DD ; LLC/PIX/SPI PINS TRISTATED AUD Outputs Enabled E0 10 A0 ; Enable 4-lane CSI Tx & Pixel Port 94 00 82 ; Enable 2-lane MIPI 94 00 A2 ; Set Auto DPHY Timing 94 7E 98 ; ADI Required Write 94 DB 13 ; ADI Required Write 94 D6 07 ; ADI Required Write 94 C4 0A ; ADI Required Write 94 71 33 ; ADI Required Write 94 72 11 ; ADI Required Write 94 F0 00 ; i2c_dphy_pwdn - 1'b0 94 31 82 ; ADI Required Write 94 1E 40 ; ADI Required Write 94 DA 01 ; i2c_mipi_pll_en - 1'b1 delay 2 ; 94 00 22 ; Power-up CSI-TX delay 1 ; 94 C1 2B ; ADI Required Write delay 1 ; 94 31 80 ; ADI Required Write End ; Supported Formats For Script Below - 720x480p60, 720(1440)x480i60, 720x576p50, 720(1440)x576i50, 800x600(SVGA)@60, 640x480(VGA)@60, 800x480(WVGA)@60, 1024x768(XGA)@60 :01-17 HDMI to MIPI TxA CSI 2-Lane - RGB666, Up to 600Mbps: E0 FF FF ; SW reset delay 5 ; E0 01 76 ; ADI Required Write E0 05 4A ; Setting Vid_Std to 720x480p60 E0 F2 01 ; Enable I2C Read Auto-Increment E0 F3 4C ; DPLL Map Address Set to 0x4C E0 F4 44 ; CP Map Address Set to 0x44 E0 F5 68 ; HDMI RX Map Address Set to 0x68 E0 F6 6C ; EDID Map Address Set to 0x6C E0 F7 64 ; HDMI RX Repeater Map Address Set to 0x64 E0 F8 62 ; HDMI RX Infoframe Map Address Set to 0x62 E0 F9 F0 ; CBUS Map Address Set to 0xF0 E0 FA 82 ; CEC Map Address Set to 0x82 E0 FB F2 ; SDP Main Map Address Set to 0xF2 E0 FC 90 ; CSI-TXB Map Address Set to 0x90 E0 FD 94 ; CSI-TXA Map Address Set to 0x94 E0 00 40 ; Disable chip powerdown & Enable HDMI Rx block 64 40 83 ; Enable HDCP 1.1 68 00 08 ; Foreground Channel = A 68 98 FF ; ADI Required Write 68 99 A3 ; ADI Required Write 68 9A 00 ; ADI Required Write 68 9B 0A ; ADI Required Write 68 9D 40 ; ADI Required Write 68 CB 09 ; ADI Required Write 68 3D 10 ; ADI Required Write 68 3E 7B ; ADI Required Write 68 3F 5E ; ADI Required Write 68 4E FE ; ADI Required Write 68 4F 18 ; ADI Required Write 68 57 A3 ; ADI Required Write 68 58 04 ; ADI Required Write 68 85 10 ; ADI Required Write 68 83 00 ; Enable All Terminations 68 A3 01 ; ADI Required Write 68 BE 00 ; ADI Required Write 68 6C 01 ; HPA Manual Enable 68 F8 01 ; HPA Asserted 68 0F 00 ; Audio Mute Speed Set to Fastest (Smallest Step Size) E0 04 02 ; RGB Out of CP E0 12 F0 ; CSC Depends on ip Packets - SDR 444 E0 17 B8 ; Configure for RGB666 & Luma & Chroma Values Can Reach 254d E0 03 86 ; CP-Insert_AV_Code 44 7C 00 ; ADI Required Write E0 0C E0 ; Enable LLC_DLL & Double LLC Timing E0 0E DD ; LLC/PIX/SPI PINS TRISTATED AUD Outputs Enabled E0 10 A0 ; Enable 4-lane CSI Tx & Pixel Port 94 00 82 ; Enable 2-lane MIPI 94 00 A2 ; Set Auto DPHY Timing 94 DB 10 ; ADI Required Write 94 D6 07 ; ADI Required Write 94 C4 0A ; ADI Required Write 94 71 33 ; ADI Required Write 94 72 11 ; ADI Required Write 94 F0 00 ; i2c_dphy_pwdn - 1'b0 94 31 82 ; ADI Required Write 94 1E 40 ; ADI Required Write 94 DA 01 ; i2c_mipi_pll_en - 1'b1 delay 2 ; 94 00 22 ; Power-up CSI-TX delay 1 ; 94 C1 2B ; ADI Required Write delay 1 ; 94 31 80 ; ADI Required Write End ; Supported Formats For Script Below - 1280x720p60, 1920x1080i60, 1280x720p50, 1920x1080i50, 1280x1024(SXGA)@60 :01-18 HDMI to MIPI TxA CSI 2-Lane - RGB666, Over 600Mbps: E0 FF FF ; SW reset delay 5 ; E0 01 76 ; ADI Required Write E0 05 85 ; Setting Vid_Std to 1280x1024(SXGA)@60 E0 F2 01 ; Enable I2C Read Auto-Increment E0 F3 4C ; DPLL Map Address Set to 0x4C E0 F4 44 ; CP Map Address Set to 0x44 E0 F5 68 ; HDMI RX Map Address Set to 0x68 E0 F6 6C ; EDID Map Address Set to 0x6C E0 F7 64 ; HDMI RX Repeater Map Address Set to 0x64 E0 F8 62 ; HDMI RX Infoframe Map Address Set to 0x62 E0 F9 F0 ; CBUS Map Address Set to 0xF0 E0 FA 82 ; CEC Map Address Set to 0x82 E0 FB F2 ; SDP Main Map Address Set to 0xF2 E0 FC 90 ; CSI-TXB Map Address Set to 0x90 E0 FD 94 ; CSI-TXA Map Address Set to 0x94 E0 00 40 ; Disable chip powerdown & Enable HDMI Rx block 64 40 83 ; Enable HDCP 1.1 68 00 08 ; Foreground Channel = A 68 98 FF ; ADI Required Write 68 99 A3 ; ADI Required Write 68 9A 00 ; ADI Required Write 68 9B 0A ; ADI Required Write 68 9D 40 ; ADI Required Write 68 CB 09 ; ADI Required Write 68 3D 10 ; ADI Required Write 68 3E 7B ; ADI Required Write 68 3F 5E ; ADI Required Write 68 4E FE ; ADI Required Write 68 4F 18 ; ADI Required Write 68 57 A3 ; ADI Required Write 68 58 04 ; ADI Required Write 68 85 10 ; ADI Required Write 68 83 00 ; Enable All Terminations 68 A3 01 ; ADI Required Write 68 BE 00 ; ADI Required Write 68 6C 01 ; HPA Manual Enable 68 F8 01 ; HPA Asserted 68 0F 00 ; Audio Mute Speed Set to Fastest (Smallest Step Size) E0 04 02 ; RGB Out of CP E0 12 F0 ; CSC Depends on ip Packets - SDR 444 E0 17 B8 ; Configure for RGB666 & Luma & Chroma Values Can Reach 254d E0 03 86 ; CP-Insert_AV_Code 44 7C 00 ; ADI Required Write E0 0C E0 ; Enable LLC_DLL & Double LLC Timing E0 0E DD ; LLC/PIX/SPI PINS TRISTATED AUD Outputs Enabled E0 10 A0 ; Enable 4-lane CSI Tx & Pixel Port 94 00 82 ; Enable 2-lane MIPI 94 00 A2 ; Set Auto DPHY Timing 94 DB 13 ; ADI Required Write 94 D6 07 ; ADI Required Write 94 C4 0A ; ADI Required Write 94 71 33 ; ADI Required Write 94 72 11 ; ADI Required Write 94 F0 00 ; i2c_dphy_pwdn - 1'b0 94 31 82 ; ADI Required Write 94 1E 40 ; ADI Required Write 94 DA 01 ; i2c_mipi_pll_en - 1'b1 delay 2 ; 94 00 22 ; Power-up CSI-TX delay 1 ; 94 C1 2B ; ADI Required Write delay 1 ; 94 31 80 ; ADI Required Write End ; Supported Formats For Script Below - 720x480p60, 720(1440)x480i60, 720x576p50, 720(1440)x576i50, 800x600(SVGA)@60, 640x480(VGA)@60, 800x480(WVGA)@60 :01-19 HDMI to MIPI TxA CSI 2-Lane - RGB888, Up to 600Mbps: E0 FF FF ; SW reset delay 5 ; E0 01 76 ; ADI Required Write E0 05 4A ; Setting Vid_Std to 720x480p60 E0 F2 01 ; Enable I2C Read Auto-Increment E0 F3 4C ; DPLL Map Address Set to 0x4C E0 F4 44 ; CP Map Address Set to 0x44 E0 F5 68 ; HDMI RX Map Address Set to 0x68 E0 F6 6C ; EDID Map Address Set to 0x6C E0 F7 64 ; HDMI RX Repeater Map Address Set to 0x64 E0 F8 62 ; HDMI RX Infoframe Map Address Set to 0x62 E0 F9 F0 ; CBUS Map Address Set to 0xF0 E0 FA 82 ; CEC Map Address Set to 0x82 E0 FB F2 ; SDP Main Map Address Set to 0xF2 E0 FC 90 ; CSI-TXB Map Address Set to 0x90 E0 FD 94 ; CSI-TXA Map Address Set to 0x94 E0 00 40 ; Disable chip powerdown & Enable HDMI Rx block 64 40 83 ; Enable HDCP 1.1 68 00 08 ; Foreground Channel = A 68 98 FF ; ADI Required Write 68 99 A3 ; ADI Required Write 68 9A 00 ; ADI Required Write 68 9B 0A ; ADI Required Write 68 9D 40 ; ADI Required Write 68 CB 09 ; ADI Required Write 68 3D 10 ; ADI Required Write 68 3E 7B ; ADI Required Write 68 3F 5E ; ADI Required Write 68 4E FE ; ADI Required Write 68 4F 18 ; ADI Required Write 68 57 A3 ; ADI Required Write 68 58 04 ; ADI Required Write 68 85 10 ; ADI Required Write 68 83 00 ; Enable All Terminations 68 A3 01 ; ADI Required Write 68 BE 00 ; ADI Required Write 68 6C 01 ; HPA Manual Enable 68 F8 01 ; HPA Asserted 68 0F 00 ; Audio Mute Speed Set to Fastest (Smallest Step Size) E0 04 02 ; RGB Out of CP E0 12 F0 ; CSC Depends on ip Packets - SDR 444 E0 17 80 ; Luma & Chroma Values Can Reach 254d E0 03 86 ; CP-Insert_AV_Code 44 7C 00 ; ADI Required Write E0 0C E0 ; Enable LLC_DLL & Double LLC Timing E0 0E DD ; LLC/PIX/SPI PINS TRISTATED AUD Outputs Enabled E0 10 A0 ; Enable 4-lane CSI Tx & Pixel Port 94 00 82 ; Enable 2-lane MIPI 94 00 A2 ; Set Auto DPHY Timing 94 DB 10 ; ADI Required Write 94 D6 07 ; ADI Required Write 94 C4 0A ; ADI Required Write 94 71 33 ; ADI Required Write 94 72 11 ; ADI Required Write 94 F0 00 ; i2c_dphy_pwdn - 1'b0 94 31 82 ; ADI Required Write 94 1E 40 ; ADI Required Write 94 DA 01 ; i2c_mipi_pll_en - 1'b1 delay 2 ; 94 00 22 ; Power-up CSI-TX delay 1 ; 94 C1 2B ; ADI Required Write delay 1 ; 94 31 80 ; ADI Required Write End ; Supported Formats For Script Below - 1280x720p60, 1920x1080i60, 1280x720p50, 1920x1080i50, 1024x768(XGA)@60 :01-20 HDMI to MIPI TxA CSI 2-Lane - RGB888, Over 600Mbps: E0 FF FF ; SW reset delay 5 ; E0 01 76 ; ADI Required Write E0 05 8C ; Setting Vid_Std to 1024x768(XGA)@60 E0 F2 01 ; Enable I2C Read Auto-Increment E0 F3 4C ; DPLL Map Address Set to 0x4C E0 F4 44 ; CP Map Address Set to 0x44 E0 F5 68 ; HDMI RX Map Address Set to 0x68 E0 F6 6C ; EDID Map Address Set to 0x6C E0 F7 64 ; HDMI RX Repeater Map Address Set to 0x64 E0 F8 62 ; HDMI RX Infoframe Map Address Set to 0x62 E0 F9 F0 ; CBUS Map Address Set to 0xF0 E0 FA 82 ; CEC Map Address Set to 0x82 E0 FB F2 ; SDP Main Map Address Set to 0xF2 E0 FC 90 ; CSI-TXB Map Address Set to 0x90 E0 FD 94 ; CSI-TXA Map Address Set to 0x94 E0 00 40 ; Disable chip powerdown & Enable HDMI Rx block 64 40 83 ; Enable HDCP 1.1 68 00 08 ; Foreground Channel = A 68 98 FF ; ADI Required Write 68 99 A3 ; ADI Required Write 68 9A 00 ; ADI Required Write 68 9B 0A ; ADI Required Write 68 9D 40 ; ADI Required Write 68 CB 09 ; ADI Required Write 68 3D 10 ; ADI Required Write 68 3E 7B ; ADI Required Write 68 3F 5E ; ADI Required Write 68 4E FE ; ADI Required Write 68 4F 18 ; ADI Required Write 68 57 A3 ; ADI Required Write 68 58 04 ; ADI Required Write 68 85 10 ; ADI Required Write 68 83 00 ; Enable All Terminations 68 A3 01 ; ADI Required Write 68 BE 00 ; ADI Required Write 68 6C 01 ; HPA Manual Enable 68 F8 01 ; HPA Asserted 68 0F 00 ; Audio Mute Speed Set to Fastest (Smallest Step Size) E0 04 02 ; RGB Out of CP E0 12 F0 ; CSC Depends on ip Packets - SDR 444 E0 17 80 ; Luma & Chroma Values Can Reach 254d E0 03 86 ; CP-Insert_AV_Code 44 7C 00 ; ADI Required Write E0 0C E0 ; Enable LLC_DLL & Double LLC Timing E0 0E DD ; LLC/PIX/SPI PINS TRISTATED AUD Outputs Enabled E0 10 A0 ; Enable 4-lane CSI Tx & Pixel Port 94 00 82 ; Enable 2-lane MIPI 94 00 A2 ; Set Auto DPHY Timing 94 DB 13 ; ADI Required Write 94 D6 07 ; ADI Required Write 94 C4 0A ; ADI Required Write 94 71 33 ; ADI Required Write 94 72 11 ; ADI Required Write 94 F0 00 ; i2c_dphy_pwdn - 1'b0 94 31 82 ; ADI Required Write 94 1E 40 ; ADI Required Write 94 DA 01 ; i2c_mipi_pll_en - 1'b1 delay 2 ; 94 00 22 ; Power-up CSI-TX delay 1 ; 94 C1 2B ; ADI Required Write delay 1 ; 94 31 80 ; ADI Required Write End ; Supported Formats For Script Below - 1280x720p60, 1920x1080i60, 1280x720p50, 1920x1080i50, 1920x1080p50, 800x600(SVGA)@60, 1280x1024(SXGA)@60, 800x480(WVGA)@60, 1024x768(XGA)@60 :01-21 HDMI to MIPI TxA CSI 4-Lane - YUV422 8-Bit, Up to 600Mbps: E0 FF FF ; SW reset delay 5 ; E0 01 76 ; ADI Required Write E0 05 81 ; Setting Vid_Std to 800x600(SVGA)@60 E0 F2 01 ; Enable I2C Read Auto-Increment E0 F3 4C ; DPLL Map Address Set to 0x4C E0 F4 44 ; CP Map Address Set to 0x44 E0 F5 68 ; HDMI RX Map Address Set to 0x68 E0 F6 6C ; EDID Map Address Set to 0x6C E0 F7 64 ; HDMI RX Repeater Map Address Set to 0x64 E0 F8 62 ; HDMI RX Infoframe Map Address Set to 0x62 E0 F9 F0 ; CBUS Map Address Set to 0xF0 E0 FA 82 ; CEC Map Address Set to 0x82 E0 FB F2 ; SDP Main Map Address Set to 0xF2 E0 FC 90 ; CSI-TXB Map Address Set to 0x90 E0 FD 94 ; CSI-TXA Map Address Set to 0x94 E0 00 40 ; Disable chip powerdown & Enable HDMI Rx block 64 40 83 ; Enable HDCP 1.1 68 00 08 ; Foreground Channel = A 68 98 FF ; ADI Required Write 68 99 A3 ; ADI Required Write 68 9A 00 ; ADI Required Write 68 9B 0A ; ADI Required Write 68 9D 40 ; ADI Required Write 68 CB 09 ; ADI Required Write 68 3D 10 ; ADI Required Write 68 3E 7B ; ADI Required Write 68 3F 5E ; ADI Required Write 68 4E FE ; ADI Required Write 68 4F 18 ; ADI Required Write 68 57 A3 ; ADI Required Write 68 58 04 ; ADI Required Write 68 85 10 ; ADI Required Write 68 83 00 ; Enable All Terminations 68 A3 01 ; ADI Required Write 68 BE 00 ; ADI Required Write 68 6C 01 ; HPA Manual Enable 68 F8 01 ; HPA Asserted 68 0F 00 ; Audio Mute Speed Set to Fastest (Smallest Step Size) E0 04 00 ; YCrCb output E0 12 F2 ; CSC Depends on ip Packets - SDR422 set E0 17 80 ; Luma & Chroma Values Can Reach 254d E0 03 86 ; CP-Insert_AV_Code 44 7C 00 ; ADI Required Write E0 0C E0 ; Enable LLC_DLL & Double LLC Timing E0 0E DD ; LLC/PIX/SPI PINS TRISTATED AUD Outputs Enabled E0 10 A0 ; Enable 4-lane CSI Tx & Pixel Port 94 00 84 ; Enable 4-lane MIPI 94 00 A4 ; Set Auto DPHY Timing 94 DB 10 ; ADI Required Write 94 D6 07 ; ADI Required Write 94 C4 0A ; ADI Required Write 94 71 33 ; ADI Required Write 94 72 11 ; ADI Required Write 94 F0 00 ; i2c_dphy_pwdn - 1'b0 94 31 82 ; ADI Required Write 94 1E 40 ; ADI Required Write 94 DA 01 ; i2c_mipi_pll_en - 1'b1 delay 2 ; 94 00 24 ; Power-up CSI-TX delay 1 ; 94 C1 2B ; ADI Required Write delay 1 ; 94 31 80 ; ADI Required Write End ; Supported Formats For Script Below - 1600x1200(UXGA)@60 :01-22 HDMI to MIPI TxA CSI 4-Lane - YUV422 8-Bit, Over 600Mbps: E0 FF FF ; SW reset delay 5 ; E0 01 76 ; ADI Required Write E0 05 96 ; Setting Vid_Std to 1600x1200(UXGA)@60 E0 F2 01 ; Enable I2C Read Auto-Increment E0 F3 4C ; DPLL Map Address Set to 0x4C E0 F4 44 ; CP Map Address Set to 0x44 E0 F5 68 ; HDMI RX Map Address Set to 0x68 E0 F6 6C ; EDID Map Address Set to 0x6C E0 F7 64 ; HDMI RX Repeater Map Address Set to 0x64 E0 F8 62 ; HDMI RX Infoframe Map Address Set to 0x62 E0 F9 F0 ; CBUS Map Address Set to 0xF0 E0 FA 82 ; CEC Map Address Set to 0x82 E0 FB F2 ; SDP Main Map Address Set to 0xF2 E0 FC 90 ; CSI-TXB Map Address Set to 0x90 E0 FD 94 ; CSI-TXA Map Address Set to 0x94 E0 00 40 ; Disable chip powerdown & Enable HDMI Rx block 64 40 83 ; Enable HDCP 1.1 68 00 08 ; Foreground Channel = A 68 98 FF ; ADI Required Write 68 99 A3 ; ADI Required Write 68 9A 00 ; ADI Required Write 68 9B 0A ; ADI Required Write 68 9D 40 ; ADI Required Write 68 CB 09 ; ADI Required Write 68 3D 10 ; ADI Required Write 68 3E 7B ; ADI Required Write 68 3F 5E ; ADI Required Write 68 4E FE ; ADI Required Write 68 4F 18 ; ADI Required Write 68 57 A3 ; ADI Required Write 68 58 04 ; ADI Required Write 68 85 10 ; ADI Required Write 68 83 00 ; Enable All Terminations 68 A3 01 ; ADI Required Write 68 BE 00 ; ADI Required Write 68 6C 01 ; HPA Manual Enable 68 F8 01 ; HPA Asserted 68 0F 00 ; Audio Mute Speed Set to Fastest (Smallest Step Size) E0 04 00 ; YCrCb output E0 12 F2 ; CSC Depends on ip Packets - SDR422 set E0 17 80 ; Luma & Chroma Values Can Reach 254d E0 03 86 ; CP-Insert_AV_Code 44 7C 00 ; ADI Required Write E0 0C E0 ; Enable LLC_DLL & Double LLC Timing E0 0E DD ; LLC/PIX/SPI PINS TRISTATED AUD Outputs Enabled E0 10 A0 ; Enable 4-lane CSI Tx & Pixel Port 94 00 84 ; Enable 4-lane MIPI 94 00 A4 ; Set Auto DPHY Timing 94 DB 13 ; ADI Required Write 94 D6 07 ; ADI Required Write 94 C4 0A ; ADI Required Write 94 71 33 ; ADI Required Write 94 72 11 ; ADI Required Write 94 F0 00 ; i2c_dphy_pwdn - 1'b0 94 31 82 ; ADI Required Write 94 1E 40 ; ADI Required Write 94 DA 01 ; i2c_mipi_pll_en - 1'b1 delay 2 ; 94 00 24 ; Power-up CSI-TX delay 1 ; 94 C1 2B ; ADI Required Write delay 1 ; 94 31 80 ; ADI Required Write End ; Supported Formats For Script Below - 720x480p60, 1280x720p60, 1920x1080i60, 720x576p50, 1280x720p50, 1920x1080i50, 800x600(SVGA)@60, 1280x1024(SXGA)@60, 640x480(VGA)@60, 800x480(WVGA)@60, 1024x768(XGA)@60 :01-23 HDMI to MIPI TxA CSI 4-Lane - YUV422 10-Bit, Up to 600Mbps: E0 FF FF ; SW reset delay 5 ; E0 01 76 ; ADI Required Write E0 05 4A ; Setting Vid_Std to 720x480p60 E0 F2 01 ; Enable I2C Read Auto-Increment E0 F3 4C ; DPLL Map Address Set to 0x4C E0 F4 44 ; CP Map Address Set to 0x44 E0 F5 68 ; HDMI RX Map Address Set to 0x68 E0 F6 6C ; EDID Map Address Set to 0x6C E0 F7 64 ; HDMI RX Repeater Map Address Set to 0x64 E0 F8 62 ; HDMI RX Infoframe Map Address Set to 0x62 E0 F9 F0 ; CBUS Map Address Set to 0xF0 E0 FA 82 ; CEC Map Address Set to 0x82 E0 FB F2 ; SDP Main Map Address Set to 0xF2 E0 FC 90 ; CSI-TXB Map Address Set to 0x90 E0 FD 94 ; CSI-TXA Map Address Set to 0x94 E0 00 40 ; Disable chip powerdown & Enable HDMI Rx block 64 40 83 ; Enable HDCP 1.1 68 00 08 ; Foreground Channel = A 68 98 FF ; ADI Required Write 68 99 A3 ; ADI Required Write 68 9A 00 ; ADI Required Write 68 9B 0A ; ADI Required Write 68 9D 40 ; ADI Required Write 68 CB 09 ; ADI Required Write 68 3D 10 ; ADI Required Write 68 3E 7B ; ADI Required Write 68 3F 5E ; ADI Required Write 68 4E FE ; ADI Required Write 68 4F 18 ; ADI Required Write 68 57 A3 ; ADI Required Write 68 58 04 ; ADI Required Write 68 85 10 ; ADI Required Write 68 83 00 ; Enable All Terminations 68 A3 01 ; ADI Required Write 68 BE 00 ; ADI Required Write 68 6C 01 ; HPA Manual Enable 68 F8 01 ; HPA Asserted 68 0F 00 ; Audio Mute Speed Set to Fastest (Smallest Step Size) E0 04 00 ; YCrCb output E0 12 F3 ; CSC Depends on ip Packets - SDR422 set - 10Bit E0 17 80 ; Luma & Chroma Values Can Reach 254d E0 03 86 ; CP-Insert_AV_Code 44 7C 00 ; ADI Required Write E0 0C E0 ; Enable LLC_DLL & Double LLC Timing E0 0E DD ; LLC/PIX/SPI PINS TRISTATED AUD Outputs Enabled E0 10 A0 ; Enable 4-lane CSI Tx & Pixel Port 94 00 84 ; Enable 4-lane MIPI 94 00 A4 ; Set Auto DPHY Timing 94 DB 10 ; ADI Required Write 94 D6 07 ; ADI Required Write 94 C4 0A ; ADI Required Write 94 71 33 ; ADI Required Write 94 72 11 ; ADI Required Write 94 F0 00 ; i2c_dphy_pwdn - 1'b0 94 31 82 ; ADI Required Write 94 1E 40 ; ADI Required Write 94 DA 01 ; i2c_mipi_pll_en - 1'b1 delay 2 ; 94 00 24 ; Power-up CSI-TX delay 1 ; 94 C1 2B ; ADI Required Write delay 1 ; 94 31 80 ; ADI Required Write End ; Supported Formats For Script Below - 1920x1080p50, 1600x1200(UXGA)@60 :01-24 HDMI to MIPI TxA CSI 4-Lane - YUV422 10-Bit, Over 600Mbps: E0 FF FF ; SW reset delay 5 ; E0 01 76 ; ADI Required Write E0 05 96 ; Setting Vid_Std to 1600x1200(UXGA)@60 E0 F2 01 ; Enable I2C Read Auto-Increment E0 F3 4C ; DPLL Map Address Set to 0x4C E0 F4 44 ; CP Map Address Set to 0x44 E0 F5 68 ; HDMI RX Map Address Set to 0x68 E0 F6 6C ; EDID Map Address Set to 0x6C E0 F7 64 ; HDMI RX Repeater Map Address Set to 0x64 E0 F8 62 ; HDMI RX Infoframe Map Address Set to 0x62 E0 F9 F0 ; CBUS Map Address Set to 0xF0 E0 FA 82 ; CEC Map Address Set to 0x82 E0 FB F2 ; SDP Main Map Address Set to 0xF2 E0 FC 90 ; CSI-TXB Map Address Set to 0x90 E0 FD 94 ; CSI-TXA Map Address Set to 0x94 E0 00 40 ; Disable chip powerdown & Enable HDMI Rx block 64 40 83 ; Enable HDCP 1.1 68 00 08 ; Foreground Channel = A 68 98 FF ; ADI Required Write 68 99 A3 ; ADI Required Write 68 9A 00 ; ADI Required Write 68 9B 0A ; ADI Required Write 68 9D 40 ; ADI Required Write 68 CB 09 ; ADI Required Write 68 3D 10 ; ADI Required Write 68 3E 7B ; ADI Required Write 68 3F 5E ; ADI Required Write 68 4E FE ; ADI Required Write 68 4F 18 ; ADI Required Write 68 57 A3 ; ADI Required Write 68 58 04 ; ADI Required Write 68 85 10 ; ADI Required Write 68 83 00 ; Enable All Terminations 68 A3 01 ; ADI Required Write 68 BE 00 ; ADI Required Write 68 6C 01 ; HPA Manual Enable 68 F8 01 ; HPA Asserted 68 0F 00 ; Audio Mute Speed Set to Fastest (Smallest Step Size) E0 04 00 ; YCrCb output E0 12 F3 ; CSC Depends on ip Packets - SDR422 set - 10Bit E0 17 80 ; Luma & Chroma Values Can Reach 254d E0 03 86 ; CP-Insert_AV_Code 44 7C 00 ; ADI Required Write E0 0C E0 ; Enable LLC_DLL & Double LLC Timing E0 0E DD ; LLC/PIX/SPI PINS TRISTATED AUD Outputs Enabled E0 10 A0 ; Enable 4-lane CSI Tx & Pixel Port 94 00 84 ; Enable 4-lane MIPI 94 00 A4 ; Set Auto DPHY Timing 94 DB 13 ; ADI Required Write 94 D6 07 ; ADI Required Write 94 C4 0A ; ADI Required Write 94 71 33 ; ADI Required Write 94 72 11 ; ADI Required Write 94 F0 00 ; i2c_dphy_pwdn - 1'b0 94 31 82 ; ADI Required Write 94 1E 40 ; ADI Required Write 94 DA 01 ; i2c_mipi_pll_en - 1'b1 delay 2 ; 94 00 24 ; Power-up CSI-TX delay 1 ; 94 C1 2B ; ADI Required Write delay 1 ; 94 31 80 ; ADI Required Write End ; Supported Formats For Script Below - 1280x720p60, 1920x1080i60, 1280x720p50, 1920x1080i50, 1920x1080p50, 800x600(SVGA)@60, 1280x1024(SXGA)@60, 800x480(WVGA)@60, 1024x768(XGA)@60 :01-25 HDMI to MIPI TxA CSI 4-Lane - RGB565, Up to 600Mbps: E0 FF FF ; SW reset delay 5 ; E0 01 76 ; ADI Required Write E0 05 81 ; Setting Vid_Std to 800x600(SVGA)@60 E0 F2 01 ; Enable I2C Read Auto-Increment E0 F3 4C ; DPLL Map Address Set to 0x4C E0 F4 44 ; CP Map Address Set to 0x44 E0 F5 68 ; HDMI RX Map Address Set to 0x68 E0 F6 6C ; EDID Map Address Set to 0x6C E0 F7 64 ; HDMI RX Repeater Map Address Set to 0x64 E0 F8 62 ; HDMI RX Infoframe Map Address Set to 0x62 E0 F9 F0 ; CBUS Map Address Set to 0xF0 E0 FA 82 ; CEC Map Address Set to 0x82 E0 FB F2 ; SDP Main Map Address Set to 0xF2 E0 FC 90 ; CSI-TXB Map Address Set to 0x90 E0 FD 94 ; CSI-TXA Map Address Set to 0x94 E0 00 40 ; Disable chip powerdown & Enable HDMI Rx block 64 40 83 ; Enable HDCP 1.1 68 00 08 ; Foreground Channel = A 68 98 FF ; ADI Required Write 68 99 A3 ; ADI Required Write 68 9A 00 ; ADI Required Write 68 9B 0A ; ADI Required Write 68 9D 40 ; ADI Required Write 68 CB 09 ; ADI Required Write 68 3D 10 ; ADI Required Write 68 3E 7B ; ADI Required Write 68 3F 5E ; ADI Required Write 68 4E FE ; ADI Required Write 68 4F 18 ; ADI Required Write 68 57 A3 ; ADI Required Write 68 58 04 ; ADI Required Write 68 85 10 ; ADI Required Write 68 83 00 ; Enable All Terminations 68 A3 01 ; ADI Required Write 68 BE 00 ; ADI Required Write 68 6C 01 ; HPA Manual Enable 68 F8 01 ; HPA Asserted 68 0F 00 ; Audio Mute Speed Set to Fastest (Smallest Step Size) E0 04 02 ; RGB Out of CP E0 12 F0 ; CSC Depends on ip Packets - SDR 444 E0 17 B8 ; Configure for RGB565 & Luma & Chroma Values Can Reach 254d E0 03 86 ; CP-Insert_AV_Code 44 7C 00 ; ADI Required Write E0 0C E0 ; Enable LLC_DLL & Double LLC Timing E0 0E DD ; LLC/PIX/SPI PINS TRISTATED AUD Outputs Enabled E0 10 A0 ; Enable 4-lane CSI Tx & Pixel Port 94 00 84 ; Enable 4-lane MIPI 94 00 A4 ; Set Auto DPHY Timing 94 DB 10 ; ADI Required Write 94 7E 98 ; ADI Required Write 94 D6 07 ; ADI Required Write 94 C4 0A ; ADI Required Write 94 71 33 ; ADI Required Write 94 72 11 ; ADI Required Write 94 F0 00 ; i2c_dphy_pwdn - 1'b0 94 31 82 ; ADI Required Write 94 1E 40 ; ADI Required Write 94 DA 01 ; i2c_mipi_pll_en - 1'b1 delay 2 ; 94 00 24 ; Power-up CSI-TX delay 1 ; 94 C1 2B ; ADI Required Write delay 1 ; 94 31 80 ; ADI Required Write End ; Supported Formats For Script Below - 1600x1200(UXGA)@60 :01-26 HDMI to MIPI TxA CSI 4-Lane - RGB565, Over 600Mbps: E0 FF FF ; SW reset delay 5 ; E0 01 76 ; ADI Required Write E0 05 96 ; Setting Vid_Std to 1600x1200(UXGA)@60 E0 F2 01 ; Enable I2C Read Auto-Increment E0 F3 4C ; DPLL Map Address Set to 0x4C E0 F4 44 ; CP Map Address Set to 0x44 E0 F5 68 ; HDMI RX Map Address Set to 0x68 E0 F6 6C ; EDID Map Address Set to 0x6C E0 F7 64 ; HDMI RX Repeater Map Address Set to 0x64 E0 F8 62 ; HDMI RX Infoframe Map Address Set to 0x62 E0 F9 F0 ; CBUS Map Address Set to 0xF0 E0 FA 82 ; CEC Map Address Set to 0x82 E0 FB F2 ; SDP Main Map Address Set to 0xF2 E0 FC 90 ; CSI-TXB Map Address Set to 0x90 E0 FD 94 ; CSI-TXA Map Address Set to 0x94 E0 00 40 ; Disable chip powerdown & Enable HDMI Rx block 64 40 83 ; Enable HDCP 1.1 68 00 08 ; Foreground Channel = A 68 98 FF ; ADI Required Write 68 99 A3 ; ADI Required Write 68 9A 00 ; ADI Required Write 68 9B 0A ; ADI Required Write 68 9D 40 ; ADI Required Write 68 CB 09 ; ADI Required Write 68 3D 10 ; ADI Required Write 68 3E 7B ; ADI Required Write 68 3F 5E ; ADI Required Write 68 4E FE ; ADI Required Write 68 4F 18 ; ADI Required Write 68 57 A3 ; ADI Required Write 68 58 04 ; ADI Required Write 68 85 10 ; ADI Required Write 68 83 00 ; Enable All Terminations 68 A3 01 ; ADI Required Write 68 BE 00 ; ADI Required Write 68 6C 01 ; HPA Manual Enable 68 F8 01 ; HPA Asserted 68 0F 00 ; Audio Mute Speed Set to Fastest (Smallest Step Size) E0 04 02 ; RGB Out of CP E0 12 F0 ; CSC Depends on ip Packets - SDR 444 E0 17 B8 ; Configure for RGB565 & Luma & Chroma Values Can Reach 254d E0 03 86 ; CP-Insert_AV_Code 44 7C 00 ; ADI Required Write E0 0C E0 ; Enable LLC_DLL & Double LLC Timing E0 0E DD ; LLC/PIX/SPI PINS TRISTATED AUD Outputs Enabled E0 10 A0 ; Enable 4-lane CSI Tx & Pixel Port 94 00 84 ; Enable 4-lane MIPI 94 00 A4 ; Set Auto DPHY Timing 94 7E 98 ; ADI Required Write 94 DB 13 ; ADI Required Write 94 D6 07 ; ADI Required Write 94 C4 0A ; ADI Required Write 94 71 33 ; ADI Required Write 94 72 11 ; ADI Required Write 94 F0 00 ; i2c_dphy_pwdn - 1'b0 94 31 82 ; ADI Required Write 94 1E 40 ; ADI Required Write 94 DA 01 ; i2c_mipi_pll_en - 1'b1 delay 2 ; 94 00 24 ; Power-up CSI-TX delay 1 ; 94 C1 2B ; ADI Required Write delay 1 ; 94 31 80 ; ADI Required Write End ; Supported Formats For Script Below - 720x480p60, 1280x720p60, 1920x1080i60, 720x576p50, 1280x720p50, 1920x1080i50, 800x600(SVGA)@60, 1280x1024(SXGA)@60, 800x480(WVGA)@60, 1024x768(XGA)@60 :01-27 HDMI to MIPI TxA CSI 4-Lane - RGB666, Up to 600Mbps: E0 FF FF ; SW reset delay 5 ; E0 01 76 ; ADI Required Write E0 05 4A ; Setting Vid_Std to 720x480p60 E0 F2 01 ; Enable I2C Read Auto-Increment E0 F3 4C ; DPLL Map Address Set to 0x4C E0 F4 44 ; CP Map Address Set to 0x44 E0 F5 68 ; HDMI RX Map Address Set to 0x68 E0 F6 6C ; EDID Map Address Set to 0x6C E0 F7 64 ; HDMI RX Repeater Map Address Set to 0x64 E0 F8 62 ; HDMI RX Infoframe Map Address Set to 0x62 E0 F9 F0 ; CBUS Map Address Set to 0xF0 E0 FA 82 ; CEC Map Address Set to 0x82 E0 FB F2 ; SDP Main Map Address Set to 0xF2 E0 FC 90 ; CSI-TXB Map Address Set to 0x90 E0 FD 94 ; CSI-TXA Map Address Set to 0x94 E0 00 40 ; Disable chip powerdown & Enable HDMI Rx block 64 40 83 ; Enable HDCP 1.1 68 00 08 ; Foreground Channel = A 68 98 FF ; ADI Required Write 68 99 A3 ; ADI Required Write 68 9A 00 ; ADI Required Write 68 9B 0A ; ADI Required Write 68 9D 40 ; ADI Required Write 68 CB 09 ; ADI Required Write 68 3D 10 ; ADI Required Write 68 3E 7B ; ADI Required Write 68 3F 5E ; ADI Required Write 68 4E FE ; ADI Required Write 68 4F 18 ; ADI Required Write 68 57 A3 ; ADI Required Write 68 58 04 ; ADI Required Write 68 85 10 ; ADI Required Write 68 83 00 ; Enable All Terminations 68 A3 01 ; ADI Required Write 68 BE 00 ; ADI Required Write 68 6C 01 ; HPA Manual Enable 68 F8 01 ; HPA Asserted 68 0F 00 ; Audio Mute Speed Set to Fastest (Smallest Step Size) E0 04 02 ; RGB Out of CP E0 12 F0 ; CSC Depends on ip Packets - SDR 444 E0 17 B8 ; Configure for RGB666 & Luma & Chroma Values Can Reach 254d E0 03 86 ; CP-Insert_AV_Code 44 7C 00 ; ADI Required Write E0 0C E0 ; Enable LLC_DLL & Double LLC Timing E0 0E DD ; LLC/PIX/SPI PINS TRISTATED AUD Outputs Enabled E0 10 A0 ; Enable 4-lane CSI Tx & Pixel Port 94 00 84 ; Enable 4-lane MIPI 94 00 A4 ; Set Auto DPHY Timing 94 DB 10 ; ADI Required Write 94 D6 07 ; ADI Required Write 94 C4 0A ; ADI Required Write 94 71 33 ; ADI Required Write 94 72 11 ; ADI Required Write 94 F0 00 ; i2c_dphy_pwdn - 1'b0 94 31 82 ; ADI Required Write 94 1E 40 ; ADI Required Write 94 DA 01 ; i2c_mipi_pll_en - 1'b1 delay 2 ; 94 00 24 ; Power-up CSI-TX delay 1 ; 94 C1 2B ; ADI Required Write delay 1 ; 94 31 80 ; ADI Required Write End ; Supported Formats For Script Below - 1920x1080p50, 1600x1200(UXGA)@60 :01-28 HDMI to MIPI TxA CSI 4-Lane - RGB666, Over 600Mbps: E0 FF FF ; SW reset delay 5 ; E0 01 76 ; ADI Required Write E0 05 96 ; Setting Vid_Std to 1600x1200(UXGA)@60 E0 F2 01 ; Enable I2C Read Auto-Increment E0 F3 4C ; DPLL Map Address Set to 0x4C E0 F4 44 ; CP Map Address Set to 0x44 E0 F5 68 ; HDMI RX Map Address Set to 0x68 E0 F6 6C ; EDID Map Address Set to 0x6C E0 F7 64 ; HDMI RX Repeater Map Address Set to 0x64 E0 F8 62 ; HDMI RX Infoframe Map Address Set to 0x62 E0 F9 F0 ; CBUS Map Address Set to 0xF0 E0 FA 82 ; CEC Map Address Set to 0x82 E0 FB F2 ; SDP Main Map Address Set to 0xF2 E0 FC 90 ; CSI-TXB Map Address Set to 0x90 E0 FD 94 ; CSI-TXA Map Address Set to 0x94 E0 00 40 ; Disable chip powerdown & Enable HDMI Rx block 64 40 83 ; Enable HDCP 1.1 68 00 08 ; Foreground Channel = A 68 98 FF ; ADI Required Write 68 99 A3 ; ADI Required Write 68 9A 00 ; ADI Required Write 68 9B 0A ; ADI Required Write 68 9D 40 ; ADI Required Write 68 CB 09 ; ADI Required Write 68 3D 10 ; ADI Required Write 68 3E 7B ; ADI Required Write 68 3F 5E ; ADI Required Write 68 4E FE ; ADI Required Write 68 4F 18 ; ADI Required Write 68 57 A3 ; ADI Required Write 68 58 04 ; ADI Required Write 68 85 10 ; ADI Required Write 68 83 00 ; Enable All Terminations 68 A3 01 ; ADI Required Write 68 BE 00 ; ADI Required Write 68 6C 01 ; HPA Manual Enable 68 F8 01 ; HPA Asserted 68 0F 00 ; Audio Mute Speed Set to Fastest (Smallest Step Size) E0 04 02 ; RGB Out of CP E0 12 F0 ; CSC Depends on ip Packets - SDR 444 E0 17 B8 ; Configure for RGB666 & Luma & Chroma Values Can Reach 254d E0 03 86 ; CP-Insert_AV_Code 44 7C 00 ; ADI Required Write E0 0C E0 ; Enable LLC_DLL & Double LLC Timing E0 0E DD ; LLC/PIX/SPI PINS TRISTATED AUD Outputs Enabled E0 10 A0 ; Enable 4-lane CSI Tx & Pixel Port 94 00 84 ; Enable 4-lane MIPI 94 00 A4 ; Set Auto DPHY Timing 94 DB 13 ; ADI Required Write 94 D6 07 ; ADI Required Write 94 C4 0A ; ADI Required Write 94 71 33 ; ADI Required Write 94 72 11 ; ADI Required Write 94 F0 00 ; i2c_dphy_pwdn - 1'b0 94 31 82 ; ADI Required Write 94 1E 40 ; ADI Required Write 94 DA 01 ; i2c_mipi_pll_en - 1'b1 delay 2 ; 94 00 24 ; Power-up CSI-TX delay 1 ; 94 C1 2B ; ADI Required Write delay 1 ; 94 31 80 ; ADI Required Write End ; Supported Formats For Script Below - 720x480p60, 1280x720p60, 1920x1080i60, 720(1440)x480i60, 720x576p50, 1280x720p50, 1920x1080i50, 720(1440)x576i50, 800x600(SVGA)@60, 640x480(VGA)@60, 800x480(WVGA)@60, 1024x768(XGA)@60 :01-29 HDMI to MIPI TxA CSI 4-Lane - RGB888, Up to 600Mbps: E0 FF FF ; SW reset delay 5 ; E0 01 76 ; ADI Required Write E0 05 4A ; Setting Vid_Std to 720x480p60 E0 F2 01 ; Enable I2C Read Auto-Increment E0 F3 4C ; DPLL Map Address Set to 0x4C E0 F4 44 ; CP Map Address Set to 0x44 E0 F5 68 ; HDMI RX Map Address Set to 0x68 E0 F6 6C ; EDID Map Address Set to 0x6C E0 F7 64 ; HDMI RX Repeater Map Address Set to 0x64 E0 F8 62 ; HDMI RX Infoframe Map Address Set to 0x62 E0 F9 F0 ; CBUS Map Address Set to 0xF0 E0 FA 82 ; CEC Map Address Set to 0x82 E0 FB F2 ; SDP Main Map Address Set to 0xF2 E0 FC 90 ; CSI-TXB Map Address Set to 0x90 E0 FD 94 ; CSI-TXA Map Address Set to 0x94 E0 00 40 ; Disable chip powerdown & Enable HDMI Rx block 64 40 83 ; Enable HDCP 1.1 68 00 08 ; Foreground Channel = A 68 98 FF ; ADI Required Write 68 99 A3 ; ADI Required Write 68 9A 00 ; ADI Required Write 68 9B 0A ; ADI Required Write 68 9D 40 ; ADI Required Write 68 CB 09 ; ADI Required Write 68 3D 10 ; ADI Required Write 68 3E 7B ; ADI Required Write 68 3F 5E ; ADI Required Write 68 4E FE ; ADI Required Write 68 4F 18 ; ADI Required Write 68 57 A3 ; ADI Required Write 68 58 04 ; ADI Required Write 68 85 10 ; ADI Required Write 68 83 00 ; Enable All Terminations 68 A3 01 ; ADI Required Write 68 BE 00 ; ADI Required Write 68 6C 01 ; HPA Manual Enable 68 F8 01 ; HPA Asserted 68 0F 00 ; Audio Mute Speed Set to Fastest (Smallest Step Size) E0 04 02 ; RGB Out of CP E0 12 F0 ; CSC Depends on ip Packets - SDR 444 E0 17 80 ; Luma & Chroma Values Can Reach 254d E0 03 86 ; CP-Insert_AV_Code 44 7C 00 ; ADI Required Write E0 0C E0 ; Enable LLC_DLL & Double LLC Timing E0 0E DD ; LLC/PIX/SPI PINS TRISTATED AUD Outputs Enabled E0 10 A0 ; Enable 4-lane CSI Tx & Pixel Port 94 00 84 ; Enable 4-lane MIPI 94 00 A4 ; Set Auto DPHY Timing 94 DB 10 ; ADI Required Write 94 D6 07 ; ADI Required Write 94 C4 0A ; ADI Required Write 94 71 33 ; ADI Required Write 94 72 11 ; ADI Required Write 94 F0 00 ; i2c_dphy_pwdn - 1'b0 94 31 82 ; ADI Required Write 94 1E 40 ; ADI Required Write 94 DA 01 ; i2c_mipi_pll_en - 1'b1 delay 2 ; 94 00 24 ; Power-up CSI-TX delay 1 ; 94 C1 2B ; ADI Required Write delay 1 ; 94 31 80 ; ADI Required Write End ; Supported Formats For Script Below - 1920x1080p60, 1920x1080p50, 1280x1024(SXGA)@60, 1600x1200(UXGA)@60 :01-30 HDMI to MIPI TxA CSI 4-Lane - RGB888, Over 600Mbps: E0 FF FF ; SW reset delay 5 ; E0 01 76 ; ADI Required Write E0 05 96 ; Setting Vid_Std to 1600x1200(UXGA)@60 E0 F2 01 ; Enable I2C Read Auto-Increment E0 F3 4C ; DPLL Map Address Set to 0x4C E0 F4 44 ; CP Map Address Set to 0x44 E0 F5 68 ; HDMI RX Map Address Set to 0x68 E0 F6 6C ; EDID Map Address Set to 0x6C E0 F7 64 ; HDMI RX Repeater Map Address Set to 0x64 E0 F8 62 ; HDMI RX Infoframe Map Address Set to 0x62 E0 F9 F0 ; CBUS Map Address Set to 0xF0 E0 FA 82 ; CEC Map Address Set to 0x82 E0 FB F2 ; SDP Main Map Address Set to 0xF2 E0 FC 90 ; CSI-TXB Map Address Set to 0x90 E0 FD 94 ; CSI-TXA Map Address Set to 0x94 E0 00 40 ; Disable chip powerdown & Enable HDMI Rx block 64 40 83 ; Enable HDCP 1.1 68 00 08 ; Foreground Channel = A 68 98 FF ; ADI Required Write 68 99 A3 ; ADI Required Write 68 9A 00 ; ADI Required Write 68 9B 0A ; ADI Required Write 68 9D 40 ; ADI Required Write 68 CB 09 ; ADI Required Write 68 3D 10 ; ADI Required Write 68 3E 7B ; ADI Required Write 68 3F 5E ; ADI Required Write 68 4E FE ; ADI Required Write 68 4F 18 ; ADI Required Write 68 57 A3 ; ADI Required Write 68 58 04 ; ADI Required Write 68 85 10 ; ADI Required Write 68 83 00 ; Enable All Terminations 68 A3 01 ; ADI Required Write 68 BE 00 ; ADI Required Write 68 6C 01 ; HPA Manual Enable 68 F8 01 ; HPA Asserted 68 0F 00 ; Audio Mute Speed Set to Fastest (Smallest Step Size) E0 04 02 ; RGB Out of CP E0 12 F0 ; CSC Depends on ip Packets - SDR 444 E0 17 80 ; Luma & Chroma Values Can Reach 254d E0 03 86 ; CP-Insert_AV_Code 44 7C 00 ; ADI Required Write E0 0C E0 ; Enable LLC_DLL & Double LLC Timing E0 0E DD ; LLC/PIX/SPI PINS TRISTATED AUD Outputs Enabled E0 10 A0 ; Enable 4-lane CSI Tx & Pixel Port 94 00 84 ; Enable 4-lane MIPI 94 00 A4 ; Set Auto DPHY Timing 94 DB 13 ; ADI Required Write 94 D6 07 ; ADI Required Write 94 C4 0A ; ADI Required Write 94 71 33 ; ADI Required Write 94 72 11 ; ADI Required Write 94 F0 00 ; i2c_dphy_pwdn - 1'b0 94 31 82 ; ADI Required Write 94 1E 40 ; ADI Required Write 94 DA 01 ; i2c_mipi_pll_en - 1'b1 delay 2 ; 94 00 24 ; Power-up CSI-TX delay 1 ; 94 C1 2B ; ADI Required Write delay 1 ; 94 31 80 ; ADI Required Write End :01-31 HDMI to Pixel Port - Stereo I2S audio - Pixel repetition - SDR8av Out: E0 FF FF ; SW reset delay 5 ; E0 01 76 ; ADI Required Write E0 F2 01 ; Enable I2C read auto-increment E0 F3 4C ; DPLL Map address set to 0x4C E0 F4 44 ; CP Map address set to 0x44 E0 F5 68 ; HDMI RX Map address set to 0x68 E0 F6 6C ; EDID Map address set to 0x6C E0 F7 64 ; HDMI RX Repeater Map address set to 0x64 E0 F8 62 ; HDMI RX Infoframe Map address set to 0x62 E0 F9 F0 ; CBUS Map address set to 0xF0 E0 FA 82 ; CEC Map address set to 0x82 E0 FB F2 ; SDP Main Map address set to 0xF2 E0 FC 90 ; CSI-TXB Map address set to 0x90 E0 FD 94 ; CSI-TXA Map address set to 0x94 E0 00 40 ; Disable chip powerdown & Enable HDMI Rx block 64 40 83 ; Enable HDCP 1.1 68 00 08 ; Foreground channel = A 68 3D 10 ; ADI Required Write 68 3E 7B ; ADI Required Write 68 3F 5E ; ADI Required Write 68 4E FE ; ADI Required Write 68 4F 18 ; ADI Required Write 68 57 A3 ; ADI Required Write 68 58 04 ; ADI Required Write 68 85 10 ; ADI Required Write 68 41 51 ; Pixel Repetition manually set to 2x for 1440 pixels in, 720 pixels out 68 83 00 ; Enable all terminations 68 98 FF ; ADI Required Write 68 99 A3 ; ADI Required Write 68 9A 00 ; ADI Required Write 68 9B 0A ; ADI Required Write 68 9D 40 ; ADI Required Write 68 CB 09 ; ADI Required Write 68 A3 01 ; ADI Required Write 68 BE 00 ; ADI Required Write 68 0F 00 ; Audio Mute Speed Set to Fastest (Smallest Step Size) 68 6C 01 ; HPA manual mode 68 F8 01 ; HPA asserted 44 3E 08 ; uv_dval_inv [3] = 1'b1 (Pr, Pb timing adjust) E0 03 86 ; Insert AV codes, CP Free run Enable E0 04 40 ; ADI Required Write E0 0E 00 ; Enable LLC, Pixel, SPI and Audio outputs E0 10 20 ; Enable Pixel port and route from CP core E0 12 F4 ; Output is 8-bit SDR 422 E0 0C FF ; llc_dll_en, llc_ddl_mux, LLC_DLL_double = 1'b1 , llc_dll_phase = 5'b11111 (31d) E0 1D 08 ; inv_llc = 1'b0, drv_llc_pad = 2'b10 End :01-32 HDMI to Pixel Port - Stereo I2S audio - SDR8av Out: E0 FF FF ; SW reset delay 5 ; E0 01 76 ; ADI Required Write E0 F2 01 ; Enable I2C read auto-increment E0 F3 4C ; DPLL Map address set to 0x4C E0 F4 44 ; CP Map address set to 0x44 E0 F5 68 ; HDMI RX Map address set to 0x68 E0 F6 6C ; EDID Map address set to 0x6C E0 F7 64 ; HDMI RX Repeater Map address set to 0x64 E0 F8 62 ; HDMI RX Infoframe Map address set to 0x62 E0 F9 F0 ; CBUS Map address set to 0xF0 E0 FA 82 ; CEC Map address set to 0x82 E0 FB F2 ; SDP Main Map address set to 0xF2 E0 FC 90 ; CSI-TXB Map address set to 0x90 E0 FD 94 ; CSI-TXA Map address set to 0x94 E0 00 40 ; Disable chip powerdown & Enable HDMI Rx block 64 40 83 ; enable HDCP 1.1 68 00 08 ; foreground channel = A 68 3D 10 ; ADI Required Write 68 3E 7B ; ADI Required Write 68 3F 5E ; ADI Required Write 68 4E FE ; ADI Required Write 68 4F 18 ; ADI Required Write 68 57 A3 ; ADI Required Write 68 58 04 ; ADI Required Write 68 85 10 ; ADI Required Write 68 83 00 ; Enable all terminations 68 98 FF ; ADI Required Write 68 99 A3 ; ADI Required Write 68 9A 00 ; ADI Required Write 68 9B 0A ; ADI Required Write 68 9D 40 ; ADI Required Write 68 CB 09 ; ADI Required Write 68 A3 01 ; ADI Required Write 68 BE 00 ; ADI Required Write 68 0F 00 ; Audio Mute Speed Set to Fastest (Smallest Step Size) 68 6C 01 ; HPA manual enable 68 F8 01 ; HPA asserted 44 3E 08 ; uv_dval_inv [3] = 1'b1 (Pr, Pb timing adjust) E0 03 86 ; Insert AV codes, CP Free run Enable E0 04 40 ; ADI Required Write E0 0E 00 ; Enable LLC, Pixel, SPI and Audio outputs E0 10 20 ; Enable Pixel port and route from CP core E0 12 F4 ; Output is 8-bit SDR 422 E0 0C FF ; llc_dll_en, llc_ddl_mux, LLC_DLL_double = 1'b1 , llc_dll_phase = 5'b11111 (31d) E0 1D 08 ; inv_llc = 1'b0, drv_llc_pad = 2'b10 End :01-33 HDMI to Pixel Port - TDM audio - SDR8av Out: E0 FF FF ; SW reset delay 5 ; E0 01 76 ; ADI Required Write E0 F2 01 ; Enable I2C read auto-increment E0 F3 4C ; DPLL Map address set to 0x4C E0 F4 44 ; CP Map address set to 0x44 E0 F5 68 ; HDMI RX Map address set to 0x68 E0 F6 6C ; EDID Map address set to 0x6C E0 F7 64 ; HDMI RX Repeater Map address set to 0x64 E0 F8 62 ; HDMI RX Infoframe Map address set to 0x62 E0 F9 F0 ; CBUS Map address set to 0xF0 E0 FA 82 ; CEC Map address set to 0x82 E0 FB F2 ; SDP Main Map address set to 0xF2 E0 FC 90 ; CSI-TXB Map address set to 0x90 E0 FD 94 ; CSI-TXA Map address set to 0x94 E0 00 40 ; Disable chip powerdown & Enable HDMI Rx block 64 40 83 ; enable HDCP 1.1 68 00 08 ; foreground channel = A 68 3D 10 ; ADI Required Write 68 3E 7B ; ADI Required Write 68 3F 5E ; ADI Required Write 68 4E FE ; ADI Required Write 68 4F 18 ; ADI Required Write 68 57 A3 ; ADI Required Write 68 58 04 ; ADI Required Write 68 85 10 ; ADI Required Write 68 83 00 ; Enable all terminations 68 98 FF ; ADI Required Write 68 99 A3 ; ADI Required Write 68 9A 00 ; ADI Required Write 68 9B 0A ; ADI Required Write 68 9D 40 ; ADI Required Write 68 CB 09 ; ADI Required Write 68 A3 01 ; ADI Required Write 68 BE 00 ; ADI Required Write 68 0F C0 ; Audio Mute Speed Set to Fastest (Smallest Step Size) and manually bypass audio delay line 68 6D 80 ; Enable TDM Output Mode 68 6C 01 ; HPA manual mode 68 F8 01 ; HPA asserted 44 3E 08 ; uv_dval_inv [3] = 1'b1 (Pr, Pb timing adjust) E0 03 86 ; Insert AV codes, CP Free run Enable E0 04 40 ; ADI Required Write E0 0E 00 ; Enable LLC, Pixel, SPI and Audio outputs E0 10 20 ; Enable Pixel port and route from CP core E0 12 F4 ; Output is 8-bit SDR 422 4C B5 03 ; MCLK set to 512 Fs E0 0C FF ; llc_dll_en, llc_ddl_mux, LLC_DLL_double = 1'b1 , llc_dll_phase = 5'b11111 (31d) E0 1D 08 ; inv_llc = 1'b0, drv_llc_pad = 2'b10 End :01-34 HDMI to Pixel Port - Stereo I2S audio - DDR8av Out: E0 FF FF ; SW reset delay 5 ; E0 01 76 ; ADI Required Write E0 F2 01 ; Enable I2C read auto-increment E0 F3 4C ; DPLL Map address set to 0x4C E0 F4 44 ; CP Map address set to 0x44 E0 F5 68 ; HDMI RX Map address set to 0x68 E0 F6 6C ; EDID Map address set to 0x6C E0 F7 64 ; HDMI RX Repeater Map address set to 0x64 E0 F8 62 ; HDMI RX Infoframe Map address set to 0x62 E0 F9 F0 ; CBUS Map address set to 0xF0 E0 FA 82 ; CEC Map address set to 0x82 E0 FB F2 ; SDP Main Map address set to 0xF2 E0 FC 90 ; CSI-TXB Map address set to 0x90 E0 FD 94 ; CSI-TXA Map address set to 0x94 E0 00 40 ; Disable chip powerdown & Enable HDMI Rx block 64 40 83 ; enable HDCP 1.1 68 00 08 ; foreground channel = A 68 3D 10 ; ADI Required Write 68 3E 7B ; ADI Required Write 68 3F 5E ; ADI Required Write 68 4E FE ; ADI Required Write 68 4F 18 ; ADI Required Write 68 57 A3 ; ADI Required Write 68 58 04 ; ADI Required Write 68 85 10 ; ADI Required Write 68 83 00 ; Enable all terminations 68 98 FF ; ADI Required Write 68 99 A3 ; ADI Required Write 68 9A 00 ; ADI Required Write 68 9B 0A ; ADI Required Write 68 9D 40 ; ADI Required Write 68 CB 09 ; ADI Required Write 68 A3 01 ; ADI Required Write 68 BE 00 ; ADI Required Write 68 0F 00 ; Audio Mute Speed Set to Fastest (Smallest Step Size) 68 6C 01 ; HPA manual mode 68 F8 01 ; HPA asserted E0 03 86 ; Insert AV codes, CP Free run Enable E0 04 20 ; CP in YPrPb mode E0 0E 00 ; Enable LLC, Pixel, SPI and Audio outputs E0 10 20 ; Enable Pixel port and route from CP core E0 12 F6 ; Output is 8-bit DDR 422 E0 0C BC ; llc_dll_en, llc_ddl_mux = 1'b0, LLC_DLL_double = 1'b0 , llc_dll_phase = 5'b11100 E0 1D 08 ; inv_llc = 1'b0, drv_llc_pad = 2'b10 End ##02 Analog input CVBS## :02-01 Analog CVBS to MIPI TX-B CSI 1-Lane - Autodetect CVBS Single Ended In Ain 1 - MIPI Out: E0 FF FF ; SW reset delay 5 ; E0 01 76 ; ADI Required Write E0 00 30 ; Disable chip powerdown - powerdown Rx E0 F2 01 ; Enable I2C Read Auto-Increment E0 F3 4C ; DPLL Map Address Set to 0x4C E0 F4 44 ; CP Map Address Set to 0x44 E0 F5 68 ; HDMI RX Map Address Set to 0x68 E0 F6 6C ; EDID Map Address Set to 0x6C E0 F7 64 ; HDMI RX Repeater Map Address Set to 0x64 E0 F8 62 ; HDMI RX Infoframe Map Address Set to 0x62 E0 F9 F0 ; CBUS Map Address Set to 0xF0 E0 FA 82 ; CEC Map Address Set to 0x82 E0 FB F2 ; SDP Main Map Address Set to 0xF2 E0 FC 90 ; CSI-TXB Map Address Set to 0x90 E0 FD 94 ; CSI-TXA Map Address Set to 0x94 E0 0E FF ; LLC/PIX/AUD/SPI PINS TRISTATED F2 0F 00 ; Exit Power Down Mode F2 52 CD ; ADI Required Write F2 00 00 ; INSEL = CVBS in on Ain 1 F2 0E 80 ; ADI Required Write F2 9C 00 ; ADI Required Write F2 9C FF ; ADI Required Write F2 0E 00 ; ADI Required Write F2 80 51 ; ADI Required Write F2 81 51 ; ADI Required Write F2 82 68 ; ADI Required Write F2 03 42 ; Tri-S Output Drivers, PwrDwn 656 pads F2 04 07 ; Power-up INTRQ pad, & Enable SFL F2 13 00 ; ADI Required Write F2 17 41 ; Select SH1 F2 31 12 ; ADI Required Write E0 10 70 ; Enable 1-Lane MIPI Tx, enable pixel output and route SD through Pixel port 90 00 81 ; Enable 1-lane MIPI 90 00 A1 ; Set Auto DPHY Timing 94 F0 00 ; ADI Required Write 94 D6 07 ; ADI Required Write 94 C0 3C ; ADI Required Write 94 C3 3C ; ADI Required Write 94 C6 3C ; ADI Required Write 94 C9 3C ; ADI Required Write 94 CC 3C ; ADI Required Write 94 D5 03 ; ADI Required Write 90 D2 40 ; ADI Required Write 90 C4 0A ; ADI Required Write 90 71 33 ; ADI Required Write 90 72 11 ; ADI Required Write 90 F0 00 ; i2c_dphy_pwdn - 1'b0 90 31 82 ; ADI Required Write 90 1E 40 ; ADI Required Write 90 DA 01 ; i2c_mipi_pll_en - 1'b1 delay 2 ; 90 00 21 ; Power-up CSI-TX delay 1 ; 90 C1 2B ; ADI Required Write delay 1 ; 90 31 80 ; ADI Required Write End :02-02 Analog CVBS to MIPI TX-B CSI 1-Lane - Autodetect CVBS Pseudo Diff In, Diff_p,n Ain5,6 - MIPI Out: E0 FF FF ; SW reset delay 5 ; E0 01 76 ; ADI Required Write E0 00 30 ; Disable chip powerdown - powerdown Rx E0 F2 01 ; Enable I2C Read Auto-Increment E0 F3 4C ; DPLL Map Address Set to 0x4C E0 F4 44 ; CP Map Address Set to 0x44 E0 F5 68 ; HDMI RX Map Address Set to 0x68 E0 F6 6C ; EDID Map Address Set to 0x6C E0 F7 64 ; HDMI RX Repeater Map Address Set to 0x64 E0 F8 62 ; HDMI RX Infoframe Map Address Set to 0x62 E0 F9 F0 ; CBUS Map Address Set to 0xF0 E0 FA 82 ; CEC Map Address Set to 0x82 E0 FB F2 ; SDP Main Map Address Set to 0xF2 E0 FC 90 ; CSI-TXB Map Address Set to 0x90 E0 FD 94 ; CSI-TXA Map Address Set to 0x94 E0 1A 19 ; DIAG3 Diagnostic Function - Enable Upper Level Slicer Only and set slice voltage to 975mV E0 0E FF ; LLC/PIX/AUD/SPI PINS TRISTATED F2 0F 00 ; Exit Power Down Mode F2 52 C0 ; ADI Required Write F2 00 10 ; ADI Required Write F2 00 10 ; INSEL = Diff_p in on Ain 5, Diff_n in on Ain6 F2 0E 80 ; ADI Required Write F2 9C 00 ; ADI Required Write F2 9C FF ; ADI Required Write F2 0E 00 ; ADI Required Write F2 5A 90 ; ADI Required Write F2 60 A0 ; ADI Required Write delay 25 ; F2 60 B0 ; ADI Required Write F2 5F A8 ; SHA gain for Div4 F2 0E 80 ; ADI Required Write F2 B6 08 ; ADI Required Write F2 C0 A0 ; ADI Required Write F2 0E 00 ; ADI Required Write F2 80 51 ; ADI Required Write F2 81 51 ; ADI Required Write F2 82 68 ; ADI Required Write F2 03 42 ; Tri-S Output Drivers, PwrDwn 656 pads F2 04 07 ; Power-up INTRQ pad, & Enable SFL F2 13 00 ; ADI Required Write F2 17 41 ; Select SH1 F2 31 12 ; ADI Required Write E0 10 70 ; Enable 1-Lane MIPI Tx, enable pixel output and route SD through Pixel port 90 00 81 ; Enable 1-lane MIPI 90 00 A1 ; Set Auto DPHY Timing 94 F0 00 ; ADI Required Write 94 D6 07 ; ADI Required Write 94 C0 3C ; ADI Required Write 94 C3 3C ; ADI Required Write 94 C6 3C ; ADI Required Write 94 C9 3C ; ADI Required Write 94 CC 3C ; ADI Required Write 94 D5 03 ; ADI Required Write 90 D2 40 ; ADI Required Write 90 C4 0A ; ADI Required Write 90 71 33 ; ADI Required Write 90 72 11 ; ADI Required Write 90 F0 00 ; i2c_dphy_pwdn - 1'b0 90 31 82 ; ADI Required Write 90 1E 40 ; ADI Required Write 90 DA 01 ; i2c_mipi_pll_en - 1'b1 delay 2 ; 90 00 21 ; Power-up CSI-TX delay 1 ; 90 C1 2B ; ADI Required Write delay 1 ; 90 31 80 ; ADI Required Write End :02-03 Analog CVBS to MIPI TX-B CSI 1-Lane - Autodetect CVBS True Diff In, Diff_p,n Ain7,8 - MIPI Out: E0 FF FF ; SW reset delay 5 ; E0 01 76 ; ADI Required Write E0 00 30 ; Disable chip powerdown - powerdown Rx E0 F2 01 ; Enable I2C Read Auto-Increment E0 F3 4C ; DPLL Map Address Set to 0x4C E0 F4 44 ; CP Map Address Set to 0x44 E0 F5 68 ; HDMI RX Map Address Set to 0x68 E0 F6 6C ; EDID Map Address Set to 0x6C E0 F7 64 ; HDMI RX Repeater Map Address Set to 0x64 E0 F8 62 ; HDMI RX Infoframe Map Address Set to 0x62 E0 F9 F0 ; CBUS Map Address Set to 0xF0 E0 FA 82 ; CEC Map Address Set to 0x82 E0 FB F2 ; SDP Main Map Address Set to 0xF2 E0 FC 90 ; CSI-TXB Map Address Set to 0x90 E0 FD 94 ; CSI-TXA Map Address Set to 0x94 E0 1B 19 ; DIAG4 Diagnostic Function - Enable Upper Level Slicer Only and set slice voltage to 975mV E0 0E FF ; LLC/PIX/AUD/SPI PINS TRISTATED F2 0F 00 ; Exit Power Down Mode F2 52 C0 ; ADI Required Write F2 00 10 ; ADI Required Write F2 00 11 ; INSEL = Diff_p in on Ain 7, Diff_n in on Ain8 F2 0E 80 ; ADI Required Write F2 9C 00 ; ADI Required Write F2 9C FF ; ADI Required Write F2 0E 00 ; ADI Required Write F2 5A 90 ; ADI Required Write F2 60 A0 ; ADI Required Write delay 25 ; F2 60 B0 ; ADI Required Write F2 5F A8 ; SHA gain for Div4 F2 0E 80 ; ADI Required Write F2 B6 08 ; ADI Required Write F2 C0 A0 ; ADI Required Write F2 0E 00 ; ADI Required Write F2 80 51 ; ADI Required Write F2 81 51 ; ADI Required Write F2 82 68 ; ADI Required Write F2 03 42 ; Tri-S Output Drivers, PwrDwn 656 pads F2 04 07 ; Power-up INTRQ pad, & Enable SFL F2 13 00 ; ADI Required Write F2 17 41 ; Select SH1 F2 31 12 ; ADI Required Write E0 10 70 ; Enable 1-Lane MIPI Tx, enable pixel output and route SD through Pixel port 90 00 81 ; Enable 1-lane MIPI 90 00 A1 ; Set Auto DPHY Timing 94 F0 00 ; ADI Required Write 94 D6 07 ; ADI Required Write 94 C0 3C ; ADI Required Write 94 C3 3C ; ADI Required Write 94 C6 3C ; ADI Required Write 94 C9 3C ; ADI Required Write 94 CC 3C ; ADI Required Write 94 D5 03 ; ADI Required Write 90 D2 40 ; ADI Required Write 90 C4 0A ; ADI Required Write 90 71 33 ; ADI Required Write 90 72 11 ; ADI Required Write 90 F0 00 ; i2c_dphy_pwdn - 1'b0 90 31 82 ; ADI Required Write 90 1E 40 ; ADI Required Write 90 DA 01 ; i2c_mipi_pll_en - 1'b1 delay 2 ; 90 00 21 ; Power-up CSI-TX delay 1 ; 90 C1 2B ; ADI Required Write delay 1 ; 90 31 80 ; ADI Required Write End :02-04 Analog CVBS to Pixel Port - Autodetect CVBS Single Ended In Ain 1 - SDR8av Out: E0 FF FF ; SW reset delay 5 ; E0 01 76 ; ADI Required Write E0 00 30 ; Disable chip powerdown - powerdown Rx E0 F2 01 ; Enable I2C read auto-increment E0 F3 4C ; DPLL Map address set to 0x4C E0 F4 44 ; CP Map address set to 0x44 E0 F5 68 ; HDMI RX Map address set to 0x68 E0 F6 6C ; EDID Map address set to 0x6C E0 F7 64 ; HDMI RX Repeater Map address set to 0x64 E0 F8 62 ; HDMI RX Infoframe Map address set to 0x62 E0 F9 F0 ; CBUS Map address set to 0xF0 E0 FA 82 ; CEC Map address set to 0x82 E0 FB F2 ; SDP Main Map address set to 0xF2 E0 FC 90 ; CSI-TXB Map address set to 0x90 E0 FD 94 ; CSI-TXA Map address set to 0x94 E0 0E 33 ; untristae & power up LLC & pixel pins E0 10 30 ; Enable pixel output and route SD through Pixel port F2 0F 00 ; Exit Power Down Mode F2 52 CD ; ADI Required Write F2 00 00 ; INSEL = CVBS in on Ain 1 F2 0E 80 ; ADI Required Write F2 9C 00 ; ADI Required Write F2 9C FF ; ADI Required Write F2 0E 00 ; ADI Required Write F2 80 51 ; ADI Required Write F2 81 51 ; ADI Required Write F2 82 68 ; ADI Required Write F2 03 0C ; Enable Pixel & Sync output drivers F2 04 07 ; ADI Required Write F2 13 00 ; ADI Required Write F2 17 41 ; select SH1 F2 31 12 ; ADI Required Write End :02-05 Analog CVBS to Pixel Port - Autodetect CVBS Pseudo Diff In, Diff_p,n Ain5,6 - SDR8av Out: E0 FF FF ; SW reset delay 5 ; E0 01 76 ; ADI Required Write E0 00 30 ; Disable chip powerdown - powerdown Rx E0 F2 01 ; Enable I2C Read Auto-Increment E0 F3 4C ; DPLL Map Address Set to 0x4C E0 F4 44 ; CP Map Address Set to 0x44 E0 F5 68 ; HDMI RX Map Address Set to 0x68 E0 F6 6C ; EDID Map Address Set to 0x6C E0 F7 64 ; HDMI RX Repeater Map Address Set to 0x64 E0 F8 62 ; HDMI RX Infoframe Map Address Set to 0x62 E0 F9 F0 ; CBUS Map Address Set to 0xF0 E0 FA 82 ; CEC Map Address Set to 0x82 E0 FB F2 ; SDP Main Map Address Set to 0xF2 E0 FC 90 ; CSI-TXB Map Address Set to 0x90 E0 FD 94 ; CSI-TXA Map Address Set to 0x94 E0 0E 33 ; untristae & power up LLC & pixel pins E0 10 30 ; Enable pixel output and route SD through Pixel port E0 1A 19 ; DIAG3 Diagnostic Function - Enable Upper Level Slicer Only and set slice voltage to 975mV F2 0F 00 ; Exit Power Down Mode F2 52 C0 ; ADI Required Write F2 00 10 ; ADI Required Write F2 00 10 ; INSEL = Diff_p in on Ain 5, Diff_n in on Ain6 F2 0E 80 ; ADI Required Write F2 9C 00 ; ADI Required Write F2 9C FF ; ADI Required Write F2 0E 00 ; ADI Required Write F2 5A 90 ; ADI Required Write F2 60 A0 ; ADI Required Write delay 25 ; F2 60 B0 ; ADI Required Write F2 5F A8 ; SHA gain for Div4 F2 0E 80 ; ADI Required Write F2 B6 08 ; ADI Required Write F2 C0 A0 ; ADI Required Write F2 0E 00 ; ADI Required Write F2 80 51 ; ADI Required Write F2 81 51 ; ADI Required Write F2 82 68 ; ADI Required Write F2 03 0C ; Enable Pixel & Sync output drivers F2 04 07 ; Power-up INTRQ pad, & Enable SFL F2 13 00 ; ADI Required Write F2 17 41 ; Select SH1 F2 31 12 ; ADI Required Write End :02-06 Analog CVBS to Pixel Port - Autodetect CVBS True Differential In Ain7,8 - SDR8av Out: E0 FF FF ; SW reset delay 5 ; E0 01 76 ; ADI Required Write E0 00 30 ; Disable chip powerdown - powerdown Rx E0 F2 01 ; ADI Required Write E0 F3 4C ; DPLL Map address set to 0x4C E0 F4 44 ; CP Map address set to 0x44 E0 F5 68 ; HDMI RX Map address set to 0x68 E0 F6 6C ; EDID Map address set to 0x6C E0 F7 64 ; HDMI RX Repeater Map address set to 0x64 E0 F8 62 ; HDMI RX Infoframe Map address set to 0x62 E0 F9 F0 ; CBUS Map address set to 0xF0 E0 FA 82 ; CEC Map address set to 0x82 E0 FB F2 ; SDP Main Map address set to 0xF2 E0 FC 90 ; CSI-TXB Map address set to 0x90 E0 FD 94 ; CSI-TXA Map address set to 0x94 E0 F2 03 ; ADI Required Write E0 0E 33 ; untristae & power up LLC & pixel pins E0 10 30 ; Enable pixel output and route SD through Pixel port E0 1B 19 ; DIAG4 Diagnostic Function - Enable Upper Level Slicer Only and set slice voltage to 975mV F2 0F 00 ; Exit Power Down Mode F2 52 C0 ; ADI Required Write F2 00 10 ; ADI Required Write F2 00 11 ; INSEL = CVBS_P in on Ain 7, CVBS_N in on Ain8 F2 0E 80 ; ADI Required Write F2 9C 00 ; ADI Required Write F2 9C FF ; ADI Required Write F2 0E 00 ; ADI Required Write F2 5A 90 ; ADI Required Write F2 60 A0 ; ADI Required Write delay 25 ; F2 60 B0 ; ADI Required Write F2 5F A8 ; ADI Required Write F2 0E 80 ; ADI Required Write F2 B6 08 ; ADI Required Write F2 C0 A0 ; ADI Required Write F2 0E 00 ; ADI Required Write F2 80 51 ; ADI Required Write F2 81 51 ; ADI Required Write F2 82 68 ; ADI Required Write F2 03 0C ; Enable Pixel & Sync output drivers F2 04 07 ; ADI Required Write F2 13 00 ; ADI Required Write F2 17 41 ; select SH1 F2 31 12 ; ADI Required Write End ##03 Analog input YC## :03-01 Analog YC to MIPI TX-B CSI 1-Lane - Autodetect YC Ain 1,2 - MIPI Out: E0 FF FF ; SW reset delay 5 ; E0 01 76 ; ADI Required Write E0 00 30 ; Disable chip powerdown - powerdown Rx E0 F2 01 ; Enable I2C Read Auto-Increment E0 F3 4C ; DPLL Map Address Set to 0x4C E0 F4 44 ; CP Map Address Set to 0x44 E0 F5 68 ; HDMI RX Map Address Set to 0x68 E0 F6 6C ; EDID Map Address Set to 0x6C E0 F7 64 ; HDMI RX Repeater Map Address Set to 0x64 E0 F8 62 ; HDMI RX Infoframe Map Address Set to 0x62 E0 F9 F0 ; CBUS Map Address Set to 0xF0 E0 FA 82 ; CEC Map Address Set to 0x82 E0 FB F2 ; SDP Main Map Address Set to 0xF2 E0 FC 90 ; CSI-TXB Map Address Set to 0x90 E0 FD 94 ; CSI-TXA Map Address Set to 0x94 E0 0E FF ; LLC/PIX/AUD/SPI PINS TRISTATED F2 0F 00 ; Exit Power Down Mode F2 53 CE ; ADI Required Write F2 00 08 ; INSEL = YC, Y=Ain1, C=Ain2 F2 0E 80 ; ADI Required Write F2 9C 00 ; ADI Required Write F2 9C FF ; ADI Required Write F2 0E 00 ; ADI Required Write F2 80 51 ; ADI Required Write F2 81 51 ; ADI Required Write F2 82 68 ; ADI Required Write F2 03 42 ; Tri-S Output Drivers, PwrDwn 656 pads F2 04 07 ; Power-up INTRQ pad, & Enable SFL F2 13 00 ; ADI Required Write F2 31 12 ; ADI Required Write E0 10 70 ; Enable 1-Lane MIPI Tx, enable pixel output and route SD through Pixel port 90 00 81 ; Enable 1-lane MIPI 90 00 A1 ; Set Auto DPHY Timing 94 F0 00 ; ADI Required Write 94 D6 07 ; ADI Required Write 94 C0 3C ; ADI Required Write 94 C3 3C ; ADI Required Write 94 C6 3C ; ADI Required Write 94 C9 3C ; ADI Required Write 94 CC 3C ; ADI Required Write 94 D5 03 ; ADI Required Write 90 D2 40 ; ADI Required Write 90 C4 0A ; ADI Required Write 90 71 33 ; ADI Required Write 90 72 11 ; ADI Required Write 90 F0 00 ; i2c_dphy_pwdn - 1'b0 90 31 82 ; ADI Required Write 90 1E 40 ; ADI Required Write 90 DA 01 ; i2c_mipi_pll_en - 1'b1 delay 2 ; 90 00 21 ; Power-up CSI-TX delay 1 ; 90 C1 2B ; ADI Required Write delay 1 ; 90 31 80 ; ADI Required Write End :03-02 Analog YC to Pixel Port - Autodetect YC In Ain1,2 - SDR8av Out: E0 FF FF ; SW reset delay 5 ; E0 01 76 ; ADI Required Write E0 00 30 ; Disable chip powerdown - powerdown Rx E0 F2 01 ; Enable I2C read auto-increment E0 F3 4C ; DPLL Map address set to 0x4C E0 F4 44 ; CP Map address set to 0x44 E0 F5 68 ; HDMI RX Map address set to 0x68 E0 F6 6C ; EDID Map address set to 0x6C E0 F7 64 ; HDMI RX Repeater Map address set to 0x64 E0 F8 62 ; HDMI RX Infoframe Map address set to 0x62 E0 F9 F0 ; CBUS Map address set to 0xF0 E0 FA 82 ; CEC Map address set to 0x82 E0 FB F2 ; SDP Main Map address set to 0xF2 E0 FC 90 ; CSI-TXB Map address set to 0x90 E0 FD 94 ; CSI-TXA Map address set to 0x94 E0 0E 33 ; untristae & power up LLC & pixel pins E0 10 30 ; Enable pixel output and route SD through Pixel port F2 0F 00 ; Exit Power Down Mode F2 53 CE ; ADI Required Write F2 00 08 ; Insel=YC1, y=Ain1, C=Ain2 F2 0E 80 ; ADI Required Write F2 9C 00 ; ADI Required Write F2 9C FF ; ADI Required Write F2 0E 00 ; ADI Required Write F2 80 51 ; ADI Required Write F2 81 51 ; ADI Required Write F2 82 68 ; ADI Required Write F2 03 0C ; Enable Pixel & Sync output drivers F2 04 07 ; ADI Required Write F2 13 00 ; ADI Required Write F2 31 12 ; ADI Required Write End ##04 Analog input YPrPb## :04-01 Analog YPrPb to MIPI TX-B CSI 1-Lane - Autodetect YPrPb In, Ain 1,2,3 - MIPI Out: E0 FF FF ; SW reset delay 5 ; E0 01 76 ; ADI Required Write E0 00 30 ; Disable chip powerdown - powerdown Rx E0 F2 01 ; Enable I2C Read Auto-Increment E0 F3 4C ; DPLL Map Address Set to 0x4C E0 F4 44 ; CP Map Address Set to 0x44 E0 F5 68 ; HDMI RX Map Address Set to 0x68 E0 F6 6C ; EDID Map Address Set to 0x6C E0 F7 64 ; HDMI RX Repeater Map Address Set to 0x64 E0 F8 62 ; HDMI RX Infoframe Map Address Set to 0x62 E0 F9 F0 ; CBUS Map Address Set to 0xF0 E0 FA 82 ; CEC Map Address Set to 0x82 E0 FB F2 ; SDP Main Map Address Set to 0xF2 E0 FC 90 ; CSI-TXB Map Address Set to 0x90 E0 FD 94 ; CSI-TXA Map Address Set to 0x94 E0 0E FF ; LLC/PIX/AUD/SPI PINS TRISTATED F2 0F 00 ; Exit Power Down Mode F2 54 C0 ; ADI Required Write F2 00 0C ; INSEL = YPbPr, Y=Ain1, Pb=Ain2, Pr=Ain3 F2 0E 80 ; ADI Required Write F2 9C 00 ; ADI Required Write F2 9C FF ; ADI Required Write F2 0E 00 ; ADI Required Write F2 80 51 ; ADI Required Write F2 81 51 ; ADI Required Write F2 82 68 ; ADI Required Write F2 03 42 ; Tri-S Output Drivers, PwrDwn 656 pads F2 04 07 ; Power-up INTRQ pad, & Enable SFL F2 13 00 ; ADI Required Write F2 31 12 ; ADI Required Write E0 10 70 ; Enable 1-Lane MIPI Tx, enable pixel output and route SD through Pixel port 90 00 81 ; Enable 1-lane MIPI 90 00 A1 ; Set Auto DPHY Timing 94 F0 00 ; ADI Required Write 94 D6 07 ; ADI Required Write 94 C0 3C ; ADI Required Write 94 C3 3C ; ADI Required Write 94 C6 3C ; ADI Required Write 94 C9 3C ; ADI Required Write 94 CC 3C ; ADI Required Write 94 D5 03 ; ADI Required Write 90 D2 40 ; ADI Required Write 90 C4 0A ; ADI Required Write 90 71 33 ; ADI Required Write 90 72 11 ; ADI Required Write 90 F0 00 ; i2c_dphy_pwdn - 1'b0 90 31 82 ; ADI Required Write 90 1E 40 ; ADI Required Write 90 DA 01 ; i2c_mipi_pll_en - 1'b1 delay 2 ; 90 00 21 ; Power-up CSI-TX delay 1 ; 90 C1 2B ; ADI Required Write delay 1 ; 90 31 80 ; ADI Required Write End :04-02 Analog YPrPb to Pixel Port - Autodetect YPrPb In Ain1,2,3 - SDR8av Out: E0 FF FF ; SW reset delay 5 ; E0 01 76 ; ADI Required Write E0 00 30 ; Disable chip powerdown - powerdown Rx E0 F2 01 ; Enable I2C read auto-increment E0 F3 4C ; DPLL Map address set to 0x4C E0 F4 44 ; CP Map address set to 0x44 E0 F5 68 ; HDMI RX Map address set to 0x68 E0 F6 6C ; EDID Map address set to 0x6C E0 F7 64 ; HDMI RX Repeater Map address set to 0x64 E0 F8 62 ; HDMI RX Infoframe Map address set to 0x62 E0 F9 F0 ; CBUS Map address set to 0xF0 E0 FA 82 ; CEC Map address set to 0x82 E0 FB F2 ; SDP Main Map address set to 0xF2 E0 FC 90 ; CSI-TXB Map address set to 0x90 E0 FD 94 ; CSI-TXA Map address set to 0x94 E0 0E 33 ; untristae & power up LLC & pixel pins E0 10 30 ; Enable pixel output and route SD through Pixel port F2 0F 00 ; Exit Power Down Mode F2 54 C0 ; ADI Required Write F2 00 0C ; INSEL = YPrPb-1, Y=Ain1, Pr=Ain2, Pb=Ain3 F2 0E 80 ; ADI Required Write F2 9C 00 ; ADI Required Write F2 9C FF ; ADI Required Write F2 0E 00 ; ADI Required Write F2 80 51 ; ADI Required Write F2 81 51 ; ADI Required Write F2 82 68 ; ADI Required Write F2 03 0C ; Enable Pixel & Sync output drivers F2 04 07 ; ADI Required Write F2 13 00 ; ADI Required Write F2 31 12 ; ADI Required Write End ##05 Analog Input Fast Switch CVBS Scripts## :05-01 FS Analog CVBS to MIPI TX-B CSI 1-Lane - Autodetect CVBS Single Ended In Ain 1 - MIPI Out: E0 FF FF ; SW reset delay 5 ; E0 01 76 ; ADI Required Write E0 00 30 ; Disable chip powerdown - powerdown Rx E0 F2 01 ; Enable I2C Read Auto-Increment E0 F3 4C ; DPLL Map Address Set to 0x4C E0 F4 44 ; CP Map Address Set to 0x44 E0 F5 68 ; HDMI RX Map Address Set to 0x68 E0 F6 6C ; EDID Map Address Set to 0x6C E0 F7 64 ; HDMI RX Repeater Map Address Set to 0x64 E0 F8 62 ; HDMI RX Infoframe Map Address Set to 0x62 E0 F9 F0 ; CBUS Map Address Set to 0xF0 E0 FA 82 ; CEC Map Address Set to 0x82 E0 FB F2 ; SDP Main Map Address Set to 0xF2 E0 FC 90 ; CSI-TXB Map Address Set to 0x90 E0 FD 94 ; CSI-TXA Map Address Set to 0x94 E0 0E FF ; LLC/PIX/AUD/SPI PINS TRISTATED F2 0F 00 ; Exit Power Down Mode F2 52 CD ; ADI Required Write F2 00 00 ; INSEL = CVBS in on Ain 1 F2 0E 80 ; ADI Required Write F2 9C 00 ; ADI Required Write F2 9C FF ; ADI Required Write F2 0E 00 ; ADI Required Write F2 80 51 ; ADI Required Write F2 81 51 ; ADI Required Write F2 82 68 ; ADI Required Write F2 0E 80 ; ADI Required Write F2 D9 44 ; ADI Required Write F2 0E 40 ; Select User Sub Map 2 F2 E0 01 ; Select fast Switching Mode F2 0E 00 ; ADI Required Write F2 03 42 ; Tri-S Output Drivers, PwrDwn 656 pads F2 04 07 ; Power-up INTRQ pad, & Enable SFL F2 13 00 ; ADI Required Write F2 17 41 ; Select SH1 F2 31 12 ; ADI Required Write E0 10 70 ; Enable 1-Lane MIPI Tx, enable pixel output and route SD through Pixel port 90 00 81 ; Enable 1-lane MIPI 90 00 A1 ; Set Auto DPHY Timing 94 F0 00 ; ADI Required Write 94 D6 07 ; ADI Required Write 94 C0 3C ; ADI Required Write 94 C3 3C ; ADI Required Write 94 C6 3C ; ADI Required Write 94 C9 3C ; ADI Required Write 94 CC 3C ; ADI Required Write 94 D5 03 ; ADI Required Write 90 D2 40 ; ADI Required Write 90 C4 0A ; ADI Required Write 90 71 33 ; ADI Required Write 90 72 11 ; ADI Required Write 90 F0 00 ; i2c_dphy_pwdn - 1'b0 90 31 82 ; ADI Required Write 90 1E 40 ; ADI Required Write 90 DA 01 ; i2c_mipi_pll_en - 1'b1 delay 2 ; 90 00 21 ; Power-up CSI-TX delay 1 ; 90 C1 2B ; ADI Required Write delay 1 ; 90 31 80 ; ADI Required Write End :05-02 FS Analog CVBS to MIPI TX-B CSI 1-Lane - Autodetect CVBS Pseudo Diff In, Diff_p,n Ain5,6 - MIPI Out: E0 FF FF ; SW reset delay 5 ; E0 01 76 ; ADI Required Write E0 00 30 ; Disable chip powerdown - powerdown Rx E0 F2 01 ; Enable I2C Read Auto-Increment E0 F3 4C ; DPLL Map Address Set to 0x4C E0 F4 44 ; CP Map Address Set to 0x44 E0 F5 68 ; HDMI RX Map Address Set to 0x68 E0 F6 6C ; EDID Map Address Set to 0x6C E0 F7 64 ; HDMI RX Repeater Map Address Set to 0x64 E0 F8 62 ; HDMI RX Infoframe Map Address Set to 0x62 E0 F9 F0 ; CBUS Map Address Set to 0xF0 E0 FA 82 ; CEC Map Address Set to 0x82 E0 FB F2 ; SDP Main Map Address Set to 0xF2 E0 FC 90 ; CSI-TXB Map Address Set to 0x90 E0 FD 94 ; CSI-TXA Map Address Set to 0x94 E0 1A 19 ; DIAG3 Diagnostic Function - Enable Upper Level Slicer Only and set slice voltage to 975mV E0 0E FF ; LLC/PIX/AUD/SPI PINS TRISTATED F2 0F 00 ; Exit Power Down Mode F2 52 C0 ; ADI Required Write F2 00 10 ; ADI Required Write F2 00 10 ; INSEL = Diff_p in on Ain 5, Diff_n in on Ain6 F2 0E 80 ; ADI Required Write F2 9C 00 ; ADI Required Write F2 9C FF ; ADI Required Write F2 0E 00 ; ADI Required Write F2 5A 90 ; ADI Required Write F2 60 A0 ; ADI Required Write delay 25 ; F2 60 B0 ; ADI Required Write F2 5F A8 ; SHA gain for Div4 F2 0E 80 ; ADI Required Write F2 B6 08 ; ADI Required Write F2 C0 A0 ; ADI Required Write F2 D9 44 ; ADI Required Write F2 0E 40 ; Select User Sub Map 2 F2 E0 01 ; Select fast Switching Mode F2 0E 00 ; ADI Required Write F2 80 51 ; ADI Required Write F2 81 51 ; ADI Required Write F2 82 68 ; ADI Required Write F2 03 42 ; Tri-S Output Drivers, PwrDwn 656 pads F2 04 07 ; Power-up INTRQ pad, & Enable SFL F2 13 00 ; ADI Required Write F2 17 41 ; Select SH1 F2 31 12 ; ADI Required Write E0 10 70 ; Enable 1-Lane MIPI Tx, enable pixel output and route SD through Pixel port 90 00 81 ; Enable 1-lane MIPI 90 00 A1 ; Set Auto DPHY Timing 94 F0 00 ; ADI Required Write 94 D6 07 ; ADI Required Write 94 C0 3C ; ADI Required Write 94 C3 3C ; ADI Required Write 94 C6 3C ; ADI Required Write 94 C9 3C ; ADI Required Write 94 CC 3C ; ADI Required Write 94 D5 03 ; ADI Required Write 90 D2 40 ; ADI Required Write 90 C4 0A ; ADI Required Write 90 71 33 ; ADI Required Write 90 72 11 ; ADI Required Write 90 F0 00 ; i2c_dphy_pwdn - 1'b0 90 31 82 ; ADI Required Write 90 1E 40 ; ADI Required Write 90 DA 01 ; i2c_mipi_pll_en - 1'b1 delay 2 ; 90 00 21 ; Power-up CSI-TX delay 1 ; 90 C1 2B ; ADI Required Write delay 1 ; 90 31 80 ; ADI Required Write End :05-03 FS Analog CVBS to MIPI TX-B CSI 1-Lane - Autodetect CVBS True Diff In, Diff_p,n Ain7,8 - MIPI Out: E0 FF FF ; SW reset delay 5 ; E0 01 76 ; ADI Required Write E0 00 30 ; Disable chip powerdown - powerdown Rx E0 F2 01 ; Enable I2C Read Auto-Increment E0 F3 4C ; DPLL Map Address Set to 0x4C E0 F4 44 ; CP Map Address Set to 0x44 E0 F5 68 ; HDMI RX Map Address Set to 0x68 E0 F6 6C ; EDID Map Address Set to 0x6C E0 F7 64 ; HDMI RX Repeater Map Address Set to 0x64 E0 F8 62 ; HDMI RX Infoframe Map Address Set to 0x62 E0 F9 F0 ; CBUS Map Address Set to 0xF0 E0 FA 82 ; CEC Map Address Set to 0x82 E0 FB F2 ; SDP Main Map Address Set to 0xF2 E0 FC 90 ; CSI-TXB Map Address Set to 0x90 E0 FD 94 ; CSI-TXA Map Address Set to 0x94 E0 1B 19 ; DIAG4 Diagnostic Function - Enable Upper Level Slicer Only and set slice voltage to 975mV E0 0E FF ; LLC/PIX/AUD/SPI PINS TRISTATED F2 0F 00 ; Exit Power Down Mode F2 52 C0 ; ADI Required Write F2 00 10 ; ADI Required Write F2 00 11 ; INSEL = Diff_p in on Ain 7, Diff_n in on Ain8 F2 0E 80 ; ADI Required Write F2 9C 00 ; ADI Required Write F2 9C FF ; ADI Required Write F2 0E 00 ; ADI Required Write F2 5A 90 ; ADI Required Write F2 60 A0 ; ADI Required Write delay 25 ; F2 60 B0 ; ADI Required Write F2 5F A8 ; SHA gain for Div4 F2 0E 80 ; ADI Required Write F2 B6 08 ; ADI Required Write F2 C0 A0 ; ADI Required Write F2 D9 44 ; ADI Required Write F2 0E 40 ; Select User Sub Map 2 F2 E0 01 ; Select fast Switching Mode F2 0E 00 ; ADI Required Write F2 80 51 ; ADI Required Write F2 81 51 ; ADI Required Write F2 82 68 ; ADI Required Write F2 03 42 ; Tri-S Output Drivers, PwrDwn 656 pads F2 04 07 ; Power-up INTRQ pad, & Enable SFL F2 13 00 ; ADI Required Write F2 17 41 ; Select SH1 F2 31 12 ; ADI Required Write E0 10 70 ; Enable 1-Lane MIPI Tx, enable pixel output and route SD through Pixel port 90 00 81 ; Enable 1-lane MIPI 90 00 A1 ; Set Auto DPHY Timing 94 F0 00 ; ADI Required Write 94 D6 07 ; ADI Required Write 94 C0 3C ; ADI Required Write 94 C3 3C ; ADI Required Write 94 C6 3C ; ADI Required Write 94 C9 3C ; ADI Required Write 94 CC 3C ; ADI Required Write 94 D5 03 ; ADI Required Write 90 D2 40 ; ADI Required Write 90 C4 0A ; ADI Required Write 90 71 33 ; ADI Required Write 90 72 11 ; ADI Required Write 90 F0 00 ; i2c_dphy_pwdn - 1'b0 90 31 82 ; ADI Required Write 90 1E 40 ; ADI Required Write 90 DA 01 ; i2c_mipi_pll_en - 1'b1 delay 2 ; 90 00 21 ; Power-up CSI-TX delay 1 ; 90 C1 2B ; ADI Required Write delay 1 ; 90 31 80 ; ADI Required Write End :05-04 FS Analog CVBS to Pixel Port - Autodetect CVBS Single Ended In Ain 1 - SDR8av Out: E0 FF FF ; SW reset delay 5 ; E0 01 76 ; ADI Required Write E0 00 30 ; Disable chip powerdown - powerdown Rx E0 F2 01 ; Enable I2C Read Auto-Increment E0 F3 4C ; DPLL Map Address Set to 0x4C E0 F4 44 ; CP Map Address Set to 0x44 E0 F5 68 ; HDMI RX Map Address Set to 0x68 E0 F6 6C ; EDID Map Address Set to 0x6C E0 F7 64 ; HDMI RX Repeater Map Address Set to 0x64 E0 F8 62 ; HDMI RX Infoframe Map Address Set to 0x62 E0 F9 F0 ; CBUS Map Address Set to 0xF0 E0 FA 82 ; CEC Map Address Set to 0x82 E0 FB F2 ; SDP Main Map Address Set to 0xF2 E0 FC 90 ; CSI-TXB Map Address Set to 0x90 E0 FD 94 ; CSI-TXA Map Address Set to 0x94 E0 0E 33 ; untristae & power up LLC & pixel pins E0 10 30 ; Enable pixel output and route SD through Pixel port F2 0F 00 ; Exit Power Down Mode F2 52 CD ; ADI Required Write F2 00 00 ; INSEL = CVBS in on Ain 1 F2 0E 80 ; ADI Required Write F2 9C 00 ; ADI Required Write F2 9C FF ; ADI Required Write F2 0E 00 ; ADI Required Write F2 80 51 ; ADI Required Write F2 81 51 ; ADI Required Write F2 82 68 ; ADI Required Write F2 0E 80 ; ADI Required Write F2 D9 44 ; ADI Required Write F2 0E 40 ; Select User Sub Map 2 F2 E0 01 ; Select fast Switching Mode F2 0E 00 ; ADI Required Write F2 03 0C ; Enable Pixel & Sync output drivers F2 04 07 ; ADI Required Write F2 13 00 ; ADI Required Write F2 17 41 ; select SH1 F2 31 12 ; ADI Required Write End :05-05 FS Analog CVBS to Pixel Port - Autodetect CVBS Pseudo Diff In, Diff_p,n Ain5,6 - SDR8av Out: E0 FF FF ; SW reset delay 5 ; E0 01 76 ; ADI Required Write E0 00 30 ; Disable chip powerdown - powerdown Rx E0 F2 01 ; Enable I2C Read Auto-Increment E0 F3 4C ; DPLL Map Address Set to 0x4C E0 F4 44 ; CP Map Address Set to 0x44 E0 F5 68 ; HDMI RX Map Address Set to 0x68 E0 F6 6C ; EDID Map Address Set to 0x6C E0 F7 64 ; HDMI RX Repeater Map Address Set to 0x64 E0 F8 62 ; HDMI RX Infoframe Map Address Set to 0x62 E0 F9 F0 ; CBUS Map Address Set to 0xF0 E0 FA 82 ; CEC Map Address Set to 0x82 E0 FB F2 ; SDP Main Map Address Set to 0xF2 E0 FC 90 ; CSI-TXB Map Address Set to 0x90 E0 FD 94 ; CSI-TXA Map Address Set to 0x94 E0 1A 19 ; DIAG3 Diagnostic Function - Enable Upper Level Slicer Only and set slice voltage to 975mV E0 0E 33 ; untristae & power up LLC & pixel pins E0 10 30 ; Enable pixel output and route SD through Pixel port F2 0F 00 ; Exit Power Down Mode F2 52 C0 ; ADI Required Write F2 00 10 ; ADI Required Write F2 00 10 ; INSEL = Diff_p in on Ain 5, Diff_n in on Ain6 F2 0E 80 ; ADI Required Write F2 9C 00 ; ADI Required Write F2 9C FF ; ADI Required Write F2 0E 00 ; ADI Required Write F2 5A 90 ; ADI Required Write F2 60 A0 ; ADI Required Write delay 25 ; F2 60 B0 ; ADI Required Write F2 5F A8 ; SHA gain for Div4 F2 0E 80 ; ADI Required Write F2 B6 08 ; ADI Required Write F2 C0 A0 ; ADI Required Write F2 D9 44 ; ADI Required Write F2 0E 40 ; Select User Sub Map 2 F2 E0 01 ; Select fast Switching Mode F2 0E 00 ; ADI Required Write F2 80 51 ; ADI Required Write F2 81 51 ; ADI Required Write F2 82 68 ; ADI Required Write F2 03 0C ; Enable Pixel & Sync output drivers F2 04 07 ; Power-up INTRQ pad, & Enable SFL F2 13 00 ; ADI Required Write F2 17 41 ; Select SH1 F2 31 12 ; ADI Required Write End :05-06 FS Analog CVBS to Pixel Port - Autodetect CVBS True Diff In, Diff_p,n Ain7,8 - SDR8av Out: E0 FF FF ; SW reset delay 5 ; E0 01 76 ; ADI Required Write E0 00 30 ; Disable chip powerdown - powerdown Rx E0 F2 01 ; Enable I2C Read Auto-Increment E0 F3 4C ; DPLL Map Address Set to 0x4C E0 F4 44 ; CP Map Address Set to 0x44 E0 F5 68 ; HDMI RX Map Address Set to 0x68 E0 F6 6C ; EDID Map Address Set to 0x6C E0 F7 64 ; HDMI RX Repeater Map Address Set to 0x64 E0 F8 62 ; HDMI RX Infoframe Map Address Set to 0x62 E0 F9 F0 ; CBUS Map Address Set to 0xF0 E0 FA 82 ; CEC Map Address Set to 0x82 E0 FB F2 ; SDP Main Map Address Set to 0xF2 E0 FC 90 ; CSI-TXB Map Address Set to 0x90 E0 FD 94 ; CSI-TXA Map Address Set to 0x94 E0 1B 19 ; DIAG4 Diagnostic Function - Enable Upper Level Slicer Only and set slice voltage to 975mV E0 0E 33 ; untristae & power up LLC & pixel pins E0 10 30 ; Enable pixel output and route SD through Pixel port F2 0F 00 ; Exit Power Down Mode F2 52 C0 ; ADI Required Write F2 00 10 ; ADI Required Write F2 00 11 ; INSEL = Diff_p in on Ain 7, Diff_n in on Ain8 F2 0E 80 ; ADI Required Write F2 9C 00 ; ADI Required Write F2 9C FF ; ADI Required Write F2 0E 00 ; ADI Required Write F2 5A 90 ; ADI Required Write F2 60 A0 ; ADI Required Write delay 25 ; F2 60 B0 ; ADI Required Write F2 5F A8 ; SHA gain for Div4 F2 0E 80 ; ADI Required Write F2 B6 08 ; ADI Required Write F2 C0 A0 ; ADI Required Write F2 D9 44 ; ADI Required Write F2 0E 40 ; Select User Sub Map 2 F2 E0 01 ; Select fast Switching Mode F2 0E 00 ; ADI Required Write F2 80 51 ; ADI Required Write F2 81 51 ; ADI Required Write F2 82 68 ; ADI Required Write F2 03 0C ; Enable Pixel & Sync output drivers F2 04 07 ; ADI Required Write F2 13 00 ; ADI Required Write F2 17 41 ; select SH1 F2 31 12 ; ADI Required Write End ##06 TTL Input Scripts - 8-Bit_SDR - MIPI Output## :06-01 8-Bit SDR TTL to MIPI TX-A CSI 1-Lane - 480i,576i,480p,576p - YUV422 8-Bit: E0 FF FF ; SW reset delay 5 ; E0 01 76 ; ADI Required Write E0 05 4A ; Setting Vid_Std to 720x480p60 E0 00 30 ; Disable chip powerdown - powerdown Rx E0 F2 01 ; Enable I2C Read Auto-Increment E0 F3 4C ; DPLL Map Address Set to 0x4C E0 F4 44 ; CP Map Address Set to 0x44 E0 F5 68 ; HDMI RX Map Address Set to 0x68 E0 F6 6C ; EDID Map Address Set to 0x6C E0 F7 64 ; HDMI RX Repeater Map Address Set to 0x64 E0 F8 62 ; HDMI RX Infoframe Map Address Set to 0x62 E0 F9 F0 ; CBUS Map Address Set to 0xF0 E0 FA 82 ; CEC Map Address Set to 0x82 E0 FB F2 ; SDP Main Map Address Set to 0xF2 E0 FC 90 ; CSI-TXB Map Address Set to 0x90 E0 FD 94 ; CSI-TXA Map Address Set to 0x94 E0 06 11 ; Configure Pix Inputs E0 10 84 ; Enable 4-lane CSI Tx E0 0E F3 ; ADI Required Write 94 00 81 ; Enable 1-lane MIPI 94 00 A1 ; Set Auto DPHY Timing 94 D6 07 ; ADI Required Write 94 C4 0A ; ADI Required Write 94 71 33 ; ADI Required Write 94 72 11 ; ADI Required Write 94 F0 00 ; i2c_dphy_pwdn - 1'b0 94 31 82 ; ADI Required Write 94 1E 40 ; ADI Required Write 94 DA 01 ; i2c_mipi_pll_en - 1'b1 delay 2 ; 94 00 21 ; Power-up CSI-TX delay 1 ; 94 C1 2B ; ADI Required Write delay 1 ; 94 31 80 ; ADI Required Write End :06-02 8-Bit SDR TTL to MIPI TX-A CSI 2-Lane - 480i,576i,480p,576p,720p,1080i - YUV422 8-Bit: E0 FF FF ; SW reset delay 5 ; E0 01 76 ; ADI Required Write E0 05 4A ; Setting Vid_Std to 720x480p60 E0 00 30 ; Disable chip powerdown - powerdown Rx E0 F2 01 ; Enable I2C Read Auto-Increment E0 F3 4C ; DPLL Map Address Set to 0x4C E0 F4 44 ; CP Map Address Set to 0x44 E0 F5 68 ; HDMI RX Map Address Set to 0x68 E0 F6 6C ; EDID Map Address Set to 0x6C E0 F7 64 ; HDMI RX Repeater Map Address Set to 0x64 E0 F8 62 ; HDMI RX Infoframe Map Address Set to 0x62 E0 F9 F0 ; CBUS Map Address Set to 0xF0 E0 FA 82 ; CEC Map Address Set to 0x82 E0 FB F2 ; SDP Main Map Address Set to 0xF2 E0 FC 90 ; CSI-TXB Map Address Set to 0x90 E0 FD 94 ; CSI-TXA Map Address Set to 0x94 E0 06 11 ; Configure Pix Inputs E0 10 84 ; Enable 4-lane CSI Tx E0 0E F3 ; ADI Required Write 94 00 82 ; Enable 2-lane MIPI 94 00 A2 ; Set Auto DPHY Timing 94 D6 07 ; ADI Required Write 94 C4 0A ; ADI Required Write 94 71 33 ; ADI Required Write 94 72 11 ; ADI Required Write 94 F0 00 ; i2c_dphy_pwdn - 1'b0 94 31 82 ; ADI Required Write 94 1E 40 ; ADI Required Write 94 DA 01 ; i2c_mipi_pll_en - 1'b1 delay 2 ; 94 00 22 ; Power-up CSI-TX delay 1 ; 94 C1 2B ; ADI Required Write delay 1 ; 94 31 80 ; ADI Required Write End :06-03 8-Bit SDR TTL to MIPI TX-A CSI 4-Lane - 480p,576p,720p,1080i - YUV422 8-Bit: E0 FF FF ; SW reset delay 5 ; E0 01 76 ; ADI Required Write E0 05 53 ; Setting Vid_Std to 1280x720p60 E0 00 30 ; Disable chip powerdown - powerdown Rx E0 F2 01 ; Enable I2C Read Auto-Increment E0 F3 4C ; DPLL Map Address Set to 0x4C E0 F4 44 ; CP Map Address Set to 0x44 E0 F5 68 ; HDMI RX Map Address Set to 0x68 E0 F6 6C ; EDID Map Address Set to 0x6C E0 F7 64 ; HDMI RX Repeater Map Address Set to 0x64 E0 F8 62 ; HDMI RX Infoframe Map Address Set to 0x62 E0 F9 F0 ; CBUS Map Address Set to 0xF0 E0 FA 82 ; CEC Map Address Set to 0x82 E0 FB F2 ; SDP Main Map Address Set to 0xF2 E0 FC 90 ; CSI-TXB Map Address Set to 0x90 E0 FD 94 ; CSI-TXA Map Address Set to 0x94 E0 06 11 ; Configure Pix Inputs E0 10 84 ; Enable 4-lane CSI Tx E0 0E F3 ; ADI Required Write 94 00 84 ; Enable 4-lane MIPI 94 00 A4 ; Set Auto DPHY Timing 94 D6 07 ; ADI Required Write 94 C4 0A ; ADI Required Write 94 71 33 ; ADI Required Write 94 72 11 ; ADI Required Write 94 F0 00 ; i2c_dphy_pwdn - 1'b0 94 31 82 ; ADI Required Write 94 1E 40 ; ADI Required Write 94 DA 01 ; i2c_mipi_pll_en - 1'b1 delay 2 ; 94 00 24 ; Power-up CSI-TX delay 1 ; 94 C1 2B ; ADI Required Write delay 1 ; 94 31 80 ; ADI Required Write End ##07 TTL Input Scripts - 8-Bit_DDR - MIPI Output## :07-01 8-Bit DDR TTL to MIPI TX-A CSI 1-Lane - 480i,576i,480p,576p - YUV422 8-Bit: E0 FF FF ; SW reset delay 5 ; E0 01 76 ; ADI Required Write E0 05 4A ; Setting Vid_Std to 720x480p60 E0 00 30 ; Disable chip powerdown - powerdown Rx E0 F2 01 ; Enable I2C Read Auto-Increment E0 F3 4C ; DPLL Map Address Set to 0x4C E0 F4 44 ; CP Map Address Set to 0x44 E0 F5 68 ; HDMI RX Map Address Set to 0x68 E0 F6 6C ; EDID Map Address Set to 0x6C E0 F7 64 ; HDMI RX Repeater Map Address Set to 0x64 E0 F8 62 ; HDMI RX Infoframe Map Address Set to 0x62 E0 F9 F0 ; CBUS Map Address Set to 0xF0 E0 FA 82 ; CEC Map Address Set to 0x82 E0 FB F2 ; SDP Main Map Address Set to 0xF2 E0 FC 90 ; CSI-TXB Map Address Set to 0x90 E0 FD 94 ; CSI-TXA Map Address Set to 0x94 E0 06 35 ; Configure Pix Inputs E0 10 84 ; Enable 4-lane CSI Tx E0 0E F3 ; ADI Required Write 94 00 81 ; Enable 1-lane MIPI 94 00 A1 ; Set Auto DPHY Timing 94 D6 07 ; ADI Required Write 94 C4 0A ; ADI Required Write 94 71 33 ; ADI Required Write 94 72 11 ; ADI Required Write 94 F0 00 ; i2c_dphy_pwdn - 1'b0 94 31 82 ; ADI Required Write 94 1E 40 ; ADI Required Write 94 DA 01 ; i2c_mipi_pll_en - 1'b1 delay 2 ; 94 00 21 ; Power-up CSI-TX delay 1 ; 94 C1 2B ; ADI Required Write delay 1 ; 94 31 80 ; ADI Required Write End :07-02 8-Bit DDR TTL to MIPI TX-A CSI 2-Lane - 480i,576i,480p,576p,720p,1080i - YUV422 8-Bit: E0 FF FF ; SW reset delay 5 ; E0 01 76 ; ADI Required Write E0 05 4A ; Setting Vid_Std to 720x480p60 E0 00 30 ; Disable chip powerdown - powerdown Rx E0 F2 01 ; Enable I2C Read Auto-Increment E0 F3 4C ; DPLL Map Address Set to 0x4C E0 F4 44 ; CP Map Address Set to 0x44 E0 F5 68 ; HDMI RX Map Address Set to 0x68 E0 F6 6C ; EDID Map Address Set to 0x6C E0 F7 64 ; HDMI RX Repeater Map Address Set to 0x64 E0 F8 62 ; HDMI RX Infoframe Map Address Set to 0x62 E0 F9 F0 ; CBUS Map Address Set to 0xF0 E0 FA 82 ; CEC Map Address Set to 0x82 E0 FB F2 ; SDP Main Map Address Set to 0xF2 E0 FC 90 ; CSI-TXB Map Address Set to 0x90 E0 FD 94 ; CSI-TXA Map Address Set to 0x94 E0 06 35 ; Configure Pix Inputs E0 10 84 ; Enable 4-lane CSI Tx E0 0E F3 ; ADI Required Write 94 00 82 ; Enable 2-lane MIPI 94 00 A2 ; Set Auto DPHY Timing 94 D6 07 ; ADI Required Write 94 C4 0A ; ADI Required Write 94 71 33 ; ADI Required Write 94 72 11 ; ADI Required Write 94 F0 00 ; i2c_dphy_pwdn - 1'b0 94 31 82 ; ADI Required Write 94 1E 40 ; ADI Required Write 94 DA 01 ; i2c_mipi_pll_en - 1'b1 delay 2 ; 94 00 22 ; Power-up CSI-TX delay 1 ; 94 C1 2B ; ADI Required Write delay 1 ; 94 31 80 ; ADI Required Write End :07-03 8-Bit DDR TTL to MIPI TX-A CSI 4-Lane - 480p,576p,720p,1080i - YUV422 8-Bit: E0 FF FF ; SW reset delay 5 ; E0 01 76 ; ADI Required Write E0 05 53 ; Setting Vid_Std to 1280x720p60 E0 00 30 ; Disable chip powerdown - powerdown Rx E0 F2 01 ; Enable I2C Read Auto-Increment E0 F3 4C ; DPLL Map Address Set to 0x4C E0 F4 44 ; CP Map Address Set to 0x44 E0 F5 68 ; HDMI RX Map Address Set to 0x68 E0 F6 6C ; EDID Map Address Set to 0x6C E0 F7 64 ; HDMI RX Repeater Map Address Set to 0x64 E0 F8 62 ; HDMI RX Infoframe Map Address Set to 0x62 E0 F9 F0 ; CBUS Map Address Set to 0xF0 E0 FA 82 ; CEC Map Address Set to 0x82 E0 FB F2 ; SDP Main Map Address Set to 0xF2 E0 FC 90 ; CSI-TXB Map Address Set to 0x90 E0 FD 94 ; CSI-TXA Map Address Set to 0x94 E0 06 35 ; Configure Pix Inputs E0 10 84 ; Enable 4-lane CSI Tx E0 0E F3 ; ADI Required Write 94 00 84 ; Enable 4-lane MIPI 94 00 A4 ; Set Auto DPHY Timing 94 D6 07 ; ADI Required Write 94 C4 0A ; ADI Required Write 94 71 33 ; ADI Required Write 94 72 11 ; ADI Required Write 94 F0 00 ; i2c_dphy_pwdn - 1'b0 94 31 82 ; ADI Required Write 94 1E 40 ; ADI Required Write 94 DA 01 ; i2c_mipi_pll_en - 1'b1 delay 2 ; 94 00 24 ; Power-up CSI-TX delay 1 ; 94 C1 2B ; ADI Required Write delay 1 ; 94 31 80 ; ADI Required Write End ##08 Free Run Scripts## :08-01 Free-run MIPI TxA CSI 1-Lane - YUV422 8-Bit, 720x480p: E0 FF FF ; SW reset delay 5 ; E0 01 76 ; ADI Required Write E0 05 4A ; Setting Vid_Std to 720x480p60 E0 F2 01 ; Enable I2C Read Auto-Increment E0 F3 4C ; DPLL Map Address Set to 0x4C E0 F4 44 ; CP Map Address Set to 0x44 E0 F5 68 ; HDMI RX Map Address Set to 0x68 E0 F6 6C ; EDID Map Address Set to 0x6C E0 F7 64 ; HDMI RX Repeater Map Address Set to 0x64 E0 F8 62 ; HDMI RX Infoframe Map Address Set to 0x62 E0 F9 F0 ; CBUS Map Address Set to 0xF0 E0 FA 82 ; CEC Map Address Set to 0x82 E0 FB F2 ; SDP Main Map Address Set to 0xF2 E0 FC 90 ; CSI-TXB Map Address Set to 0x90 E0 FD 94 ; CSI-TXA Map Address Set to 0x94 E0 00 40 ; Disable chip powerdown & Enable HDMI Rx block 64 40 83 ; Enable HDCP 1.1 68 00 08 ; Foreground Channel = A 68 98 FF ; ADI Required Write 68 99 A3 ; ADI Required Write 68 9A 00 ; ADI Required Write 68 9B 0A ; ADI Required Write 68 9D 40 ; ADI Required Write 68 CB 09 ; ADI Required Write 68 3D 10 ; ADI Required Write 68 3E 7B ; ADI Required Write 68 3F 5E ; ADI Required Write 68 4E FE ; ADI Required Write 68 4F 18 ; ADI Required Write 68 57 A3 ; ADI Required Write 68 58 04 ; ADI Required Write 68 85 10 ; ADI Required Write 68 83 00 ; Enable All Terminations 68 A3 01 ; ADI Required Write 68 BE 00 ; ADI Required Write 68 6C 01 ; HPA Manual Enable 68 F8 01 ; HPA Asserted 68 0F 00 ; Audio Mute Speed Set to Fastest (Smallest Step Size) E0 04 00 ; YCrCb output E0 12 F2 ; CSC Depends on ip Packets - SDR422 set E0 17 80 ; Luma & Chroma Values Can Reach 254d E0 03 86 ; CP-Insert_AV_Code 44 7C 00 ; ADI Required Write E0 0C E0 ; Enable LLC_DLL & Double LLC Timing E0 0E DD ; LLC/PIX/SPI PINS TRISTATED AUD Outputs Enabled E0 10 A0 ; Enable 4-lane CSI Tx & Pixel Port 94 00 81 ; Enable 1-lane MIPI 94 00 A1 ; Set Auto DPHY Timing 94 DB 10 ; ADI Required Write 94 D6 07 ; ADI Required Write 94 C4 0A ; ADI Required Write 94 71 33 ; ADI Required Write 94 72 11 ; ADI Required Write 94 F0 00 ; i2c_dphy_pwdn - 1'b0 94 31 82 ; ADI Required Write 94 1E 40 ; ADI Required Write 94 DA 01 ; i2c_mipi_pll_en - 1'b1 delay 2 ; 94 00 21 ; Power-up CSI-TX delay 1 ; 94 C1 2B ; ADI Required Write delay 1 ; 94 31 80 ; ADI Required Write 44 C9 2D ; use cp_vid_std when free run E0 05 4A ; cp_vid_std set to 720x480p E0 03 86 ; Insert AV codes, enable CP free run mode E0 00 00 ; Disable HDMI Rx E0 04 80 ; Force CP to free run (YCbCr) 44 37 81 ; Output Colorbars Pattern End :08-02 Free-run MIPI TxA CSI 2-Lane - YUV422 8-Bit, 720x480p: E0 FF FF ; SW reset delay 5 ; E0 01 76 ; ADI Required Write E0 05 4A ; Setting Vid_Std to 720x480p60 E0 F2 01 ; Enable I2C Read Auto-Increment E0 F3 4C ; DPLL Map Address Set to 0x4C E0 F4 44 ; CP Map Address Set to 0x44 E0 F5 68 ; HDMI RX Map Address Set to 0x68 E0 F6 6C ; EDID Map Address Set to 0x6C E0 F7 64 ; HDMI RX Repeater Map Address Set to 0x64 E0 F8 62 ; HDMI RX Infoframe Map Address Set to 0x62 E0 F9 F0 ; CBUS Map Address Set to 0xF0 E0 FA 82 ; CEC Map Address Set to 0x82 E0 FB F2 ; SDP Main Map Address Set to 0xF2 E0 FC 90 ; CSI-TXB Map Address Set to 0x90 E0 FD 94 ; CSI-TXA Map Address Set to 0x94 E0 00 40 ; Disable chip powerdown & Enable HDMI Rx block 64 40 83 ; Enable HDCP 1.1 68 00 08 ; Foreground Channel = A 68 98 FF ; ADI Required Write 68 99 A3 ; ADI Required Write 68 9A 00 ; ADI Required Write 68 9B 0A ; ADI Required Write 68 9D 40 ; ADI Required Write 68 CB 09 ; ADI Required Write 68 3D 10 ; ADI Required Write 68 3E 7B ; ADI Required Write 68 3F 5E ; ADI Required Write 68 4E FE ; ADI Required Write 68 4F 18 ; ADI Required Write 68 57 A3 ; ADI Required Write 68 58 04 ; ADI Required Write 68 85 10 ; ADI Required Write 68 83 00 ; Enable All Terminations 68 A3 01 ; ADI Required Write 68 BE 00 ; ADI Required Write 68 6C 01 ; HPA Manual Enable 68 F8 01 ; HPA Asserted 68 0F 00 ; Audio Mute Speed Set to Fastest (Smallest Step Size) E0 04 00 ; YCrCb output E0 12 F2 ; CSC Depends on ip Packets - SDR422 set E0 17 80 ; Luma & Chroma Values Can Reach 254d E0 03 86 ; CP-Insert_AV_Code 44 7C 00 ; ADI Required Write E0 0C E0 ; Enable LLC_DLL & Double LLC Timing E0 0E DD ; LLC/PIX/SPI PINS TRISTATED AUD Outputs Enabled E0 10 A0 ; Enable 4-lane CSI Tx & Pixel Port 94 00 82 ; Enable 2-lane MIPI 94 00 A2 ; Set Auto DPHY Timing 94 DB 10 ; ADI Required Write 94 D6 07 ; ADI Required Write 94 C4 0A ; ADI Required Write 94 71 33 ; ADI Required Write 94 72 11 ; ADI Required Write 94 F0 00 ; i2c_dphy_pwdn - 1'b0 94 31 82 ; ADI Required Write 94 1E 40 ; ADI Required Write 94 DA 01 ; i2c_mipi_pll_en - 1'b1 delay 2 ; 94 00 22 ; Power-up CSI-TX delay 1 ; 94 C1 2B ; ADI Required Write delay 1 ; 94 31 80 ; ADI Required Write 44 C9 2D ; use cp_vid_std when free run E0 05 4A ; cp_vid_std set to 720x480p E0 03 86 ; Insert AV codes, enable CP free run mode E0 00 00 ; Disable HDMI Rx E0 04 80 ; Force CP to free run(YCbCr) 44 37 81 ; Output Colorbars Pattern End :08-03 Free-run MIPI TxA CSI 1-Lane - YUV422 8-Bit, 720x576p: E0 FF FF ; SW reset delay 5 ; E0 01 76 ; ADI Required Write E0 05 4A ; Setting Vid_Std to 720x480p60 E0 F2 01 ; Enable I2C Read Auto-Increment E0 F3 4C ; DPLL Map Address Set to 0x4C E0 F4 44 ; CP Map Address Set to 0x44 E0 F5 68 ; HDMI RX Map Address Set to 0x68 E0 F6 6C ; EDID Map Address Set to 0x6C E0 F7 64 ; HDMI RX Repeater Map Address Set to 0x64 E0 F8 62 ; HDMI RX Infoframe Map Address Set to 0x62 E0 F9 F0 ; CBUS Map Address Set to 0xF0 E0 FA 82 ; CEC Map Address Set to 0x82 E0 FB F2 ; SDP Main Map Address Set to 0xF2 E0 FC 90 ; CSI-TXB Map Address Set to 0x90 E0 FD 94 ; CSI-TXA Map Address Set to 0x94 E0 00 40 ; Disable chip powerdown & Enable HDMI Rx block 64 40 83 ; Enable HDCP 1.1 68 00 08 ; Foreground Channel = A 68 98 FF ; ADI Required Write 68 99 A3 ; ADI Required Write 68 9A 00 ; ADI Required Write 68 9B 0A ; ADI Required Write 68 9D 40 ; ADI Required Write 68 CB 09 ; ADI Required Write 68 3D 10 ; ADI Required Write 68 3E 7B ; ADI Required Write 68 3F 5E ; ADI Required Write 68 4E FE ; ADI Required Write 68 4F 18 ; ADI Required Write 68 57 A3 ; ADI Required Write 68 58 04 ; ADI Required Write 68 85 10 ; ADI Required Write 68 83 00 ; Enable All Terminations 68 A3 01 ; ADI Required Write 68 BE 00 ; ADI Required Write 68 6C 01 ; HPA Manual Enable 68 F8 01 ; HPA Asserted 68 0F 00 ; Audio Mute Speed Set to Fastest (Smallest Step Size) E0 04 00 ; YCrCb output E0 12 F2 ; CSC Depends on ip Packets - SDR422 set E0 17 80 ; Luma & Chroma Values Can Reach 254d E0 03 86 ; CP-Insert_AV_Code 44 7C 00 ; ADI Required Write E0 0C E0 ; Enable LLC_DLL & Double LLC Timing E0 0E DD ; LLC/PIX/SPI PINS TRISTATED AUD Outputs Enabled E0 10 A0 ; Enable 4-lane CSI Tx & Pixel Port 94 00 81 ; Enable 1-lane MIPI 94 00 A1 ; Set Auto DPHY Timing 94 DB 10 ; ADI Required Write 94 D6 07 ; ADI Required Write 94 C4 0A ; ADI Required Write 94 71 33 ; ADI Required Write 94 72 11 ; ADI Required Write 94 F0 00 ; i2c_dphy_pwdn - 1'b0 94 31 82 ; ADI Required Write 94 1E 40 ; ADI Required Write 94 DA 01 ; i2c_mipi_pll_en - 1'b1 delay 2 ; 94 00 21 ; Power-up CSI-TX delay 1 ; 94 C1 2B ; ADI Required Write delay 1 ; 94 31 80 ; ADI Required Write 44 C9 2D ; use cp_vid_std when free run E0 05 4B ; cp_vid_std set to 720x576p E0 03 96 ; Insert AV codes, enable CP free run mode E0 00 00 ; Disable HDMI Rx E0 04 80 ; Force CP to free run (YCbCr) 44 37 81 ; Output Colorbars Pattern End :08-04 Free-run MIPI TxA CSI 2-Lane - YUV422 8-Bit, 720x576p: E0 FF FF ; SW reset delay 5 ; E0 01 76 ; ADI Required Write E0 05 4A ; Setting Vid_Std to 720x480p60 E0 F2 01 ; Enable I2C Read Auto-Increment E0 F3 4C ; DPLL Map Address Set to 0x4C E0 F4 44 ; CP Map Address Set to 0x44 E0 F5 68 ; HDMI RX Map Address Set to 0x68 E0 F6 6C ; EDID Map Address Set to 0x6C E0 F7 64 ; HDMI RX Repeater Map Address Set to 0x64 E0 F8 62 ; HDMI RX Infoframe Map Address Set to 0x62 E0 F9 F0 ; CBUS Map Address Set to 0xF0 E0 FA 82 ; CEC Map Address Set to 0x82 E0 FB F2 ; SDP Main Map Address Set to 0xF2 E0 FC 90 ; CSI-TXB Map Address Set to 0x90 E0 FD 94 ; CSI-TXA Map Address Set to 0x94 E0 00 40 ; Disable chip powerdown & Enable HDMI Rx block 64 40 83 ; Enable HDCP 1.1 68 00 08 ; Foreground Channel = A 68 98 FF ; ADI Required Write 68 99 A3 ; ADI Required Write 68 9A 00 ; ADI Required Write 68 9B 0A ; ADI Required Write 68 9D 40 ; ADI Required Write 68 CB 09 ; ADI Required Write 68 3D 10 ; ADI Required Write 68 3E 7B ; ADI Required Write 68 3F 5E ; ADI Required Write 68 4E FE ; ADI Required Write 68 4F 18 ; ADI Required Write 68 57 A3 ; ADI Required Write 68 58 04 ; ADI Required Write 68 85 10 ; ADI Required Write 68 83 00 ; Enable All Terminations 68 A3 01 ; ADI Required Write 68 BE 00 ; ADI Required Write 68 6C 01 ; HPA Manual Enable 68 F8 01 ; HPA Asserted 68 0F 00 ; Audio Mute Speed Set to Fastest (Smallest Step Size) E0 04 00 ; YCrCb output E0 12 F2 ; CSC Depends on ip Packets - SDR422 set E0 17 80 ; Luma & Chroma Values Can Reach 254d E0 03 86 ; CP-Insert_AV_Code 44 7C 00 ; ADI Required Write E0 0C E0 ; Enable LLC_DLL & Double LLC Timing E0 0E DD ; LLC/PIX/SPI PINS TRISTATED AUD Outputs Enabled E0 10 A0 ; Enable 4-lane CSI Tx & Pixel Port 94 00 82 ; Enable 2-lane MIPI 94 00 A2 ; Set Auto DPHY Timing 94 DB 10 ; ADI Required Write 94 D6 07 ; ADI Required Write 94 C4 0A ; ADI Required Write 94 71 33 ; ADI Required Write 94 72 11 ; ADI Required Write 94 F0 00 ; i2c_dphy_pwdn - 1'b0 94 31 82 ; ADI Required Write 94 1E 40 ; ADI Required Write 94 DA 01 ; i2c_mipi_pll_en - 1'b1 delay 2 ; 94 00 22 ; Power-up CSI-TX delay 1 ; 94 C1 2B ; ADI Required Write delay 1 ; 94 31 80 ; ADI Required Write 44 C9 2D ; use cp_vid_std when free run E0 05 4B ; cp_vid_std set to 720x576p E0 03 96 ; Insert AV codes, enable CP free run mode E0 00 00 ; Disable HDMI Rx E0 04 80 ; Force CP to free run (YCbCr) 44 37 81 ; Output Colorbars Pattern End :08-05 Free-run MIPI TxA CSI 1-Lane - RGB888, VGA 640x480 60Hz: E0 FF FF ; SW reset delay 5 ; E0 01 76 ; ADI Required Write E0 05 4A ; Setting Vid_Std to 720x480p60 E0 F2 01 ; Enable I2C Read Auto-Increment E0 F3 4C ; DPLL Map Address Set to 0x4C E0 F4 44 ; CP Map Address Set to 0x44 E0 F5 68 ; HDMI RX Map Address Set to 0x68 E0 F6 6C ; EDID Map Address Set to 0x6C E0 F7 64 ; HDMI RX Repeater Map Address Set to 0x64 E0 F8 62 ; HDMI RX Infoframe Map Address Set to 0x62 E0 F9 F0 ; CBUS Map Address Set to 0xF0 E0 FA 82 ; CEC Map Address Set to 0x82 E0 FB F2 ; SDP Main Map Address Set to 0xF2 E0 FC 90 ; CSI-TXB Map Address Set to 0x90 E0 FD 94 ; CSI-TXA Map Address Set to 0x94 E0 00 40 ; Disable chip powerdown & Enable HDMI Rx block 64 40 83 ; Enable HDCP 1.1 68 00 08 ; Foreground Channel = A 68 98 FF ; ADI Required Write 68 99 A3 ; ADI Required Write 68 9A 00 ; ADI Required Write 68 9B 0A ; ADI Required Write 68 9D 40 ; ADI Required Write 68 CB 09 ; ADI Required Write 68 3D 10 ; ADI Required Write 68 3E 7B ; ADI Required Write 68 3F 5E ; ADI Required Write 68 4E FE ; ADI Required Write 68 4F 18 ; ADI Required Write 68 57 A3 ; ADI Required Write 68 58 04 ; ADI Required Write 68 85 10 ; ADI Required Write 68 83 00 ; Enable All Terminations 68 A3 01 ; ADI Required Write 68 BE 00 ; ADI Required Write 68 6C 01 ; HPA Manual Enable 68 F8 01 ; HPA Asserted 68 0F 00 ; Audio Mute Speed Set to Fastest (Smallest Step Size) E0 04 02 ; RGB Out of CP E0 12 F0 ; CSC Depends on ip Packets - SDR 444 E0 17 80 ; Luma & Chroma Values Can Reach 254d E0 03 86 ; CP-Insert_AV_Code 44 7C 00 ; ADI Required Write E0 0C E0 ; Enable LLC_DLL & Double LLC Timing E0 0E DD ; LLC/PIX/SPI PINS TRISTATED AUD Outputs Enabled E0 10 A0 ; Enable 4-lane CSI Tx & Pixel Port 94 00 81 ; Enable 1-lane MIPI 94 00 A1 ; Set Auto DPHY Timing 94 DB 13 ; ADI Required Write 94 D6 07 ; ADI Required Write 94 C4 0A ; ADI Required Write 94 71 33 ; ADI Required Write 94 72 11 ; ADI Required Write 94 F0 00 ; i2c_dphy_pwdn - 1'b0 94 31 82 ; ADI Required Write 94 1E 40 ; ADI Required Write 94 DA 01 ; i2c_mipi_pll_en - 1'b1 delay 2 ; 94 00 21 ; Power-up CSI-TX delay 1 ; 94 C1 2B ; ADI Required Write delay 1 ; 94 31 80 ; ADI Required Write 44 C9 2D ; use cp_vid_std when free run E0 05 88 ; cp_vid_std set to VGA 640x480@60 E0 03 86 ; Insert AV codes, enable CP free run mode E0 00 00 ; Disable HDMI Rx E0 04 82 ; Force CP to free run (RGB) 44 37 81 ; Output Colorbars Pattern End :08-06 Free-run MIPI TxA CSI 2-Lane - RGB888, VGA 640x480 60Hz: E0 FF FF ; SW reset delay 5 ; E0 01 76 ; ADI Required Write E0 05 4A ; Setting Vid_Std to 720x480p60 E0 F2 01 ; Enable I2C Read Auto-Increment E0 F3 4C ; DPLL Map Address Set to 0x4C E0 F4 44 ; CP Map Address Set to 0x44 E0 F5 68 ; HDMI RX Map Address Set to 0x68 E0 F6 6C ; EDID Map Address Set to 0x6C E0 F7 64 ; HDMI RX Repeater Map Address Set to 0x64 E0 F8 62 ; HDMI RX Infoframe Map Address Set to 0x62 E0 F9 F0 ; CBUS Map Address Set to 0xF0 E0 FA 82 ; CEC Map Address Set to 0x82 E0 FB F2 ; SDP Main Map Address Set to 0xF2 E0 FC 90 ; CSI-TXB Map Address Set to 0x90 E0 FD 94 ; CSI-TXA Map Address Set to 0x94 E0 00 40 ; Disable chip powerdown & Enable HDMI Rx block 64 40 83 ; Enable HDCP 1.1 68 00 08 ; Foreground Channel = A 68 98 FF ; ADI Required Write 68 99 A3 ; ADI Required Write 68 9A 00 ; ADI Required Write 68 9B 0A ; ADI Required Write 68 9D 40 ; ADI Required Write 68 CB 09 ; ADI Required Write 68 3D 10 ; ADI Required Write 68 3E 7B ; ADI Required Write 68 3F 5E ; ADI Required Write 68 4E FE ; ADI Required Write 68 4F 18 ; ADI Required Write 68 57 A3 ; ADI Required Write 68 58 04 ; ADI Required Write 68 85 10 ; ADI Required Write 68 83 00 ; Enable All Terminations 68 A3 01 ; ADI Required Write 68 BE 00 ; ADI Required Write 68 6C 01 ; HPA Manual Enable 68 F8 01 ; HPA Asserted 68 0F 00 ; Audio Mute Speed Set to Fastest (Smallest Step Size) E0 04 02 ; RGB Out of CP E0 12 F0 ; CSC Depends on ip Packets - SDR 444 E0 17 80 ; Luma & Chroma Values Can Reach 254d E0 03 86 ; CP-Insert_AV_Code 44 7C 00 ; ADI Required Write E0 0C E0 ; Enable LLC_DLL & Double LLC Timing E0 0E DD ; LLC/PIX/SPI PINS TRISTATED AUD Outputs Enabled E0 10 A0 ; Enable 4-lane CSI Tx & Pixel Port 94 00 82 ; Enable 2-lane MIPI 94 00 A2 ; Set Auto DPHY Timing 94 DB 10 ; ADI Required Write 94 D6 07 ; ADI Required Write 94 C4 0A ; ADI Required Write 94 71 33 ; ADI Required Write 94 72 11 ; ADI Required Write 94 F0 00 ; i2c_dphy_pwdn - 1'b0 94 31 82 ; ADI Required Write 94 1E 40 ; ADI Required Write 94 DA 01 ; i2c_mipi_pll_en - 1'b1 delay 2 ; 94 00 22 ; Power-up CSI-TX delay 1 ; 94 C1 2B ; ADI Required Write delay 1 ; 94 31 80 ; ADI Required Write 44 C9 2D ; use cp_vid_std when free run E0 05 88 ; cp_vid_std set to VGA 640x480@60 E0 03 86 ; Insert AV codes, enable CP free run mode E0 00 00 ; Disable HDMI Rx E0 04 82 ; Force CP to free run (RGB) 44 37 81 ; Output Colorbars Pattern End :08-07 Free-run MIPI TxA CSI 2-Lane - YUV422 8-Bit, 1280x720p 60Hz: E0 FF FF ; SW reset delay 5 ; E0 01 76 ; ADI Required Write E0 05 4A ; Setting Vid_Std to 720x480p60 E0 F2 01 ; Enable I2C Read Auto-Increment E0 F3 4C ; DPLL Map Address Set to 0x4C E0 F4 44 ; CP Map Address Set to 0x44 E0 F5 68 ; HDMI RX Map Address Set to 0x68 E0 F6 6C ; EDID Map Address Set to 0x6C E0 F7 64 ; HDMI RX Repeater Map Address Set to 0x64 E0 F8 62 ; HDMI RX Infoframe Map Address Set to 0x62 E0 F9 F0 ; CBUS Map Address Set to 0xF0 E0 FA 82 ; CEC Map Address Set to 0x82 E0 FB F2 ; SDP Main Map Address Set to 0xF2 E0 FC 90 ; CSI-TXB Map Address Set to 0x90 E0 FD 94 ; CSI-TXA Map Address Set to 0x94 E0 00 40 ; Disable chip powerdown & Enable HDMI Rx block 64 40 83 ; Enable HDCP 1.1 68 00 08 ; Foreground Channel = A 68 98 FF ; ADI Required Write 68 99 A3 ; ADI Required Write 68 9A 00 ; ADI Required Write 68 9B 0A ; ADI Required Write 68 9D 40 ; ADI Required Write 68 CB 09 ; ADI Required Write 68 3D 10 ; ADI Required Write 68 3E 7B ; ADI Required Write 68 3F 5E ; ADI Required Write 68 4E FE ; ADI Required Write 68 4F 18 ; ADI Required Write 68 57 A3 ; ADI Required Write 68 58 04 ; ADI Required Write 68 85 10 ; ADI Required Write 68 83 00 ; Enable All Terminations 68 A3 01 ; ADI Required Write 68 BE 00 ; ADI Required Write 68 6C 01 ; HPA Manual Enable 68 F8 01 ; HPA Asserted 68 0F 00 ; Audio Mute Speed Set to Fastest (Smallest Step Size) E0 04 00 ; YCrCb output E0 12 F2 ; CSC Depends on ip Packets - SDR422 set E0 17 80 ; Luma & Chroma Values Can Reach 254d E0 03 86 ; CP-Insert_AV_Code 44 7C 00 ; ADI Required Write E0 0C E0 ; Enable LLC_DLL & Double LLC Timing E0 0E DD ; LLC/PIX/SPI PINS TRISTATED AUD Outputs Enabled E0 10 A0 ; Enable 4-lane CSI Tx & Pixel Port 94 00 82 ; Enable 2-lane MIPI 94 00 A2 ; Set Auto DPHY Timing 94 DB 10 ; ADI Required Write 94 D6 07 ; ADI Required Write 94 C4 0A ; ADI Required Write 94 71 33 ; ADI Required Write 94 72 11 ; ADI Required Write 94 F0 00 ; i2c_dphy_pwdn - 1'b0 94 31 82 ; ADI Required Write 94 1E 40 ; ADI Required Write 94 DA 01 ; i2c_mipi_pll_en - 1'b1 delay 2 ; 94 00 22 ; Power-up CSI-TX delay 1 ; 94 C1 2B ; ADI Required Write delay 1 ; 94 31 80 ; ADI Required Write 44 C9 2D ; use cp_vid_std when free run E0 05 53 ; cp_vid_std set to 1280x720p@60 E0 03 86 ; Insert AV codes, enable CP free run mode E0 00 00 ; Disable HDMI Rx E0 04 80 ; Force CP to free run (YCbCr) 44 37 81 ; Output Colorbars Pattern End :08-08 Free-run MIPI TxA CSI 4-Lane - YUV422 8-Bit, 1280x720p 60Hz: E0 FF FF ; SW reset delay 5 ; E0 01 76 ; ADI Required Write E0 05 81 ; Setting Vid_Std to 800x600(SVGA)@60 E0 F2 01 ; Enable I2C Read Auto-Increment E0 F3 4C ; DPLL Map Address Set to 0x4C E0 F4 44 ; CP Map Address Set to 0x44 E0 F5 68 ; HDMI RX Map Address Set to 0x68 E0 F6 6C ; EDID Map Address Set to 0x6C E0 F7 64 ; HDMI RX Repeater Map Address Set to 0x64 E0 F8 62 ; HDMI RX Infoframe Map Address Set to 0x62 E0 F9 F0 ; CBUS Map Address Set to 0xF0 E0 FA 82 ; CEC Map Address Set to 0x82 E0 FB F2 ; SDP Main Map Address Set to 0xF2 E0 FC 90 ; CSI-TXB Map Address Set to 0x90 E0 FD 94 ; CSI-TXA Map Address Set to 0x94 E0 00 40 ; Disable chip powerdown & Enable HDMI Rx block 64 40 83 ; Enable HDCP 1.1 68 00 08 ; Foreground Channel = A 68 98 FF ; ADI Required Write 68 99 A3 ; ADI Required Write 68 9A 00 ; ADI Required Write 68 9B 0A ; ADI Required Write 68 9D 40 ; ADI Required Write 68 CB 09 ; ADI Required Write 68 3D 10 ; ADI Required Write 68 3E 7B ; ADI Required Write 68 3F 5E ; ADI Required Write 68 4E FE ; ADI Required Write 68 4F 18 ; ADI Required Write 68 57 A3 ; ADI Required Write 68 58 04 ; ADI Required Write 68 85 10 ; ADI Required Write 68 83 00 ; Enable All Terminations 68 A3 01 ; ADI Required Write 68 BE 00 ; ADI Required Write 68 6C 01 ; HPA Manual Enable 68 F8 01 ; HPA Asserted 68 0F 00 ; Audio Mute Speed Set to Fastest (Smallest Step Size) E0 04 00 ; YCrCb output E0 12 F2 ; CSC Depends on ip Packets - SDR422 set E0 17 80 ; Luma & Chroma Values Can Reach 254d E0 03 86 ; CP-Insert_AV_Code 44 7C 00 ; ADI Required Write E0 0C E0 ; Enable LLC_DLL & Double LLC Timing E0 0E DD ; LLC/PIX/SPI PINS TRISTATED AUD Outputs Enabled E0 10 A0 ; Enable 4-lane CSI Tx & Pixel Port 94 00 84 ; Enable 4-lane MIPI 94 00 A4 ; Set Auto DPHY Timing 94 DB 10 ; ADI Required Write 94 D6 07 ; ADI Required Write 94 C4 0A ; ADI Required Write 94 71 33 ; ADI Required Write 94 72 11 ; ADI Required Write 94 F0 00 ; i2c_dphy_pwdn - 1'b0 94 31 82 ; ADI Required Write 94 1E 40 ; ADI Required Write 94 DA 01 ; i2c_mipi_pll_en - 1'b1 delay 2 ; 94 00 24 ; Power-up CSI-TX delay 1 ; 94 C1 2B ; ADI Required Write delay 1 ; 94 31 80 ; ADI Required Write 44 C9 2D ; use cp_vid_std when free run E0 05 53 ; cp_vid_std set to 1280x720p@60 E0 03 86 ; Insert AV codes, enable CP free run mode E0 00 00 ; Disable HDMI Rx E0 04 80 ; Force CP to free run (YCbCr) 44 37 81 ; Output Colorbars Pattern End :08-09 Free-run MIPI TxA CSI 2-Lane - RGB888, 1280x720p 60Hz: E0 FF FF ; SW reset delay 5 ; E0 01 76 ; ADI Required Write E0 05 8C ; Setting Vid_Std to 1024x768(XGA)@60 E0 F2 01 ; Enable I2C Read Auto-Increment E0 F3 4C ; DPLL Map Address Set to 0x4C E0 F4 44 ; CP Map Address Set to 0x44 E0 F5 68 ; HDMI RX Map Address Set to 0x68 E0 F6 6C ; EDID Map Address Set to 0x6C E0 F7 64 ; HDMI RX Repeater Map Address Set to 0x64 E0 F8 62 ; HDMI RX Infoframe Map Address Set to 0x62 E0 F9 F0 ; CBUS Map Address Set to 0xF0 E0 FA 82 ; CEC Map Address Set to 0x82 E0 FB F2 ; SDP Main Map Address Set to 0xF2 E0 FC 90 ; CSI-TXB Map Address Set to 0x90 E0 FD 94 ; CSI-TXA Map Address Set to 0x94 E0 00 40 ; Disable chip powerdown & Enable HDMI Rx block 64 40 83 ; Enable HDCP 1.1 68 00 08 ; Foreground Channel = A 68 98 FF ; ADI Required Write 68 99 A3 ; ADI Required Write 68 9A 00 ; ADI Required Write 68 9B 0A ; ADI Required Write 68 9D 40 ; ADI Required Write 68 CB 09 ; ADI Required Write 68 3D 10 ; ADI Required Write 68 3E 7B ; ADI Required Write 68 3F 5E ; ADI Required Write 68 4E FE ; ADI Required Write 68 4F 18 ; ADI Required Write 68 57 A3 ; ADI Required Write 68 58 04 ; ADI Required Write 68 85 10 ; ADI Required Write 68 83 00 ; Enable All Terminations 68 A3 01 ; ADI Required Write 68 BE 00 ; ADI Required Write 68 6C 01 ; HPA Manual Enable 68 F8 01 ; HPA Asserted 68 0F 00 ; Audio Mute Speed Set to Fastest (Smallest Step Size) E0 04 02 ; RGB Out of CP E0 12 F0 ; CSC Depends on ip Packets - SDR 444 E0 17 80 ; Luma & Chroma Values Can Reach 254d E0 03 86 ; CP-Insert_AV_Code 44 7C 00 ; ADI Required Write E0 0C E0 ; Enable LLC_DLL & Double LLC Timing E0 0E DD ; LLC/PIX/SPI PINS TRISTATED AUD Outputs Enabled E0 10 A0 ; Enable 4-lane CSI Tx & Pixel Port 94 00 82 ; Enable 2-lane MIPI 94 00 A2 ; Set Auto DPHY Timing 94 DB 13 ; ADI Required Write 94 D6 07 ; ADI Required Write 94 C4 0A ; ADI Required Write 94 71 33 ; ADI Required Write 94 72 11 ; ADI Required Write 94 F0 00 ; i2c_dphy_pwdn - 1'b0 94 31 82 ; ADI Required Write 94 1E 40 ; ADI Required Write 94 DA 01 ; i2c_mipi_pll_en - 1'b1 delay 2 ; 94 00 22 ; Power-up CSI-TX delay 1 ; 94 C1 2B ; ADI Required Write delay 1 ; 94 31 80 ; ADI Required Write 44 C9 2D ; use cp_vid_std when free run E0 05 53 ; cp_vid_std set to 1280x720p@60 E0 03 86 ; Insert AV codes, enable CP free run mode E0 00 00 ; Disable HDMI Rx E0 04 82 ; Force CP to free run (RGB) 44 37 81 ; Output Colorbars Pattern End :08-10 Free-run MIPI TxA CSI 4-Lane - RGB888, 1280x720p 60Hz: E0 FF FF ; SW reset delay 5 ; E0 01 76 ; ADI Required Write E0 05 4A ; Setting Vid_Std to 720x480p60 E0 F2 01 ; Enable I2C Read Auto-Increment E0 F3 4C ; DPLL Map Address Set to 0x4C E0 F4 44 ; CP Map Address Set to 0x44 E0 F5 68 ; HDMI RX Map Address Set to 0x68 E0 F6 6C ; EDID Map Address Set to 0x6C E0 F7 64 ; HDMI RX Repeater Map Address Set to 0x64 E0 F8 62 ; HDMI RX Infoframe Map Address Set to 0x62 E0 F9 F0 ; CBUS Map Address Set to 0xF0 E0 FA 82 ; CEC Map Address Set to 0x82 E0 FB F2 ; SDP Main Map Address Set to 0xF2 E0 FC 90 ; CSI-TXB Map Address Set to 0x90 E0 FD 94 ; CSI-TXA Map Address Set to 0x94 E0 00 40 ; Disable chip powerdown & Enable HDMI Rx block 64 40 83 ; Enable HDCP 1.1 68 00 08 ; Foreground Channel = A 68 98 FF ; ADI Required Write 68 99 A3 ; ADI Required Write 68 9A 00 ; ADI Required Write 68 9B 0A ; ADI Required Write 68 9D 40 ; ADI Required Write 68 CB 09 ; ADI Required Write 68 3D 10 ; ADI Required Write 68 3E 7B ; ADI Required Write 68 3F 5E ; ADI Required Write 68 4E FE ; ADI Required Write 68 4F 18 ; ADI Required Write 68 57 A3 ; ADI Required Write 68 58 04 ; ADI Required Write 68 85 10 ; ADI Required Write 68 83 00 ; Enable All Terminations 68 A3 01 ; ADI Required Write 68 BE 00 ; ADI Required Write 68 6C 01 ; HPA Manual Enable 68 F8 01 ; HPA Asserted 68 0F 00 ; Audio Mute Speed Set to Fastest (Smallest Step Size) E0 04 02 ; RGB Out of CP E0 12 F0 ; CSC Depends on ip Packets - SDR 444 E0 17 80 ; Luma & Chroma Values Can Reach 254d E0 03 86 ; CP-Insert_AV_Code 44 7C 00 ; ADI Required Write E0 0C E0 ; Enable LLC_DLL & Double LLC Timing E0 0E DD ; LLC/PIX/SPI PINS TRISTATED AUD Outputs Enabled E0 10 A0 ; Enable 4-lane CSI Tx & Pixel Port 94 00 84 ; Enable 4-lane MIPI 94 00 A4 ; Set Auto DPHY Timing 94 DB 10 ; ADI Required Write 94 D6 07 ; ADI Required Write 94 C4 0A ; ADI Required Write 94 71 33 ; ADI Required Write 94 72 11 ; ADI Required Write 94 F0 00 ; i2c_dphy_pwdn - 1'b0 94 31 82 ; ADI Required Write 94 1E 40 ; ADI Required Write 94 DA 01 ; i2c_mipi_pll_en - 1'b1 delay 2 ; 94 00 24 ; Power-up CSI-TX delay 1 ; 94 C1 2B ; ADI Required Write delay 1 ; 94 31 80 ; ADI Required Write 44 C9 2D ; use cp_vid_std when free run E0 05 53 ; cp_vid_std set to 1280x720p@60 E0 03 86 ; Insert AV codes, enable CP free run mode E0 00 00 ; Disable HDMI Rx E0 04 82 ; Force CP to free run (RGB) 44 37 81 ; Output Colorbars Pattern End :08-11 Free-run MIPI TxA CSI 2-Lane - RGB888, WVGA 800x480 60Hz: E0 FF FF ; SW reset delay 5 ; E0 01 76 ; ADI Required Write E0 05 8C ; Setting Vid_Std to 1024x768(XGA)@60 E0 F2 01 ; Enable I2C Read Auto-Increment E0 F3 4C ; DPLL Map Address Set to 0x4C E0 F4 44 ; CP Map Address Set to 0x44 E0 F5 68 ; HDMI RX Map Address Set to 0x68 E0 F6 6C ; EDID Map Address Set to 0x6C E0 F7 64 ; HDMI RX Repeater Map Address Set to 0x64 E0 F8 62 ; HDMI RX Infoframe Map Address Set to 0x62 E0 F9 F0 ; CBUS Map Address Set to 0xF0 E0 FA 82 ; CEC Map Address Set to 0x82 E0 FB F2 ; SDP Main Map Address Set to 0xF2 E0 FC 90 ; CSI-TXB Map Address Set to 0x90 E0 FD 94 ; CSI-TXA Map Address Set to 0x94 E0 00 40 ; Disable chip powerdown & Enable HDMI Rx block 64 40 83 ; Enable HDCP 1.1 68 00 08 ; Foreground Channel = A 68 98 FF ; ADI Required Write 68 99 A3 ; ADI Required Write 68 9A 00 ; ADI Required Write 68 9B 0A ; ADI Required Write 68 9D 40 ; ADI Required Write 68 CB 09 ; ADI Required Write 68 3D 10 ; ADI Required Write 68 3E 7B ; ADI Required Write 68 3F 5E ; ADI Required Write 68 4E FE ; ADI Required Write 68 4F 18 ; ADI Required Write 68 57 A3 ; ADI Required Write 68 58 04 ; ADI Required Write 68 85 10 ; ADI Required Write 68 83 00 ; Enable All Terminations 68 A3 01 ; ADI Required Write 68 BE 00 ; ADI Required Write 68 6C 01 ; HPA Manual Enable 68 F8 01 ; HPA Asserted 68 0F 00 ; Audio Mute Speed Set to Fastest (Smallest Step Size) E0 04 02 ; RGB Out of CP E0 12 F0 ; CSC Depends on ip Packets - SDR 444 E0 17 80 ; Luma & Chroma Values Can Reach 254d E0 03 86 ; CP-Insert_AV_Code 44 7C 00 ; ADI Required Write E0 0C E0 ; Enable LLC_DLL & Double LLC Timing E0 0E DD ; LLC/PIX/SPI PINS TRISTATED AUD Outputs Enabled E0 10 A0 ; Enable 4-lane CSI Tx & Pixel Port 94 00 82 ; Enable 2-lane MIPI 94 00 A2 ; Set Auto DPHY Timing 94 DB 13 ; ADI Required Write 94 D6 07 ; ADI Required Write 94 C4 0A ; ADI Required Write 94 71 33 ; ADI Required Write 94 72 11 ; ADI Required Write 94 F0 00 ; i2c_dphy_pwdn - 1'b0 94 31 82 ; ADI Required Write 94 1E 40 ; ADI Required Write 94 DA 01 ; i2c_mipi_pll_en - 1'b1 delay 2 ; 94 00 22 ; Power-up CSI-TX delay 1 ; 94 C1 2B ; ADI Required Write delay 1 ; 94 31 80 ; ADI Required Write 44 C9 2D ; use cp_vid_std when free run E0 05 9E ; cp_vid_std set to WVGA 800x480@60 E0 03 86 ; Insert AV codes, enable CP free run mode E0 00 00 ; Disable HDMI Rx E0 04 82 ; Force CP to free run (RGB) 44 37 81 ; Output Colorbars Pattern End :08-12 Free-run MIPI TxA CSI 4-Lane - RGB888, WVGA 800x480 60Hz: E0 FF FF ; SW reset delay 5 ; E0 01 76 ; ADI Required Write E0 05 4A ; Setting Vid_Std to 720x480p60 E0 F2 01 ; Enable I2C Read Auto-Increment E0 F3 4C ; DPLL Map Address Set to 0x4C E0 F4 44 ; CP Map Address Set to 0x44 E0 F5 68 ; HDMI RX Map Address Set to 0x68 E0 F6 6C ; EDID Map Address Set to 0x6C E0 F7 64 ; HDMI RX Repeater Map Address Set to 0x64 E0 F8 62 ; HDMI RX Infoframe Map Address Set to 0x62 E0 F9 F0 ; CBUS Map Address Set to 0xF0 E0 FA 82 ; CEC Map Address Set to 0x82 E0 FB F2 ; SDP Main Map Address Set to 0xF2 E0 FC 90 ; CSI-TXB Map Address Set to 0x90 E0 FD 94 ; CSI-TXA Map Address Set to 0x94 E0 00 40 ; Disable chip powerdown & Enable HDMI Rx block 64 40 83 ; Enable HDCP 1.1 68 00 08 ; Foreground Channel = A 68 98 FF ; ADI Required Write 68 99 A3 ; ADI Required Write 68 9A 00 ; ADI Required Write 68 9B 0A ; ADI Required Write 68 9D 40 ; ADI Required Write 68 CB 09 ; ADI Required Write 68 3D 10 ; ADI Required Write 68 3E 7B ; ADI Required Write 68 3F 5E ; ADI Required Write 68 4E FE ; ADI Required Write 68 4F 18 ; ADI Required Write 68 57 A3 ; ADI Required Write 68 58 04 ; ADI Required Write 68 85 10 ; ADI Required Write 68 83 00 ; Enable All Terminations 68 A3 01 ; ADI Required Write 68 BE 00 ; ADI Required Write 68 6C 01 ; HPA Manual Enable 68 F8 01 ; HPA Asserted 68 0F 00 ; Audio Mute Speed Set to Fastest (Smallest Step Size) E0 04 02 ; RGB Out of CP E0 12 F0 ; CSC Depends on ip Packets - SDR 444 E0 17 80 ; Luma & Chroma Values Can Reach 254d E0 03 86 ; CP-Insert_AV_Code 44 7C 00 ; ADI Required Write E0 0C E0 ; Enable LLC_DLL & Double LLC Timing E0 0E DD ; LLC/PIX/SPI PINS TRISTATED AUD Outputs Enabled E0 10 A0 ; Enable 4-lane CSI Tx & Pixel Port 94 00 84 ; Enable 4-lane MIPI 94 00 A4 ; Set Auto DPHY Timing 94 DB 10 ; ADI Required Write 94 D6 07 ; ADI Required Write 94 C4 0A ; ADI Required Write 94 71 33 ; ADI Required Write 94 72 11 ; ADI Required Write 94 F0 00 ; i2c_dphy_pwdn - 1'b0 94 31 82 ; ADI Required Write 94 1E 40 ; ADI Required Write 94 DA 01 ; i2c_mipi_pll_en - 1'b1 delay 2 ; 94 00 24 ; Power-up CSI-TX delay 1 ; 94 C1 2B ; ADI Required Write delay 1 ; 94 31 80 ; ADI Required Write 44 C9 2D ; use cp_vid_std when free run E0 05 9E ; cp_vid_std set to WVGA 800x480@60 E0 03 86 ; Insert AV codes, enable CP free run mode E0 00 00 ; Disable HDMI Rx E0 04 82 ; Force CP to free run (RGB) 44 37 81 ; Output Colorbars Pattern End :08-13 Free-run MIPI TxA CSI 4-Lane - RGB888, WXGA-SONY 1280x768 60Hz: E0 FF FF ; SW reset delay 5 ; E0 01 76 ; ADI Required Write E0 05 4A ; Setting Vid_Std to 720x480p60 E0 F2 01 ; Enable I2C Read Auto-Increment E0 F3 4C ; DPLL Map Address Set to 0x4C E0 F4 44 ; CP Map Address Set to 0x44 E0 F5 68 ; HDMI RX Map Address Set to 0x68 E0 F6 6C ; EDID Map Address Set to 0x6C E0 F7 64 ; HDMI RX Repeater Map Address Set to 0x64 E0 F8 62 ; HDMI RX Infoframe Map Address Set to 0x62 E0 F9 F0 ; CBUS Map Address Set to 0xF0 E0 FA 82 ; CEC Map Address Set to 0x82 E0 FB F2 ; SDP Main Map Address Set to 0xF2 E0 FC 90 ; CSI-TXB Map Address Set to 0x90 E0 FD 94 ; CSI-TXA Map Address Set to 0x94 E0 00 40 ; Disable chip powerdown & Enable HDMI Rx block 64 40 83 ; Enable HDCP 1.1 68 00 08 ; Foreground Channel = A 68 98 FF ; ADI Required Write 68 99 A3 ; ADI Required Write 68 9A 00 ; ADI Required Write 68 9B 0A ; ADI Required Write 68 9D 40 ; ADI Required Write 68 CB 09 ; ADI Required Write 68 3D 10 ; ADI Required Write 68 3E 7B ; ADI Required Write 68 3F 5E ; ADI Required Write 68 4E FE ; ADI Required Write 68 4F 18 ; ADI Required Write 68 57 A3 ; ADI Required Write 68 58 04 ; ADI Required Write 68 85 10 ; ADI Required Write 68 83 00 ; Enable All Terminations 68 A3 01 ; ADI Required Write 68 BE 00 ; ADI Required Write 68 6C 01 ; HPA Manual Enable 68 F8 01 ; HPA Asserted 68 0F 00 ; Audio Mute Speed Set to Fastest (Smallest Step Size) E0 04 02 ; RGB Out of CP E0 12 F0 ; CSC Depends on ip Packets - SDR 444 E0 17 80 ; Luma & Chroma Values Can Reach 254d E0 03 86 ; CP-Insert_AV_Code 44 7C 00 ; ADI Required Write E0 0C E0 ; Enable LLC_DLL & Double LLC Timing E0 0E DD ; LLC/PIX/SPI PINS TRISTATED AUD Outputs Enabled E0 10 A0 ; Enable 4-lane CSI Tx & Pixel Port 94 00 84 ; Enable 4-lane MIPI 94 00 A4 ; Set Auto DPHY Timing 94 DB 10 ; ADI Required Write 94 D6 07 ; ADI Required Write 94 C4 0A ; ADI Required Write 94 71 33 ; ADI Required Write 94 72 11 ; ADI Required Write 94 F0 00 ; i2c_dphy_pwdn - 1'b0 94 31 82 ; ADI Required Write 94 1E 40 ; ADI Required Write 94 DA 01 ; i2c_mipi_pll_en - 1'b1 delay 2 ; 94 00 24 ; Power-up CSI-TX delay 1 ; 94 C1 2B ; ADI Required Write delay 1 ; 94 31 80 ; ADI Required Write 44 C9 2D ; use cp_vid_std when free run E0 05 90 ; cp_vid_std set to WXGA-SONY 1280x768@60 E0 03 86 ; Insert AV codes, enable CP free run mode E0 00 00 ; Disable HDMI Rx E0 04 82 ; Force CP to free run (RGB) 44 37 81 ; Output Colorbars Pattern End :08-14 Free-run MIPI TxA CSI 4-Lane - RGB888, 1920x1080p 60Hz: E0 FF FF ; SW reset delay 5 ; E0 01 76 ; ADI Required Write E0 05 96 ; Setting Vid_Std to 1600x1200(UXGA)@60 E0 F2 01 ; Enable I2C Read Auto-Increment E0 F3 4C ; DPLL Map Address Set to 0x4C E0 F4 44 ; CP Map Address Set to 0x44 E0 F5 68 ; HDMI RX Map Address Set to 0x68 E0 F6 6C ; EDID Map Address Set to 0x6C E0 F7 64 ; HDMI RX Repeater Map Address Set to 0x64 E0 F8 62 ; HDMI RX Infoframe Map Address Set to 0x62 E0 F9 F0 ; CBUS Map Address Set to 0xF0 E0 FA 82 ; CEC Map Address Set to 0x82 E0 FB F2 ; SDP Main Map Address Set to 0xF2 E0 FC 90 ; CSI-TXB Map Address Set to 0x90 E0 FD 94 ; CSI-TXA Map Address Set to 0x94 E0 00 40 ; Disable chip powerdown & Enable HDMI Rx block 64 40 83 ; Enable HDCP 1.1 68 00 08 ; Foreground Channel = A 68 98 FF ; ADI Required Write 68 99 A3 ; ADI Required Write 68 9A 00 ; ADI Required Write 68 9B 0A ; ADI Required Write 68 9D 40 ; ADI Required Write 68 CB 09 ; ADI Required Write 68 3D 10 ; ADI Required Write 68 3E 7B ; ADI Required Write 68 3F 5E ; ADI Required Write 68 4E FE ; ADI Required Write 68 4F 18 ; ADI Required Write 68 57 A3 ; ADI Required Write 68 58 04 ; ADI Required Write 68 85 10 ; ADI Required Write 68 83 00 ; Enable All Terminations 68 A3 01 ; ADI Required Write 68 BE 00 ; ADI Required Write 68 6C 01 ; HPA Manual Enable 68 F8 01 ; HPA Asserted 68 0F 00 ; Audio Mute Speed Set to Fastest (Smallest Step Size) E0 04 02 ; RGB Out of CP E0 12 F0 ; CSC Depends on ip Packets - SDR 444 E0 17 80 ; Luma & Chroma Values Can Reach 254d E0 03 86 ; CP-Insert_AV_Code 44 7C 00 ; ADI Required Write E0 0C E0 ; Enable LLC_DLL & Double LLC Timing E0 0E DD ; LLC/PIX/SPI PINS TRISTATED AUD Outputs Enabled E0 10 A0 ; Enable 4-lane CSI Tx & Pixel Port 94 00 84 ; Enable 4-lane MIPI 94 00 A4 ; Set Auto DPHY Timing 94 DB 13 ; ADI Required Write 94 D6 07 ; ADI Required Write 94 C4 0A ; ADI Required Write 94 71 33 ; ADI Required Write 94 72 11 ; ADI Required Write 94 F0 00 ; i2c_dphy_pwdn - 1'b0 94 31 82 ; ADI Required Write 94 1E 40 ; ADI Required Write 94 DA 01 ; i2c_mipi_pll_en - 1'b1 delay 2 ; 94 00 24 ; Power-up CSI-TX delay 1 ; 94 C1 2B ; ADI Required Write delay 1 ; 94 31 80 ; ADI Required Write 44 C9 2D ; use cp_vid_std when free run E0 05 5E ; cp_vid_std set to 1920x1080p60 E0 03 86 ; Insert AV codes, enable CP free run mode E0 00 00 ; Disable HDMI Rx E0 04 82 ; Force CP to free run (RGB) 44 37 81 ; Output Colorbars Pattern End :08-15 Free-run MIPI TxB CSI 1-Lane - YUV422 8-Bit, NTSC: E0 FF FF ; SW reset delay 5 ; E0 01 76 ; ADI Required Write E0 00 30 ; Disable chip powerdown - powerdown Rx E0 F2 01 ; Enable I2C Read Auto-Increment E0 F3 4C ; DPLL Map Address Set to 0x4C E0 F4 44 ; CP Map Address Set to 0x44 E0 F5 68 ; HDMI RX Map Address Set to 0x68 E0 F6 6C ; EDID Map Address Set to 0x6C E0 F7 64 ; HDMI RX Repeater Map Address Set to 0x64 E0 F8 62 ; HDMI RX Infoframe Map Address Set to 0x62 E0 F9 F0 ; CBUS Map Address Set to 0xF0 E0 FA 82 ; CEC Map Address Set to 0x82 E0 FB F2 ; SDP Main Map Address Set to 0xF2 E0 FC 90 ; CSI-TXB Map Address Set to 0x90 E0 FD 94 ; CSI-TXA Map Address Set to 0x94 E0 0E FF ; LLC/PIX/AUD/SPI PINS TRISTATED F2 0F 00 ; Exit Power Down Mode F2 52 CD ; ADI Required Write F2 00 00 ; INSEL = CVBS in on Ain 1 F2 0E 80 ; ADI Required Write F2 9C 00 ; ADI Required Write F2 9C FF ; ADI Required Write F2 0E 00 ; ADI Required Write F2 02 54 ; ADI Required Write F2 0C 37 ; Force free run F2 14 11 ; Output Colorbars F2 80 51 ; ADI Required Write F2 81 51 ; ADI Required Write F2 82 68 ; ADI Required Write F2 03 42 ; Tri-S Output Drivers, PwrDwn 656 pads F2 04 07 ; Power-up INTRQ pad, & Enable SFL F2 13 00 ; ADI Required Write F2 17 41 ; Select SH1 F2 31 12 ; ADI Required Write E0 10 70 ; Enable 1-Lane MIPI Tx, enable pixel output and route SD through Pixel port 90 00 81 ; Enable 1-lane MIPI 90 00 A1 ; Set Auto DPHY Timing 94 F0 00 ; ADI Required Write 94 D6 07 ; ADI Required Write 94 C0 3C ; ADI Required Write 94 C3 3C ; ADI Required Write 94 C6 3C ; ADI Required Write 94 C9 3C ; ADI Required Write 94 CC 3C ; ADI Required Write 94 D5 03 ; ADI Required Write 90 D2 40 ; ADI Required Write 90 C4 0A ; ADI Required Write 90 71 33 ; ADI Required Write 90 72 11 ; ADI Required Write 90 F0 00 ; i2c_dphy_pwdn - 1'b0 90 31 82 ; ADI Required Write 90 1E 40 ; ADI Required Write 90 DA 01 ; i2c_mipi_pll_en - 1'b1 delay 2 ; 90 00 21 ; Power-up CSI-TX delay 1 ; 90 C1 2B ; ADI Required Write delay 1 ; 90 31 80 ; ADI Required Write End :08-16 Free-run MIPI TxB CSI 1-Lane - YUV422 8-Bit, PAL: E0 FF FF ; SW reset delay 5 ; E0 01 76 ; ADI Required Write E0 00 30 ; Disable chip powerdown - powerdown Rx E0 F2 01 ; Enable I2C Read Auto-Increment E0 F3 4C ; DPLL Map Address Set to 0x4C E0 F4 44 ; CP Map Address Set to 0x44 E0 F5 68 ; HDMI RX Map Address Set to 0x68 E0 F6 6C ; EDID Map Address Set to 0x6C E0 F7 64 ; HDMI RX Repeater Map Address Set to 0x64 E0 F8 62 ; HDMI RX Infoframe Map Address Set to 0x62 E0 F9 F0 ; CBUS Map Address Set to 0xF0 E0 FA 82 ; CEC Map Address Set to 0x82 E0 FB F2 ; SDP Main Map Address Set to 0xF2 E0 FC 90 ; CSI-TXB Map Address Set to 0x90 E0 FD 94 ; CSI-TXA Map Address Set to 0x94 E0 0E FF ; LLC/PIX/AUD/SPI PINS TRISTATED F2 0F 00 ; Exit Power Down Mode F2 52 CD ; ADI Required Write F2 00 00 ; INSEL = CVBS in on Ain 1 F2 0E 80 ; ADI Required Write F2 9C 00 ; ADI Required Write F2 9C FF ; ADI Required Write F2 0E 00 ; ADI Required Write F2 02 84 ; ADI Required Write F2 0C 37 ; Force free run F2 14 11 ; Output Colorbars F2 80 51 ; ADI Required Write F2 81 51 ; ADI Required Write F2 82 68 ; ADI Required Write F2 03 42 ; Tri-S Output Drivers, PwrDwn 656 pads F2 04 07 ; Power-up INTRQ pad, & Enable SFL F2 13 00 ; ADI Required Write F2 17 41 ; Select SH1 F2 31 12 ; ADI Required Write E0 10 70 ; Enable 1-Lane MIPI Tx, enable pixel output and route SD through Pixel port 90 00 81 ; Enable 1-lane MIPI 90 00 A1 ; Set Auto DPHY Timing 94 F0 00 ; ADI Required Write 94 D6 07 ; ADI Required Write 94 C0 3C ; ADI Required Write 94 C3 3C ; ADI Required Write 94 C6 3C ; ADI Required Write 94 C9 3C ; ADI Required Write 94 CC 3C ; ADI Required Write 94 D5 03 ; ADI Required Write 90 D2 40 ; ADI Required Write 90 C4 0A ; ADI Required Write 90 71 33 ; ADI Required Write 90 72 11 ; ADI Required Write 90 F0 00 ; i2c_dphy_pwdn - 1'b0 90 31 82 ; ADI Required Write 90 1E 40 ; ADI Required Write 90 DA 01 ; i2c_mipi_pll_en - 1'b1 delay 2 ; 90 00 21 ; Power-up CSI-TX delay 1 ; 90 C1 2B ; ADI Required Write delay 1 ; 90 31 80 ; ADI Required Write End :08-17 Forced 480p free run to Pixel Port - SDR8av Out: E0 FF FF ; SW reset delay 5 ; E0 01 76 ; ADI Required Write E0 F2 01 ; Enable I2C read auto-increment E0 F3 4C ; DPLL Map address set to 0x4C E0 F4 44 ; CP Map address set to 0x44 E0 F5 68 ; HDMI RX Map address set to 0x68 E0 F6 6C ; EDID Map address set to 0x6C E0 F7 64 ; HDMI RX Repeater Map address set to 0x64 E0 F8 62 ; HDMI RX Infoframe Map address set to 0x62 E0 F9 F0 ; CBUS Map address set to 0xF0 E0 FA 82 ; CEC Map address set to 0x82 E0 FB F2 ; SDP Main Map address set to 0xF2 E0 FC 90 ; CSI-TXB Map address set to 0x90 E0 FD 94 ; CSI-TXA Map address set to 0x94 E0 00 40 ; Disable chip powerdown & Enable HDMI Rx block 64 40 83 ; enable HDCP 1.1 68 00 08 ; foreground channel = A 68 3D 10 ; ADI Required Write 68 3E 7B ; ADI Required Write 68 3F 5E ; ADI Required Write 68 4E FE ; ADI Required Write 68 4F 08 ; ADI Required Write 68 57 A3 ; ADI Required Write 68 58 04 ; ADI Required Write 68 85 10 ; ADI Required Write 68 83 00 ; Enable all terminations 68 98 FF ; ADI Required Write 68 99 A3 ; ADI Required Write 68 9A 00 ; ADI Required Write 68 9B 0A ; ADI Required Write 68 9D 40 ; ADI Required Write 68 CB 09 ; ADI Required Write 68 A3 01 ; ADI Required Write 68 BE 00 ; ADI Required Write 68 0F 00 ; Audio Mute Speed Set to Fastest (Smallest Step Size) E0 0E DD ; Enable audio pads 68 6C 01 ; HPA manual enable 68 F8 01 ; HPA asserted E0 03 86 ; Insert AV codes, CP Free run Enable E0 04 00 ; CP in YPrPb mode E0 0E 11 ; Enable LLC, Pixel and Audio outputs E0 10 20 ; Enable Pixel port and route from CP core E0 12 F4 ; Output is 8-bit SDR 422 E0 0C FF ; llc_dll_en, llc_ddl_mux, LLC_DLL_double = 1'b1 , llc_dll_phase = 5'b11111 (31d) E0 1D 08 ; inv_llc = 1'b0, drv_llc_pad = 2'b10 E0 05 4A ; CP_VID_STD set to 480p E0 03 86 ; CP free run enabled 44 C9 2D ; Free run based on CP_VID_STD 44 BF 16 ; Free color programmed manually 44 C0 A2 ; Y = 162 for Yellow color 44 C1 8E ; Cr = 142 for Yellow color 44 C2 2C ; Cb = 44 for Yellow color E0 00 70 ; Power down HDMI Rx 44 3E 08 ; uv_dval_inv [3] = 1'b1 (Pr, Pb timing adjust) E0 04 C0 ; CP force free run End :08-18 Forced 720p free run to Pixel Port - SDR8av Out: E0 FF FF ; SW reset delay 5 ; E0 01 76 ; ADI Required Write E0 F2 01 ; Enable I2C read auto-increment E0 F3 4C ; DPLL Map address set to 0x4C E0 F4 44 ; CP Map address set to 0x44 E0 F5 68 ; HDMI RX Map address set to 0x68 E0 F6 6C ; EDID Map address set to 0x6C E0 F7 64 ; HDMI RX Repeater Map address set to 0x64 E0 F8 62 ; HDMI RX Infoframe Map address set to 0x62 E0 F9 F0 ; CBUS Map address set to 0xF0 E0 FA 82 ; CEC Map address set to 0x82 E0 FB F2 ; SDP Main Map address set to 0xF2 E0 FC 90 ; CSI-TXB Map address set to 0x90 E0 FD 94 ; CSI-TXA Map address set to 0x94 E0 00 40 ; Disable chip powerdown & Enable HDMI Rx block 64 40 83 ; enable HDCP 1.1 68 00 08 ; foreground channel = A 68 3D 10 ; ADI Required Write 68 3E 7B ; ADI Required Write 68 3F 5E ; ADI Required Write 68 4E FE ; ADI Required Write 68 4F 08 ; ADI Required Write 68 57 A3 ; ADI Required Write 68 58 04 ; ADI Required Write 68 85 10 ; ADI Required Write 68 83 00 ; Enable all terminations 68 98 FF ; ADI Required Write 68 99 A3 ; ADI Required Write 68 9A 00 ; ADI Required Write 68 9B 0A ; ADI Required Write 68 9D 40 ; ADI Required Write 68 CB 09 ; ADI Required Write 68 A3 01 ; ADI Required Write 68 BE 00 ; ADI Required Write 68 0F 00 ; Audio Mute Speed Set to Fastest (Smallest Step Size) E0 0E DD ; Enable audio pads 68 6C 01 ; HPA manual enable 68 F8 01 ; HPA asserted E0 03 86 ; Insert AV codes, CP Free run Enable E0 04 00 ; CP in YPrPb mode E0 0E 11 ; Enable LLC, Pixel and Audio outputs E0 10 20 ; Enable Pixel port and route from CP core E0 12 F4 ; Output is 8-bit SDR 422 E0 0C FF ; llc_dll_en, llc_ddl_mux, LLC_DLL_double = 1'b1 , llc_dll_phase = 5'b11111 (31d) E0 1D 08 ; inv_llc = 1'b0, drv_llc_pad = 2'b10 E0 05 53 ; CP_VID_STD set to 720p E0 03 86 ; CP free run enabled 44 C9 2D ; Free run based on CP_VID_STD 44 BF 16 ; Free color programmed manually 44 C0 A2 ; Y = 162 for Yellow color 44 C1 8E ; Cr = 142 for Yellow color 44 C2 2C ; Cb = 44 for Yellow color E0 00 70 ; Power down HDMI Rx 44 3E 08 ; uv_dval_inv [3] = 1'b1 (Pr, Pb timing adjust) E0 04 C0 ; CP force free run End :08-19 Forced 1080i free run to Pixel Port - SDR8av Out: E0 FF FF ; SW reset delay 5 ; E0 01 76 ; ADI Required Write E0 F2 01 ; Enable I2C read auto-increment E0 F3 4C ; DPLL Map address set to 0x4C E0 F4 44 ; CP Map address set to 0x44 E0 F5 68 ; HDMI RX Map address set to 0x68 E0 F6 6C ; EDID Map address set to 0x6C E0 F7 64 ; HDMI RX Repeater Map address set to 0x64 E0 F8 62 ; HDMI RX Infoframe Map address set to 0x62 E0 F9 F0 ; CBUS Map address set to 0xF0 E0 FA 82 ; CEC Map address set to 0x82 E0 FB F2 ; SDP Main Map address set to 0xF2 E0 FC 90 ; CSI-TXB Map address set to 0x90 E0 FD 94 ; CSI-TXA Map address set to 0x94 E0 00 40 ; Disable chip powerdown & Enable HDMI Rx block 64 40 83 ; enable HDCP 1.1 68 00 08 ; foreground channel = A 68 3D 10 ; ADI Required Write 68 3E 7B ; ADI Required Write 68 3F 5E ; ADI Required Write 68 4E FE ; ADI Required Write 68 4F 08 ; ADI Required Write 68 57 A3 ; ADI Required Write 68 58 04 ; ADI Required Write 68 85 10 ; ADI Required Write 68 83 00 ; Enable all terminations 68 98 FF ; ADI Required Write 68 99 A3 ; ADI Required Write 68 9A 00 ; ADI Required Write 68 9B 0A ; ADI Required Write 68 9D 40 ; ADI Required Write 68 CB 09 ; ADI Required Write 68 A3 01 ; ADI Required Write 68 BE 00 ; ADI Required Write 68 0F 00 ; Audio Mute Speed Set to Fastest (Smallest Step Size) E0 0E DD ; Enable audio pads 68 6C 01 ; HPA manual enable 68 F8 01 ; HPA asserted E0 03 86 ; Insert AV codes, CP Free run Enable E0 04 00 ; CP in YPrPb mode E0 0E 11 ; Enable LLC, Pixel and Audio outputs E0 10 20 ; Enable Pixel port and route from CP core E0 12 F4 ; Output is 8-bit SDR 422 E0 0C FF ; llc_dll_en, llc_ddl_mux, LLC_DLL_double = 1'b1 , llc_dll_phase = 5'b11111 (31d) E0 1D 08 ; inv_llc = 1'b0, drv_llc_pad = 2'b10 E0 05 54 ; CP_VID_STD set to 1080i E0 03 86 ; CP free run enabled 44 C9 2D ; Free run based on CP_VID_STD 44 BF 16 ; Free color programmed manually 44 C0 A2 ; Y = 162 for Yellow color 44 C1 8E ; Cr = 142 for Yellow color 44 C2 2C ; Cb = 44 for Yellow color E0 00 70 ; Power down HDMI Rx 44 3E 08 ; uv_dval_inv [3] = 1'b1 (Pr, Pb timing adjust) E0 04 C0 ; CP force free run End