======================================================================
                          - WmTSharcIceHP - 
                        ADSP-TSxxx HPPCI-ICE
                 
                           Version 1.00.6
                          
                         Analog Devices, Inc.
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        WmTSharcIceHP is a TigerSHARC JTAG Debug Target for VisualDSP++ 2.0
        or greater.  It will provide full JTAG debug support for all TSx
        processors using the HPPCI-ICE from Analog Devices.

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        Requirements
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        - VisualDSP++ 2.0 or greater with TigerSHARC support
        
        - HPPCI-ICE JTAG emulator from Analog Devices
        
        - Windows 98, Windows NT 4.0 with SP3 or greater, Windows 2000, 
          or Windows XP

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        Installation and Usage Notes
======================================================================
                  
        - Operation under Windows NT, Windows 2000, or Windows XP requires 
          the proper JTAG Emulator Driver from Analog Devices, Inc. to be 
          installed and running.  The driver installation is integrated 
          into the Emulation Tools setup for Windows NT.
                
        - After installation the JTAG ICE Configurator utility MUST be
          run before starting a debug session.
          
        - When switching between different target boards be sure to
          first close the current debugger session, then move the
          emulator pod to the new target and finally start a new debugger
          session on the new target.  "Hot swapping" between different
          target boards using "New Session" or "Select Session" from the 
          debugger menu is not supported by the ICE.

        - User code should be sure to not modify the following bits.  Doing
          so may disable communications with the host.

                - DBGEN or NMOD (bits 8 or 9) in SQCTL

                < TS101 and TS001 only >
                - DBG (bit 31) in IMASKH

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        Features in this release
======================================================================

        - Support for the TS201, TS202, and TS203 processors
        
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        Fixes in this release
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        < TS101 >
        - When interrupts are nested, the SW Exception ISR was not finishing
          execution before another latched interrupt gets serviced.

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        Known Issues
======================================================================

        < TS001 and TS101 only >
        - Under the Settings menu, "Watchpoints..." are not fully functional.
          WP0 with a single address range works, but WP1 and WP2 and monitoring
          for a range of addresses does not work.
          
        - On TS001 choosing 'Reset' or 'Restart' does not fully reset the chip.
          Writable registers with known reset values will be reset, the PC will
          be placed at 0x0, and watchpoints will be disabled.  Read-only
          registers will not be reset and bits in registers that depend upon
          strap options at boot will not be reset either.

        - If an assembly program has a label "_main" at location 0x0 and the
          "Run to Main" menu item is checked, upon loading the program it
          will not stop at "_main", rather it will run past it.

        - Cycle count registers (CCNT0 and CCNT1) are not writable through the
          emulator.  The registers work correctly otherwise they just cannot be
          modified by the emulator.

        < TS001 and TS101 only >
        - The Trace Buffer registers update strangely while single-stepping
          through code.  However the registers contain correct values after
          halting the processor.

        < TS201 Rev 0.0 silicon >
        - Due to silicon eratta 03-00-0248, debugging level-sensitive interrupts 
          is not supported.

        - Due to silicon eratta 03-00-0248, debugging trace buffer overflow
          SW exceptions is not supported.

        - Interrupt control register INTCTL cannot be read because of silicon 
          errata 03-00-0213.  Please make use of the _Save_INTCTL common address.

        - Writing to memory between 0x1FFA0 and 0x20000 is restricted. The emulation 
          software uses this memory for a temporary solution to silicon 
          eratta 03-00-0248.
          
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        Change Log
======================================================================

        Version 1.00.1
                
        - Initial full release

        Version 1.00.0

        - Initial internal release