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                          - WmBlackfinIce - 
                 Blackfin JTAG Emulator Debug Target DLL
                 
                          Version 2.00.0
                          
                        Analog Devices, Inc.
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        WmBlackfinIce is a Blackfin JTAG Debug Target for VisualDSP++ 2.0, or
        greater.  It will provide full JTAG debug support for all 2153x
        processors using an external emulator such as the Summit-ICE or
        Mountain-ICE from Analog Devices.

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        Requirements
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        - VisualDSP++ 2.0, or greater with Blackfin support
        
        - A Summit-ICE or Mountain-ICE Emulator
        
        - Windows 95 OSR2, Windows 98, Windows NT 4.0 with SP3 or greater,
          or Windows 2000
        
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        Installation and Usage Notes
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        - Operation under Windows NT or Windows 2000 requires the proper 
          JTAG Emulator Driver from Analog Devices, Inc. to be installed 
          and running.  The driver installation is integrated into the 
          Emulation Tools setup for Windows NT.
                
        - After installation the JTAG ICE Configurator utility MUST be
          run before starting a debug session.
          
        - When switching between different target boards be sure to
          first close the current debugger session, then move the
          emulator pod to the new target and finally start a new debugger
          session on the new target.  "Hot swapping" between different
          target boards using "New Session" or "Select Session" from the 
          debugger menu is not supported by the ICE.

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        Features in this release
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        - This Third Alpha release supports all the basic debug capabilites.

                - run/halt/step
                - read/write register
                - read/write memory (L1 and L2)
                - software breakpoints
                - hardware breakpoints
                - performance monitor
                - trace buffer
                - statistical profiling
                - memory mapped registers 
                - user selectable between M3 and SP usage. (default SP)
                - user selectable between opcode & raw scan methods. (default OPCODE)
                - user selectable reset levels.  Select between core,
                  system, or both core & system level reset. (default BOTH)
                - added a target option to stall the dsp on exit.
                - added background telemetry channel support
                - Window MemDMA Read Channel and MemDMA Write Channel were interchanged.
                
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        Using M3 as an emulator scratch register
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In some circumstances, such as when debugging stack initialization code, it 
is desirable to reserve a register for the emulator's use.  M3 has been 
designated as the register to use in such circumstances.  The run-time 
libraries have been built to take this into account, but a small number 
of functions save and restore processor context, and these have been built 
in two versions.  They are in the libraries libm3free.dlb and libm3res.dlb.

To link against these libraries as appropriate, define the LIBM3 macro in 
your LDF, as follows:

#ifdef M3_RESERVED
#define LIBM3 libm3res.dlb
#else
#define LIBM3 libm3free.dlb
#endif

and include the LIBM3 macro in the list of libraries to be searched:

#define LIBS libc.dlb, LIBM3, libevent.dlb, ... ,
                

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        Fixes in this release
======================================================================

        - Now compatible with the New configurator
                
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        Known Issues
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        Change Log
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        Revision 1.61.2
        - Fixed SSSTEP and SNEN child registers of system config (TAR-12925)
        - Fixed EXCAUSE child register of Sequencer status (TAR-12923)
        

        Revision 1.60.4

        - Fixed UART0 and UART1 Registers (DLL, DLH, THR, RBR, and IER) so 
          that they update properly in the register window.

        Revision 1.60.3

        - ability to patch code into L1 instruction cache.
        - ability to patch data in L1 data cache
        - ability to set/clear breakpoints in L1 instruction cache
        - memory verification error when setting memory using an
          expression window is fixed.
        - fixed bug in L1 SDRAM that caused inability do download 
          blocks of data/instructions when they started at a non 32
          bit aligned address.
        - Increases download speed to L1 SDRAM memory.
        - changed target options so opcode mode is the default mode
        - fixed bug where the ITEST registers were not being preserved
          when viewing an L1 memory window.
        - changed target options so SP was the default mode.
        - Added Core reset target option
        - Added System reset target option