====================================================================== - WmTSharcIceCE - Apex-Ice USB JTAG Emulator Version 1.65.0 Analog Devices ====================================================================== Apex-Ice is a USB JTAG Debug Emulator for VisualDSP 4.1.x and VisualDSP++ 1.00 or greater. It will provide full JTAG debug support for all TigerSHARC processors using an external emulator through the USB port. ====================================================================== Requirements ====================================================================== - VisualDSP 4.1.x or VisualDSP++ 1.00 or greater. NOTE: Version 4.1.x is still supported but the new statistical profiling feature will not be available. - An Apex-ICE JTAG Emulator - Windows 98, Windows 2000, or Windows XP. ====================================================================== Installation and Usage Notes ====================================================================== - After installation the ApexControl utility must be run to verify correct operation. - After installation the ICE Configurator utility MUST be run before starting a debug session. - When switching between different target boards be sure to first close the current debugger session, then move the emulator pod to the new target and finally start a new debugger session on the new target. "Hot swapping" between different target boards using "New Session" or "Select Session" from the debugger menu is not supported by the ICE. ====================================================================== Downloading files to the Apex-ICE ====================================================================== - After a successful installation, the ApexControl utility must be used to download firmware file updates. The following steps must be completed successfully before using the Apex-ICE: 1.) Launch the ApexControl utility. 2.) Press the connect button to make the connection to the Apex-ICE. 3.) Now press the Firmware Update button. A Firmware Version Dialog will be displayed. 4.) Press Upgrade button to download all firmwares. A download progress dialog will be displayed for each file. 5.) When download finished, ApexICE device will be forced to reboot. ====================================================================== Features in this release ====================================================================== - Support for the TS201, TS202, and TS203 processors ====================================================================== Fixes in this release ====================================================================== < TS101 > - When interrupts are nested, the SW Exception ISR was not finishing execution before another latched interrupt gets serviced. ====================================================================== Known Issues ====================================================================== - The Analog Devices Inc. drivers for EZ-Kits and emulators are not currently digitally signed by Microsoft Corporation, but have been tested within our internal lab and work under the various Windows operating systems. We are currently evaluating and investigating the certification process and its value to our end product. - On WindowsXP, unplug USB cable from one USB port and plug in another USB port would cause New Hardware Found message and have to reinstall USB device driver. < TS001 and TS101 only > - Under the Settings menu, "Watchpoints..." are not fully functional. WP0 with a single address range works, but WP1 and WP2 and monitoring for a range of addresses does not work. - On TS001 choosing 'Reset' or 'Restart' does not fully reset the chip. Writable registers with known reset values will be reset, the PC will be placed at 0x0, and watchpoints will be disabled. Read-only registers will not be reset and bits in registers that depend upon strap options at boot will not be reset either. - If an assembly program has a label "_main" at location 0x0 and the "Run to Main" menu item is checked, upon loading the program it will not stop at "_main", rather it will run past it. - Cycle count registers (CCNT0 and CCNT1) are not writable through the emulator. The registers work correctly otherwise they just cannot be modified by the emulator. < TS001 and TS101 only > - The Trace Buffer registers update strangely while single-stepping through code. However the registers contain correct values after halting the processor. < TS201 Rev 0.0 silicon > - Due to silicon eratta 03-00-0248, debugging level-sensitive interrupts is not supported. - Due to silicon eratta 03-00-0248, debugging trace buffer overflow SW exceptions is not supported. - Interrupt control register INTCTL cannot be read because of silicon errata 03-00-0213. Please make use of the _Save_INTCTL common address. - Writing to memory between 0x1FFA0 and 0x20000 is restricted. The emulation software uses this memory for a temporary solution to silicon eratta 03-00-0248. ====================================================================== Change Log ====================================================================== Revision 1.50.2 < TS001 and TS101 only > - Protect against bringing up more than one VisualDSP++ session on the same emulator. - Added target option to allow watchpoints to be restored after a reset. - Added context-sensitive help to the "Target Options" and "Hardware Watchpoint" dialogs. Revision 1.50.0 < TS001 and TS101 only > - Compatible with the new "VisualDSP++ Configurator" utility. - Fixed issue with "MP Run" and "MP Step" commands if the active MP group did not contain all the DSPs in the platform. - Fixed issue which allowed users to clear the DBGEN or NMOD bits in SQCTL through a register window which would disable debug capabilities with the host. Revision 1.40.4 < TS001 and TS101 only > - Added a new option in the "Target Option" dialog called "Stop DMA". When selected this will stop all DMA when the DSP is halted. The current transaction will complete but subsequent transactions will not be started. When the DSP is set running again the DMA will be re-enabled to the previous user setting. - Fixed issue where two resets were needed in order to reset ILAT and PMASK if interrupts were being served. Now a single reset will correctly reset these registers. - Protect against accidental "load" or "reload" while DSP is running. Revision 1.40.2 < TS001 and TS101 only > - Fixed issue with stepping into interrupt handlers that have their mask bit located in IMASKL. Revision 1.40.1 < TS001 and TS101 only > - Added the Branch Target Buffer (BTB) registers. Note that there are many of these registers so keeping the BTB window open will slow down the ICE especially during opening and closing the debugger. Close the BTB window before closing the debugger to avoid this delay. - Added the TRCBMASK register to the Trace Buffer window which indicates if an entry was a source or target address. - Added bit breakdowns for SQCTL, SQSTAT, and SDRCON registers. - Removed the SYSCTL register which does not exist on the TS101. Revision 1.40.0 < TS001 and TS101 only > - Added a new target option called "Use opcode scans on load" which is accessible through the "Settings->Target Options" menu item. Checking this option will speed up the time it takes to load an executable. - Single stepping into exception and interrupt handlers are now supported. If an exception or interrupt has been latched since halting and a single step command is issued the ICE will vector to the proper service routine. It will appear that the first instruction in the service routine has been skipped because when the ICE halts after the step the PC will be on the second instruction in the service routine. In reality the first instruction of the service routine was the one that was stepped over though, not the instruction that the PC was last pointing to before the step because the ICE will vector prior to executing the single step. - The DBG bit in IMASKH (bit 31) will disable emulation if cleared. The ICE will now not allow this bit to be cleared through a register window. It is possible to clear this bit in user code but doing so will render the ICE useless. Please do not disable this bit in user code while trying to debug. - IMASKH is set to 0x80000000 on a software reset. This is to match the value set by the loader. Note that this value disables GLOBAL interrupts (bit 60) in IMASKH so be sure to enable GLOBAL if interrupts are needed. Stepping an IDLE instruction with GLOBAL disabled will cause the ICE to lose communication with the DSP. - Accesses to SDRAM will not be allowed if SDRAM ENABLE (bit 0) in SDRCON is cleared. SDRCON is one-time writable after a power on reset so be sure to configure it properly if SDRAM accesses will be made. - Cycle count registers (CCNT0 and CCNT1) are not writable through the emulator. The target option to "Reset cycle counters on run" has been disabled and writes to these registers through a register window will generate a warning. These registers work correctly otherwise, they just can't be modified by the emulator. Revision 1.30.1 < TS001 and TS101 only > - Fixed issue with DCNT and DSTAT becoming corrupted if they are displayed in register windows. Also note that the DCNT alias registers (DCNTST and DCNTCL) have been removed from the ICE. - Fixed issue with resetting link ports on ADSP-TS101. - Fixed issue with resetting PMASK on ADSP-TS101. Revision 1.30.0 < TS001 and TS101 only > - Added support for the ADSP-TS101 device type. - Fixed issue with MP stepping over the IDLE instruction. Also note that single stepping over an IDLE instruction is no longer handled by skipping the instruction. Both single and multi-processor stepping over the IDLE instruction are handled by placing a breakpoint on the instruction following the IDLE and running the DSP. The DSP(s) will be in a running state until an interrupt occurs and control returns to the instruction following the IDLE or a software breakpoint inside an interrupt service routine (ISR) is encountered. If users wish to step through ISRs by stepping over IDLE they must set software breakpoints in the appropriate ISRs. Revision 1.20.1 < TS001 and TS101 only > - Added support for the ADSP-TS001 device type. Revision 1.20.0 < TS001 and TS101 only > - Improved overall performance. - More robust handling of MP commands. - Corrected reset value for DSTAT. Revision 1.10.0 < TS001 and TS101 only > - Corrected reset values for the following registers: LSTAT - Added Link Status and Control registers (LSTATx, LCTLx) which can be accessed under the "Register->Custom..." menu item. - Breakpoints can now only be placed at the first instruction of a multi-line instruction. Reapplying breakpoints after modifying a program could previously cause breakpoints to be placed at invalid instructions. - DMA TCB registers are only written to by the ICE if the user modifies them through the debugger. This was causing hang conditions because they were being updated even without user modification. - Single stepping over an IDLE instruction is handled by just skipping over it. Previously the debugger would lose communication and display incorrect data. Revision 1.00.1 < TS001 and TS101 only > - Corrected reset values for the following registers: SQCTL and DC4 through DC13 Revision 1.00.0 < TS001 and TS101 only > - This is the first release.