Uncompromised Linearity from the LTC2185 and ADA4927-1

Introduction

The LTC2185 is a 125Msps 16-bit ADC with excellent noise and linearity performance while only consuming 185mW per channel. It is ideal for demanding low power applications that require excellent AC performance. A high performance ADC like the LTC2185 requires a high performance amplifier driving it to maintain the excellent performance. The ADA4927-1 delivers the linearity performance required by the LTC2185 while only consuming 215mW. The well designed package of the ADA4927-1 allows for a simple layout that reduces parasitic capacitance in the feedback path that can erode the phase margin of the amplifier. This combination of ADC and driver allows excellent performance from 62.5-125MHz a region where other high speed amplifiers are lacking.

LTC2185

The LTC2185 is a two-channel simultaneous sampling parallel ADC which offers a choice of full-rate CMOS, or double data rate (DDR) CMOS/LVDS digital outputs. Pin-compatible speed grade options include 25Msps, 40Msps, 65Msps, 80Msps and 105Msps with approximate power dissipation of just 1.5mW/Msps per channel. It includes popular features such as the digital output randomizer and alternate bit polarity (ABP) mode that minimize digital feedback when using parallel CMOS outputs. Analog full power bandwidth of 550MHz and ultralow jitter of 0.07psRMS allows under-sampling of IF frequencies with excellent noise performance. To maintain this level of performance the LTC2185 needs to be driven with an appropriate amplifier like the ADA4927-1.

ADA4927-1

The ADA4927 is a high speed differential current feedback amplifier. Fabricated on Analog Devices’ silicon-germanium process, the ADA4927-1 has excellent distortion and an input voltage noise of only 1.3nV/√Hz. This allows it to drive high speed ADCs like the LTC2185. The gain of the ADA4927-1 is set with external feedback resistors located next to the input pins. By keeping the feedback pins and input pins close on the package, the ADA4927-1 provides a clean layout and minimizing the parasitic capacitance in the feedback network. This make the ADA4927-1 an ideal choice for driving high performance ADCs, like the LTC2185, from DC to 125 MHz.

Layout

Figure 1 shows a schematic of the ADA4927-1 driving the LTC2185. The corresponding layout is shown in figure 2. The feedback pins on the ADA4927-1 are adjacent to the input pins which minimizes the parasitic capacitance of the feedback node and improves the phase margin of the amplifier. It also Simplifier the layout by making it possible to place feedback resistors directly across the two pins and not having additional trace length in the feedback path. There is a simple filter between the amplifier and ADC that reduces the wideband noise of the amplifier and improves the SNR of the system. This filter also attenuates the sampling glitches from the ADC before they reach the amplifier. This helps keep the output network of the ADA4927 from oscillating in response to these glitches. This filter network can be modified to accommodate a wide range of input bandwidth requirements.

Figure 1: Schematic showing an ADA4927—1 driving one channel of the LTC2185

Figure 1: Schematic showing an ADA4927-1 driving one channel of the LTC2185

Figure 2: Layout showing an ADA4927—1 driving once channel of the LTC2185

Figure 2: Layout showing an ADA4927-1 driving once channel of the LTC2185

Results

Figure 3 and figure 4 show the SNR and SFDR of the LTC2185 and ADA4927-1 combination. The SFDR stays above 67dB out to 125MHz while the SNR is better than 63dB to the same frequency. This combination only consumes 250mW. With a sample rate of 125Msps, this combination provides good performance through the entire 2nd Nyquist zone where other amplifiers begin to have poor linearity.

Figure 3: SNR of the LTC2185 driven with the ADA4927—1

Figure 3: SNR of the LTC2185 driven with the ADA4927-1

Figure 4: SFDR of the LTC2185 driven with the ADA4927—1

Figure 4: SFDR of the LTC2185 driven with the ADA4927-1

Conclusion

Using the ADA4927-1 to drive the LTC2185 provides excellent linearity while keeping the power consumption low. The fact that the ADA4927-1 stays very linear out to 125MHz allows this ADC amplifier combination to be used in demanding communication and medical applications that require the use of the second Nyquist zone of the LTC2185. The pin out of the ADA4927-1 and filter design minimize the complexity of the layout while maintaining excellent performance on a low power budget.

Generic_Author_image

Clarence Mayott

Clarence Mayott is a mixed signal application section leader with over 10 years of experience at Linear Technology.

Beginning with the DC1151, a demo board for the LTC2246H, Clarence has designed nearly all of the high speed ADC demo boards for Linear Technology. These boards have been used for evaluation purposes in a wide range of applications. He designed demo boards with complete signal chains combining amplifiers and ADC combinations to help the end customer evaluate systems more easily. He also designed companion boards, including clock and signal source boards, to help facilitate the evaluation of high speed ADC demo boards. Clarence manages the continued development of PScope, the software used for various pipeline and SAR ADCs.

His expertise in design and layout of demo boards allows him to instruct customers on how to implement high speed ADCs into their own designs. He has worked on many technical areas, including medical, automotive and communications. His experience allows him to see schematic errors, minute layout errors, and other design flaws in designs.

With the release of the LTC2000, Clarence has expanded his knowledge base to include high speed DACs and waveform generation in addition to high speed ADCs. As an application section leader he oversees the continued development of LTDACGen a new software tool for generating complex waveforms for high speed DACs.

He has given technical trainings both within Linear Technology and to potential customers describing how to implement proper signal chains from the antenna through the FPGA.

He received an M.S. in Electrical Engineering from Santa Clara University and a B.S. degree in Electrical Engineering from California State University Polytechnic San Luis Obispo.