Many times the reference designs for high-speed high-resolution SAR ADCs show a relatively high-speed opamp in front of the ADC to drive it. There are good reasons for that: A low output impedance at high frequencies helps absorb the charge kick-back from the ADC’s sample capacitor, and the opamp’s high loop gain at moderate frequencies assures high AC linearity to match the ADC’s excellent harmonic distortion performance.

The problem with many high-speed opamps, however, is that they often consume relatively high supply current, and that they are not always optimized for the best DC performance such as low offset or low 1/f noise. Recently, I wondered what would happen if we’d interface a micro-power precision opamp such as LT6011 (bandwidth: 330kHz) to the LTC2378-18 ADC (18-bit, 1Msps). So we gave it a try.

We hooked up the circuit as shown in Figure 1. The results were surprisingly good. The circuit’s measured INL of +/-1LSB at 18-bits is similar to the spec of the ADC by itself. The SNR of 100dB is within a dB of the ADC datasheet spec. Meanwhile, the LT6011 boasts true DC precision, with a maximum offset voltage of 60uV, and a 1/f noise corner of only 3Hz. Best of all, the LT6011 consumes only 135uA per amplifier, which means that even running off wide supply voltages, the power consumption of the amplifier is much less than the already low power consumption of the ADC.

So is there a catch? Can you always do this? The circuit is legitimate, and I do not hesitate to recommend it to systems designers, under the right circumstances. What are those circumstances?

First of all, notice that we placed a low frequency pole (49Ohm with 10nF, about 325kHz) between the amplifier and the ADC. This makes sure that the relatively high broadband noise density of the opamp does not integrate over a wide bandwidth to limit the ADC’s noise performance. But it also means that the circuit cannot respond quickly to fast-changing input signals. In any case, the LT6011’s sluggish 0.1V/us slew rate wouldn’t allow that anyway. So don’t use this circuit if you expect the signal to change arbitrarily fast for every next sample of the ADC (such as in multiplexed or high-speed pixelated systems).

More subtly, you have to realize that the low bandwidth interface does not allow the ADC’s input sample capacitor to fully settle to 18-bit accuracy in between conversions. Technically, this means that the ADC is not really digitizing a buffered version of the input signal, but instead a voltage that is always a small percentage off from the real input voltage. The beauty though is that this percentage remains fixed, because the LTC2378-18 always fully resets its sample capacitor, and has a very linear front-end. As a result, the effect of not fully settling is merely a small gain error, which becomes indistinguishable compared to the accuracy of a typical voltage reference or feedback resistor ratio. The caveat is that, if you do not always allow the same amount of time in between ADC conversions, that then the circuit will settle the ADC sample capacitor to a greater or lesser extent, depending on how much time has passed since the previous conversion. This can lead to unexpected errors. So don’t use this setup if you plan to clock the ADC using a non-uniform (non-periodic) sampling clock.

In summary, if you think about your system requirements carefully, you may be able to optimize your circuit to benefit from the excellent DC precision and low power consumption of a slower driver opamp, while still getting the performance that you expect from an 18-bit 1Msps ADC.