DS3134 Step-By-Step Configuration-Bridge Mode

Overview
This application note describes an example of how to configure a single T1 port on the DS3134 operating in Bridge Mode. Additionally, this example describes how to construct, send, receive, and check a packet in loopback mode on that port. This application note is presented as a coding example for easy adaptation to end user applications.

The Local Bus can operate in two modes in DS3134:

1. PCI Bridge Mode
2. Configuration Mode

This example has the following configuration:

• Port 1 of the DS3134 is a channelized T1 port. All other ports are not used.
• Port 1 DS0's 0-3 of the DS3134 is assigned to HDLC channel 3. All other port 1 DS0's are unsigned.
• HDLC channel 3 of the DS3134 is assigned four RX FIFO blocks, four TX FIFO blocks, an RX FIFO high water mark of 3, and a TX low water mark of 1.
• A 16-byte packet is constructed in host memory using one TX buffer, one TX descriptor and one TX pending queue entry. Since the DS3134 is in loopback mode, when the packet is transmitted it will also be received by the DS3134. The received packet is written to host memory using one RX buffer, one RX descriptor and one RX done queue entry.
• The host memory is configured as follows:
  1. Receive Side:
     1. RX free queue base address (RFQBA1/0) = 0x10000000
     2. RX done queue base address (RDQBA1/0) = 0x10000100
     3. RX descriptor base address (RDBA1/0) = 0x10000200
     4. RX buffer base address = 0x10001000
  2. Transmit Side:
  1. TX pending queue base address (TPQBA1/0) = 0x10000300
  2. TX done queue base address (TDQBA1/0) = 0x10000400
  3. TX descriptor base address (TDBA1/0) = 0x10000500
  4. TX buffer base address = 0x10002000

write_reg(address, data)

Write the specified data to the specified DS3134 register address

Inputs:

• address = the register address where data is to be written
• data = the data to be written to the specified register

Outputs: None

read_reg(address, data)

Read the contents of the DS3134 register at the specified address

Input: address = the register address which is to be read
Output: data = the value read from the register

write_reg_IS(address, data)

Write the specified data to the specified DS3134 indirect select register and then wait for that register's busy bit to clear before returning

Inputs:

• address = the indirect select register where data is to be written
• data = the data to be written to the specified register

Outputs: None

Function Code:

write_reg(address, data);
bit_check = 0x8000;
while (bit_check & 0x8000)
	read_reg(address, bit_check);

wr_dword(address, data)

Write the specified 32-bit data value to the specified 32-bit host memory address

Inputs:

• address = the host memory address where data is to be written
• data = the data to be written to the specified memory address

Outputs: None

rd_dword(address, data)

Read a 32-bit data value from the specified 32-bit host memory address

Input: address = the host memory address which is to be read
Output: data = the 32-bit data value read from host memory

frame_wait(count)

Provides a delay equal to count number of frame periods where a frame period is 125 microseconds

Input: count = number of frame periods to wait
Outputs: None

1. Reset the DS3134
2. Configure the DS3134
3. Enable the HDLC channel
4. Put the HDLC channel in loopback mode
5. Queue, send, receive, and check a data packet

Reset The DS3134
Resetting the DS3134 consists of two steps. First the internal RAM's of the DS3134 must be zeroed and then the DS3134 internal registers must be reset.

Zero The DS3134 Internal RAM's
The DS3134 internal configuration RAM's are not cleared by resetting the chip and therefore must be manually zeroed. This task is accomplished performing a series of writes to each internal ram in the DS3134 using the appropriate data and indirect select registers of the DS3134. This section details the procedure for accomplishing this task.

// Zero RX configuration and TX configuration RAM's for all ports
for(port=0; port<16; port=port+1)
{
	write_reg(CP0RD + 8*port, 0x0000);
	for(ds0=0; ds0<128; ds0=ds0+1)
	{
		// Set bits 9-8 = 01 to select RX Configuration RAM
		// Set bits 9-8 = 10 to select TX Configuration RAM
		write_reg_IS(CP0RDIS + 8*port, (0x0100 + ds0));
		write_reg_IS(CP0RDIS + 8*port, (0x0200 + ds0));
	}
}

// Zero the RX HDLC channel definition RAM
write_reg(RHCD, 0x0000);
for(channel=0; channel<256; channel=channel+1)
	write_reg_IS(RHCDIS, channel);

// Zero the TX HDLC channel definition RAM
write_reg(THCD, 0x0000);
for(channel=0; channel<256; channel=channel+1)
	write_reg_IS(THCDIS, channel);

// Zero the RX FIFO Starting Block Pointer RAM
write_reg(RFSBP, 0x0000);
for(channel=0; channel<256; channel=channel+1)
	write_reg_IS(RFSBPIS, channel);

// Zero the RX FIFO Block Pointer RAM
write_reg(RFBP, 0x0000);
for(channel=0; channel<256; channel=channel+1)
	write_reg_IS(RFBPIS, channel);

// Zero the RX FIFO High Water Mark RAM
write_reg(RFHWM, 0x0000);
for(channel=0; channel<256; channel=channel+1)
	write_reg_IS(RFHWMIS, channel);

// Zero the TX FIFO Starting Block Pointer registers
write_reg(TFSBP, 0x0000);
for(channel=0; channel<256; channel=channel+1)
	write_reg_IS(TFSBPIS, channel);

// Zero the TX FIFO Block Pointer RAM
write_reg(TFBP, 0x0000);
for(channel=0; channel<256; channel=channel+1)
	write_reg_IS(TFBPIS, channel);

// Zero the TX FIFO Low Water Mark RAM
write_reg(TFLWM, 0x0000);
for(channel=0; channel<256; channel=channel+1)
	write_reg_IS(TFLWMIS, channel);

// Zero the RX DMA configuration RAM
write_reg(RDMAC, 0x0000);
for(channel=0; channel<256; channel=channer+1)
	write_reg_IS(RDMACIS, 0x0400 + channel);

// Zero the TX DMA configuration RAM
write_reg(TDMAC, 0x0000);
for(channel=0; channel<256; channel=channer+1)
	write_reg_IS(TDMACIS, 0x0400 + channel);

// Reset DS3134 using MRID registers master reset bit.
write_reg(MRID, 0x0001);
write_reg(MRID, 0x0000);

1. Configure the PCI registers
2. Configure the Layer 1 registers
3. Configure the HDLC registers
4. Configure the FIFO registers
5. Configure the DMA registers

// This example uses port 1 channel 3
port = 1;
channel = 3;

// RX free queue base address
rfq_base_addr = 0x10000000;

// RX free queue end address
// - RX free queue size = 16
rfq_end_idx = 0x000F;

// RX done queue base address
rdq_base_addr = 0x10000100;

// RX done queue end address
// - RX done queue size = 16
rdq_end_idx = 0x000F;

// RX descriptor base address
// - RX descriptor table size = 256
rdscr_base_addr = 0x10000200;

// RX data buffer base address
rx_buf_base_addr = 0x10001000;

// TX pending queue base address
tpq_base_addr = 0x10000300;

// TX pending queue end address
// - TX pending queue size = 16
tpq_end_idx = 0x000F;

// TX done queue base address
tdq_base_addr = 0x10000400;

// TX done queue end address
// - TX done queue size = 16
tdq_end_idx = 0x000F;

// TX descriptor base address
// - TX descriptor table size = 256
tdscr_base_addr = 0x10000500;

// TX data buffer base address
tx_buf_base_addr = 0x10002000;

// Map DS3134 Configuration Registers to a PCI bus base address
write_reg(PDCM, 32'h80000000);

// PCI command/status register 0 - controls DS3134 DMA functionality
// Set Bit 1 = 1 to enable accesses to internal device configuration registers through PCI
// bus (required for Bridge mode)
// Set Bit 2 = 1 to allow the device operation as bus master on PCI bus (required for DMA)
// Set Bit 6 = 1 to act on parity errors
// Set Bit 8 = 1 to enable the PSERR pin
write_reg(PCMD0, 32'h00000146);

• Assigning the HDLC channel number to the incoming and outgoing data
• Channelized local and network loopbacks
• Channelized selection of 64 kps, 56 kps or no data
• Channelized transmit DS0 channel fill of all ones
• Routing data to and from the BERT function
• Routing data to the V.54 loop pattern detector

// Set RX Port Control Register
// Set bits 2-0 = 000 for clock, data and sync are not inverted
// Set bits 5-4 = 00 for sync pulse 0 clocks early
// Set bits 7-6 = 00 for T1 mode
// Set bit 10 = 0 to disable local loopback
write_reg(RP0CR + 4*port, 0x0000);

// Set TX Port Control Register
// Set bit 2-0 = 000 for clock, data and sync are not inverted
// Set bit 3 = 0 to force all data at TD to be 1
// Set bits 5-4 = 00 for sync pulse 0 clocks early
// Set bits 7-6 = 0 for T1 mode
write_reg(TP0CR + 4*port, 0x0000);

// RX Port Configuration Registers
// DS0's 0-3 disabled, assigned to HDLC channel
// CP[n]RDIS bits 9-8 = 01 for Receive Configuration
write_reg(CP0RD + 8*port, 0x0000 + channel);
for(ds0=0; ds0<4; ds0=ds0+1)
	write_reg_IS(CP0RDIS + 8*port, 0x0100 + ds0);

// TX Port Configuration Registers
// DS0's 0-3 disabled, assigned to HDLC channel
// CP[n]RDIS bits 9-8 = 10 for Transmit Configuration
write_reg(CP0RD + 8*port, 0x0000 + channel);
for(ds0=0; ds0<4; ds0=ds0+1)
	write_reg_IS(CP0RDIS + 8*port, 0x0200 + ds0);

• Zero stuffing and de-stuffing
• Flag detection and byte alignment
• CRC generation and checking
• Data inversion and bit flipping

// RX HDLC configuration
// Set bits 3-2 = 10 for 32-bit CRC
write_reg(RHCD, 0x0008);
write_reg_IS(RHCDIS, channel);

// TX HDLC configuration
// Set bit 1= 0 to select an interfill byte of 7E
// Set bits 3-2 = 10 for 32-bit CRC
// Set bits 11-8 = 1000 for closing flag/no interfill bytes/opening flag
write_reg(THCD, 0x0108);
write_reg_IS(THCDIS, channel);

In this example, four TX FIFO blocks and four RX FIFO blocks are assigned to the HDLC channel. This example also uses an RX FIFO high water mark of 3 and TX FIFO low water mark of 1. The RX FHFO high water mark indicates how many blocks should be written into RX FIFO by the HDLC engines before the DMA will begin sending the data to the PCI Bus. The high water mark setting must be between one block and one less than the number of blocks in the link-list chain for the particular channel involved. The TX FIFO low water mark indicates how many blocks should be left in the TX FIFO before the DMA should begin getting more data from the PCI Bus. The amount of FIFO memory, RX FIFO high water mark, and TX FIFO low water mark required by an HDLC channel to prevent transmit underflows and receive overflows from occurring is application dependent. The TX FIFO and RX FIFO of the DS3134 are configured independently on an HDLC channel basis via the registers listed in the following tables.

// Build the RX FIFO block linked list
// 0->1->2->3->0
for (block=0; block<4; block=block+1)
{
	// Bits 9-0 in RFBP register indicate which block is next in the
	// linked list
	write_reg(RFBP, block+1);
	write_reg_IS(RFBPIS, block);
}

// The last block points to the first block to create a circular linked list
write_reg(RFBP, 0x0000);
write_reg_IS(RFBPIS, 0x0003);

// Assign the circular linked list to a specific channel
write_reg(RFSBP, 0x0000);
write_reg_IS(RFSBPIS, channel);

// Set RX FIFO high water mark for channel to 3
write_reg(RFHWM, 0x0003);
write_reg_IS(RFHWMIS, channel);

// TX FIFO block linked list
// 0->1->2->3->0
for (block=0; block<3; block=block+1)
{
	// Bits 9-0 in RFBP register indicate which block is next in the linked list
	write_reg(TFBP, block+1);
	write_reg_IS(TFBPIS, block);
}

// The last block points to the first block to create a circular linked list
write_reg(TFBP, 0x0000);
write_reg_IS(TFBPIS, 0x0003);

// Assign the circular linked list to a specific channel
write_reg(TFSBP, 0x0000);
write_reg_IS(TFSBPIS, channel);

// Set TX FIFO low water mark for channel to 1
write_reg(TFLWM, 0x0001);
write_reg_IS(TFLWMIS, channel);

This is accomplished using descriptors which are defined as pre-formatted messages passed from the host to the DMA block or vice versa. Via these descriptors, the host informs the DMA about the location and status of packet data to be transmitted, and where to place packet data that is received. The DMA uses these descriptors to tell the host the status of packet data that has been transmitted, and the status and location of packet data that has been received.

On the receive side the host will write to the free queue descriptors informing the DMA where it can place incoming packet data. Associated with each free queue entry is a receive data buffer location and packet descriptor. As the DS3134 uses receive free queue entries to write received packet data to host memory it creates entries in the RX done queue. These RX done queue entries inform the host about the location and status of received data. Refer to the DS3134 data sheet for more detailed information. The host must configure the RX DMA by writing to all the of the registers at the following table:

// RX large buffer size = 256 bytes
write_reg(RLBS, 0x0100);

// RX free queue base address
write_reg(RFQBA0, rfq_base_addr & 0x0000FFFF);
write_reg(RFQBA1, (rfq_base_addr >> 16) & 0x0000FFFF);

// RX free queue large buffer read and write pointers = 0
write_reg(RFQLBRP, 0x0000);
write_reg(RFQLBWP, 0x0000);

// RX free queue small buffer start address = 16
write_reg(RFQSBSA, rfq_end_idx);

// RX free queue small buffer read and write pointers = 0
write_reg(RFQSBRP, 0x0000);
write_reg(RFQSBWP, 0x0000);

// RX free queue end address
write_reg(RFQEA, rfq_end_idx);

// RX done queue base address
write_reg(RDQBA0, rdq_base_addr & 0x0000FFFF);
write_reg(RDQBA1, (rdq_base_addr >> 16) & 0x0000FFFF);

// RX done queue read and write pointers = 0
write_reg(RDQRP, 0x0000);
write_reg(RDQWP, 0x0000);

// RX done queue end address
write_reg(RDQEA, rdq_end_idx);

// RX descriptor base address
write_reg(RDBA0, rdscr_base_addr & 0x0000FFFF);
write_reg(RDBA1, (rdscr_base_addr >> 16) & 0x0000FFFF);

// RX DMA Channel Configuration
// The data in RDMAC register is written to or read from the Receive Configuration RAM
// Set bit 0 = 0 to disable the HDLC Channel
// Set bit 201 = 00 for large buffers only
// Set bit 6-3 = 0000 for 0 byte offset from the data buffer address of the first data buffer
// Set Bit 9-7 = 000 for DMA write to the Done Queue only after packet reception is complete
// Set the HDLC Channel Number by RDMACIS register
write_reg(RDMAC, 0x0000);
write_reg_IS(RDMACIS, 0x0400 + channel);

As the DS3134 processes transmit pending queue descriptor entries it creates transmit done queue descriptor queue entries. The DMA will write to the done queue when it has completed transmitting either a complete packet or data buffer depending on how the DS3134 is configured. Via these done queue descriptors, the DMA informs the host about the status of the outgoing packet data. Refer to the DS3134 data sheet for more detailed information. The host must configure the TX DMA by writing to all the of the registers at the following table:

// TX pending queue base address
write_reg(TPQBA0, tpq_base_addr & 0x0000FFFF);
write_reg(TPQBA1, (tpq_base_addr >> 16) & 0x0000FFFF);

// TX pending queue read and write pointers = 0
write_reg(TPQRP, 0x0000);
write_reg(TPQWP, 0x0000);

// TX pending queue end address
write_reg(TPQEA, tpq_end_idx);

// TX done queue base address
write_reg(TDQBA0, tdq_base_addr & 0x0000FFFF);
write_reg(TDQBA1, (tdq_base_addr >> 16) & 0x0000FFFF);

// TX done queue read and write pointers = 0
write_reg(TDQRP, 0x0000);
write_reg(TDQWP, 0x0000);

// TX done queue end address
write_reg(TDQEA, tdq_end_idx);

// TX descriptor base address
write_reg(TDBA0, tdscr_base_addr & 0x0000FFFF);
write_reg(TDBA1, (tdscr_base_addr >> 16) & 0x0000FFFF);

// TX DMA Channel Configuration
// The data in TDMAC register is written to or read from the Receive Configuration RAM
// Set bit 0 = 0 to disable HDLC Channel
// Set bit 1 = 0 for write done queue after packet transmitted
// Set the HDLC Channel Number by TDMACIS register
write_reg(TDMAC, 0x0000);
write_reg_IS(TDMACIS, 0x0200 + channel);

1. Enable the channel in the port TX and RX configuration RAM's
2. Enable port data transmission in Layer 1
3. Enable TX DMA and RX DMA for the DS3134
4. Enable HDLC channel TX DMA and RX DMA

// Enable packet reception in port layer 1 RX configuration RAM
for (ds0=0; ds0<4; ds0=ds0+1)
{
	// Read the current data value from the RX Configuration RAM
	// Set CP[n]RDIS bits 6-0 = DS0
	// Set CP[n]RDIS bit 14 = 1 to read data from the RAM
	// Set CP[n]RDIS bits 9-8 = 01 to select RX configuration RAM
	write_reg_IS(CP0RDIS + 8*port, 0x4100 + ds0);
	read_reg(CP0RD + 8*port, data);

	// Update memory with new value
	// Set CP[n]RDIS bits 6-0 = DS0
	// Set CP[n]RDIS bit 14 = 0 to write data to the RAM
	// Set CP[n]RDIS bits 9-8 = 01 to select RX configuration RAM
	// Enable DS0 by setting bit 15 = 1 in CP[0]RD register
	write_reg(CP0RD + 8*port, data | 0x8000);
	write_reg_IS(CP0RDIS + 8*port, 0x0100 + ds0);
}

// Enable packet transmission in Port Layer 1 TX configuration RAM
for (ds0=0; ds0<4; ds0=ds0+1)
{
	// Read the current data value from the RX Configuration RAM
	// Set CP[n]RDIS bits 6-0 = DS0
	// Set CP[n]RDIS bit 14 = 1 to read data from the RAM
	// Set CP[n]RDIS bits 9-8 = 10 to select TX configuration RAM
	write_reg_IS(CP0RDIS + 8*port, 0x4200 + ds0);
	read_reg(CP0RD + 8*port, bit_check);
	// Update memory with new value
	// Set CP[n]RDIS bits 6-0 = DS0
	// Set CP[n]RDIS bit 14 = 0 to write data to the RAM
	// Set CP[n]RDIS bits 9-8 = 10 to select TX configuration RAM
	// Enable DS0 by setting bit 15 = 1 in CP[0]RD register
	write_reg(CP0RD + 8*port, bit_check | 0x8000);
	write_reg_IS(CP0RDIS + 8*port, 0x0200 + ds0);
}

// TX port control register
// Set Bit 3 = 1 to allow data to be transmitted normally
read_reg(TP0CR + 4*port, data);
write_reg(TP0CR + 4*port, data | 0x0008);

// Enable TX and RX DMA in the DS3134 master configuration register
// Set bit 0 = 1 to enable Receive DMA
// Set bits 2-1 = 00 to burst length maximum is 32 dwords
// Set bit 3 = 1 to enable Transmit DMA
// Set bits 6 = 1 for HDLC packet data on PCI bus is big endian
// Set bits 11-7 = 00000 to select Port 0 has the dedicated resources of the BERT
write_reg(MC, 0x0049);

// Read the current channel value from the RX DMA Configuration RAM
// Set RDMACIS bits 7-0 = channel
// Set RDMACIS bits 10-8 = 100 to read lower word of dword 2
// Set RDMACIS bit 14 = 1 to read from RAM
write_reg_IS(RDMACIS, 0x4400 + channel);
read_reg(RDMAC, data);

// Enable channel RX DMA
// Update RAM with new value
// Set RDMAC bit 0 = 1 to enable the HDLC channel
// Set RDMACIS bits 7-0 = channel
// Set RDMACIS bits 10-8 = 100 to read lower word of dword 2
// Set RDMACIS bit 14 = 1 to read from RAM
write_reg(RDMAC, data | 0x0001);
write_reg_IS(RDMACIS, 0x0400 + channel);

// Read the current channel value from the TX DMA Configuration RAM
// Set TDMACIS bits 7-0 = channel
// Set TDMACIS bits 11-8 = 0010 to read lower word of dword 1
// Set TDMACIS bit 14 = 1 to read from RAM
write_reg_IS(TDMACIS, 0x4200 + channel);
	read_reg(TDMAC, data);

// Enable channel TX DMA
// Update RAM with new value
// Set TDMAC bit 0 = 1 to enable the HDLC channel
// Set TDMACIS bits 7-0 = channel
// Set TDMACIS bits 11-8 = 0010 to read lower word of dword 1
// Set TDMACIS bit 14 = 0 to write to RAM
write_reg((TDMAC, data | 0x0001);
write_reg_IS(TDMACIS, 0x0200, + channel);

// Wait for at least 5 frame periods for the internal DS3134 initialization to complete frame_wait(5);
// Set Bit 10 = 1 to enable loopback - routes transmit data back to the receive port
read_reg(RP0CR + 4*port, data);
write_reg(RP0CR + 4*port, data | 0x0400);

Initialize The RX Free Queue
Before the DS3134 can DMA received packets from its internal FIFO to host memory, the host must instruct the DS3134 where to put the data. This is done via the RX free queue. Each entry in the RX free queue contains a pointer to an RX data buffer and an RX packet descriptor index. This example uses one RX free queue entry. This entry contains one RX free queue large buffer and one RX packet descriptor. The DS3134 RX large data buffer size has been set to 256 bytes (RLBS = 256). Additionally, the DS3134 has been configured to use a 4-byte CRC and to write the RX CRC into the RX data buffer. Therefore one RX large data buffer is capable of holding up to 252 bytes of packet data.

Offset/Address Acronym Register Name Data Sheet Section 0710 RFQLBWP Receive Free Queue Large Buffer Host Write Pointer 8.1.3 0718 RFQLBRP Receive Free Queue Large Buffer DMA Read Pointer 8.1.3

// check for space in RX large free queue
read_reg(RFQLBWP, wr_ptr);
read_reg(RFQLBRP, rd_ptr);

if (rd_ptr > wr_ptr)
	cnt = rd_ptr - wr_ptr - 1;
else
	cnt = rfq_end_idx - wr_ptr + rd_ptr;

// If room in RX free queue then put 1 entry in the queue
// dword 0 = RX data buffer address
// (use RX data buffer starting at RX buffer area base address)
// dword 1 = corresponding RX descriptor index (use RX descriptor table index 0)
if (cnt > 0)
{
	rx_dscr_idx = 0;
	wr_dword(rfq_base_addr + wr_ptr*8, rx_buf_base_addr);
	wr_dword(rfq_base_addr + wr_ptr*8 + 4, rx_dscr_idx);
	// Advance the RX free queue large buffer write pointer by 1
	write_reg(RFQLBWP, (wr_ptr + 1) % (rfq_end_idx + 1));
}

// Create a 16-byte data packet in memory in a TX buffer whose start address is the TX buffer area base
// address
wr_dword(tx_buf_base_addr, 0x01234567);
wr_dword(tx_buf_base_addr + 4, 0x89ABCDEF);
wr_dword(tx_buf_base_addr + 8, 0x02468ACE);
wr_dword(tx_buf_base_addr + 12, 0x13579BDF);

// Create a TX descriptor (4 dwords) for the packet at TX descriptor
// TX descriptor table index 0
// dword0 = TX buffer address
// dword1 = EOF, CV, byte count, next descriptor pointer
// dowrd2 = HDLC channel
// dword3 = PV, next pending descriptor pointer (set to 0)
tx_dscr_idx = 0;
wr_dword(tdscr_base_addr + tx_dscr_idx*16, tx_buf_base_addr);
wr_dword(tdscr_base_addr + tx_dscr_idx*16 + 4, 0x80100000);
wr_dword(tdscr_base_addr + tx_dscr_idx*16 + 8, 0x00000000 + channel);
wr_dword(tdscr_base_addr + tx_dscr_idx*16 + 12, 0x00000000);

// Read SDMA register to clear any previously set status bits
read_reg(SDMA, data);

// check free space in TX pending queue
read_reg(TPQWP, wr_ptr);
read_reg(TPQRP, rd_ptr);

if (rd_ptr > wr_ptr)
	cnt = rd_ptr - wr_ptr - 1;
else
	cnt = rfq_end_idx - wr_ptr + rd_ptr;

// If room in the TX pending queue create an entry for the packet
if (cnt > 0)
{
	wr_dword(tpq_base_addr + wr_ptr*4, 0x0000000 + (channel << 16));

	// Advance the TX pending queue write pointer
	write_reg(TPQWP, (wr_ptr + 1) % (tpq_end_idx + 1));
}

// wait 2 frame periods for packet to be transmitted/received
frame_wait(2);

// Check SDMA register
// Expected value = 0x6440, if not, it means there was error
read_reg(SDMA, data);

// Check to see how many entries are in the TX done queue (distance from TDQRP to TDQWP)
// Expected value is 1 - one entry in the TX done queue corresponding to the packet that was sent
read_reg(TDQRP, rd_ptr);
read_reg(TDQWP, wr_ptr);

if (wr_ptr >= rd_ptr)
	cnt = wr_ptr - rd_ptr;
else
	cnt = tdq_end_idx + 1 - rd_ptr + wr_ptr;

// Check TX done queue descriptor
// Expected value = 0x0003000
// Bits 15-0 indicates the descriptor pointer
// Bits 23-16 indicate the channel number, it should be 3 in this example
// Bits 28-26 indicate the packet status, all 0 means the packet transmission is complete and the descriptor
// pointer field corresponds to the first descriptor in the HDLC packet that has been transmitted
rd_dword(tdq_base_addr + rd_ptr*4, tdq_entry);

// Advance the TX done queue read pointer
write_reg(TDQRP, (rd_ptr + 1) % (tdq_end_idx + 1));

// Check the RX large free queue to see how many RX buffers are in the queue (distance from RFQLBRP
// to RFQLBWP)
// Expected number is 0 since the queue had 1 buffer before the packet was received and packet reception
// required 1 buffer
read_reg(RFQLBRP, rd_ptr);
read_reg(RFQLBWP, wr_ptr);

if (wr_ptr >= rd_ptr)
	cnt = wr_ptr - rd_ptr;
else
	cnt = rfq_end_idx + 1 - rd_ptr + wr_ptr;

// Check RX done queue to see if any packets were received (distance from RDQRP to RDQWP)
// Expected value is 1 - one entry in the RX done queue entry corresponding to the one packet that should
// have been received
read_reg(RDQRP, rd_ptr);
read_reg(RDQWP, wr_ptr);

if (wr_ptr >= rd_ptr)
	cnt = wr_ptr - rd_ptr;
else
	cnt = rdq_end_idx + 1 - rd_ptr + wr_ptr;

// Check the RX done queue descriptor
// Expected value = 0x40030000,
// Bits 15-0 indicates the descriptor pointer
// Bits 23-16 indicate the channel number, it should be 3 in this example
// Bits 26-24 indicate the buffer count, all 0 means that a complete packet has been received
rd_dword(rdq_base_addr + 8*rd_ptr, rdq_entry);

// Check the corresponding RX descriptor (4 dwords)
// dword 0 expected value = 0x10001000 the RX buffer address
// dword 1 expected value = 0x80140000
// Bits 15-0 is the next descriptor pointer
// Bits 28-16 is the number of bytes stored in the data buffer
// Bits 31-29 indicates buffer status
// dword 2 excepted value = 0x000B7503
// Bits 7-0 indicates HDLC channel number (should match TDQ entry channel)
// Bits 31-8 indicates the timestamp (can vary)
rdscr_idx = rdq_entry & 0x0000FFFF;
rd_dword(rdscr_base_addr + 16*rdscr_idx, rdscr_dword0);
rd_dword(rdscr_base_addr + 16*rdscr_idx + 4, rdscr_dword1);
rd_dword(rdscr_base_addr + 16*rdscr_idx + 8, rdscr_dword2);

// Check the data in the RX buffer
// 16 bytes of data + 4-byte CRC
// Expected values = 0x01234567
// 0x89ABCDEF
// 0x02468ACE
// 0x13579BDF
// 0x05127B09 (4-byte CRC)
byte_count = (rdscr_dword1 >> 16) & 0x00001FFF;
for (addr=rdscr_dword0, addr<rdscr_dword0+byte_count; addr=addr+4)
	rd_dword(addr, data);

// Advance the RX done queue read pointer
write_reg(RDQRP, (rd_ptr + 1) % (rdq_end_idx + 1));