Doc ID: DOC-1762

Change

For the PWM_CHANCFG Configuration registers, the timer options are:

• PWMAH \ AL – Timer 0 & Timer 1
• PWMBH \ BL – Timer 0 & Timer 2
• PWMCH \ CL – Timer 0 & Timer 3
• PWMDH \ DL – Timer 0 & Timer 4

In Table 18-37:

For PWM_CHANCFG.REFTMRD, the bit description should be:

The PWM_CHANCFG.REFTMRD bit selects whether the PWM uses PWMTMR0 or PWMTMR4 as the reference timer for Channel D operation.

The enumerations description should be:

0 = PWMTMR0 is Channel D reference

1 = PWMTMR4 is Channel D reference

For PWM_CHANCFG.REFTMRC, the bit description should be:

The PWM_CHANCFG.REFTMRC bit selects whether the PWM uses PWMTMR0 or PWMTMR3 as the reference timer for Channel C operation.

The enumerations description should be:

0 = PWMTMR0 is Channel C reference

1 = PWMTMR3 is Channel C reference

For PWM_CHANCFG.REFTMRB, the bit description should be:

The PWM_CHANCFG.REFTMRB bit selects whether the PWM uses PWMTMR0 or PWMTMR2 as the reference timer for Channel B operation.

The enumerations description should be:

0 = PWMTMR0 is Channel B reference

1 = PWMTMR2 is Channel B reference

Doc ID: DOC-1703

Change

If a system reset occurs while the debugger is performing a system MMR access, the MMR transaction is lost completely.

Last Update Date: 2018年05月07日