Documentation Errata for ADSP-BF51x Blackfin® Processor Hardware Reference
Chapter: 2 / Page 2
Doc ID: DOC-1501
In Table 2-1, the ending address for starting address
0xFF80 8000 is incorrect. Instead of
0xFF9F FFFF, the ending address should be
Chapter: 8 / Page 4
Doc ID: DOC-1427
The statement "The reset value of
0x5." is incorrect. The reset value of
MSEL is actually
In addition, in Figure 8-4 on page 8-21, the binary value of the register should be
0000 1100 0000 0000 and the hexadecimal reset value should be
Chapter: 18 / Page 1
Doc ID: DOC-1532
The SPI Serial Flash chapter now requires the following disclaimer:
Warning: This chapter describes the SPI flash memory in ADSP-BF51x processors whose part numbers end in 4F4. If the part number of your ADSP-BF51x processor ends in 4F16, please consult the product data sheet for accurate information regarding the SPI flash memory.
Chapter: 20 / Page 15
Doc ID: DOC-1758
Under the "1, 2, or 3 External Frame Syncs" heading, the first statement erroneously indicates that the frame sync signals are level-sensitive.
The statement should read "The frame syncs are edge-sensitive signals.".
Last Update Date: 2018年03月15日