Doc ID: DOC-1421

Change

In the section External Interface, the clock value should be changed from 133 MHz to 100 Mhz as follows:

When clocked internally, the clock source is the processor’s peripheral clock (SCLK). Assuming the peripheral clock is running at 100 MHz, the maximum period for the timer count is ((2³²-1) / 100 MHz) = 43 seconds.

Doc ID: DOC-1422

Change

In the section Input Noise Filtering (Debouncing), the clock value should be changed from 133 MHz to 100 MHz, and the equations for filter time range should be changed as follows:

Assuming an SCLK frequency of 100 MHz, the filter time range is shown by the following equations:

DPRESCALE = 0b0000
          tfilter = 128*1*10ns = 1.28µs

DPRESCALE = 0b10001
          tfilter = 128*(131072)*10ns = 167772us = (approx.) 168ms

Doc ID: DOC-1417

Change

In the section Bit Rate Generation, change the title for Table 15-2 to UART Bit Rate Examples With 100 MHz SCLK, and replace the table as follows:

Bit Rate	Dfactor = 16			Dfactor = 1
	DL	Actual	%Error	DL	Actual	%Error
2400	2604	2400.15	0.006	41667	2399.98	0.001
4800	1302	4800.31	0.006	20833	4800.08	0.002
9600	651	9600.61	0.006	10417	9599.69	0.003
19200	326	19171.78	0.147	5208	19201.23	0.006
38400	163	38343.56	0.147	2604	38402.46	0.006
57600	109	57339.45	0.452	1736	57603.69	0.006
115200	54	115740.74	0.469	868	115207.37	0.006
921600	7	892857.14	3.119	109	917431.19	0.452
1500000	4	1562500.00	4.167	67	1492537.31	0.498
3000000	2	3125000.00	4.167	33	3030303.03	1.010
6250000	1	6250000.00	0.000	16	6250000.00	0.000

Doc ID: DOC-1423

Change

In the section Serial Clock Signal (SCL), the clock value should be changed from 133 MHz to 83 MHz, and the example should be changed as follows:

Note: It is not always possible to achieve 10 MHz accuracy. In such cases, it is safe to round up the PRESCALE value to the next highest integer. For example, if SCLK is 83 MHz, the PRESCALE value is calculated as 83 MHz/10 MHz = 8.3. In this case, a PRESCALE value of 9 ensures that all timing requirements are met.

Doc ID: DOC-1424

Change

In the section Code-Generated Transfer, the SCLK and SPI clock values in the comments to the SPI_Register_Initialization function in Listings 18-1 and 18-6 should be changed as follows:

SPI_Register_Initialization:
P0.H = hi(SPI_FLG);
P0.L = lo(SPI_FLG);
R0 = W[P0] (Z);
BITSET (R0,0x7); /* FLS7 */
W[P0] = R0; /* Enable slave-select output pin */

P0.H = hi(SPI_BAUD);
P0.L = lo(SPI_BAUD);
R0.L = 0x208E; /* Write to SPI Baud rate register */
W[P0] = R0.L; ssync; /* If SCLK = 100 MHz, SPI clock ~= 6 kHz
*/

Last Update Date: 2017年05月25日