Documentation Errata for ADSP-BF50x Blackfin ® Processor Hardware Reference
Chapter: 10 / Page 3
Doc ID: DOC-1421
In the section External Interface, the clock value should be changed from 133 MHz to 100 Mhz as follows:
When clocked internally, the clock source is the processor’s peripheral clock (
Assuming the peripheral clock is running at 100 MHz, the maximum period for the timer count is ((232-1) / 100 MHz) = 43 seconds.
Chapter: 13 / Page 8
Doc ID: DOC-1422
In the section Input Noise Filtering (Debouncing), the clock value should be changed from 133 MHz to 100 MHz, and the equations for filter time range should be changed as follows:
SCLK frequency of 100 MHz, the filter time range is shown by the following equations:
DPRESCALE = 0b0000 tfilter = 128*1*10ns = 1.28µs DPRESCALE = 0b10001 tfilter = 128*(131072)*10ns = 167772us = (approx.) 168ms
Chapter: 15 / Page 19
Doc ID: DOC-1417
In the section Bit Rate Generation, change the title for Table 15-2 to UART Bit Rate Examples With 100 MHz SCLK, and replace the table as follows:
|Dfactor = 16||Dfactor = 1|
Chapter: 16 / Page 4
Doc ID: DOC-1423
In the section Serial Clock Signal (SCL), the clock value should be changed from 133 MHz to 83 MHz, and the example should be changed as follows:
Note: It is not always possible to achieve 10 MHz accuracy.
In such cases, it is safe to round up the
PRESCALE value to the next highest integer.
For example, if
SCLK is 83 MHz, the
PRESCALE value is calculated as 83 MHz/10 MHz = 8.3.
In this case, a
PRESCALE value of 9 ensures that all timing requirements are met.
Chapter: 18 / Page 45
Doc ID: DOC-1424
In the section Code-Generated Transfer, the SCLK and SPI clock values in the comments to the SPI_Register_Initialization function in Listings 18-1 and 18-6 should be changed as follows:
SPI_Register_Initialization: P0.H = hi(SPI_FLG); P0.L = lo(SPI_FLG); R0 = W[P0] (Z); BITSET (R0,0x7); /* FLS7 */ W[P0] = R0; /* Enable slave-select output pin */ P0.H = hi(SPI_BAUD); P0.L = lo(SPI_BAUD); R0.L = 0x208E; /* Write to SPI Baud rate register */ W[P0] = R0.L; ssync; /* If SCLK = 100 MHz, SPI clock ~= 6 kHz */
Last Update Date: 2017年05月25日