1. Data Sheet Errata

Documentation Errata for ADSP-214xx SHARC® Processor Hardware Reference

Chapter: 7 / Page 47

Doc ID: DOC-1428

Change

The following incorrect statement occurs under the Chained DMA heading:

For chained DMA, if the PCI bit is cleared (= 0), the DMA complete interrupt is generated only after the entire chained DMA access is complete. If the PCI bit is set (=1), then a DMA interrupt is generated for each TCB.

The correct information is:

For chained DMA, if the CCINTR (channel complete interrupt) bit is cleared (=0), the DMA complete interrupt is generated only after the entire chained DMA access is complete. If the CCINTR bit is set (=1), then a DMA interrupt is generated for each TCB.

The same correction applies to the information on page 7-71.

Chapter: 7 / Page 74

Doc ID: DOC-1709

Change

There are several corrections for the IIR Throughput section.

The expression:

(TCB load + 5 × B × W) × C is incorrect and should be changed to

(TCB load + 5 × B × W) × C - 7

The following sentence in the information bullet is incorrect:

14 PCLK cycles are required for TCB loading for coefficients and save state operation.

Replace this with:

The total number of PCLK cycles required for the initial coefficient load are as follows:

(18 + B × 14) × C for odd number of biquad stages OR

(17 + B × 14) × C for even number of biquad stages

Chapter: 13 / Page 8

Doc ID: DOC-1514

Change

In Digital Servo Loop, the following information is incomplete:

The digital-servo loop must be able to provide excellent rejection of jitter on the ASRCx_FS_IP and ASRCx_FS_OP clocks as well as measure the arrival of the ASRCx_FS_OP clock within 5 ps.

The correct information is:

The digital-servo loop must be able to provide excellent rejection of jitter on the ASRCx_FS_IP and ASRCx_FS_OP clocks as well as measure the arrival of the ASRCx_FS_OP clock within 5 ps. The jitter rejection begins at less than 1 Hz.

Chapter: 13 / Page 15

Doc ID: DOC-1425

Change

The description of dithering mode requires clarification. The accurate description is:

For the 140 dB ASRC, the DITHER_EN bit controls whether dithering is added when word lengths less than 24 bits are selected. No dithering is added when DITHER_EN is disabled.

For the 128 dB ASRC, serial output data is dithered down to 20, 18, or 16 bits when 20-, 18-, or 16-bit output data is selected and the DITHER_EN bit is set. In the case of 20-, 18- and 16-bit word lengths, the least significant bits of the 24-bit word coming from the SRC into the serial output port are truncated. For the 24-bit word length, DITHER_EN is not applicable. Even when the DITHER_EN signal is cleared, it automatically adds dithering to the 24-bit word before truncating to the appropriate output word length in order to reduce the dynamic range of the ASRC to 128 dB. The type of dithering applied to digital audio samples is not user-configurable.


Last Update Date: 2017年05月08日