Documentation Errata for ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573: SHARC+ Dual-Core DSP with Arm® Cortex-A5 Data Sheet

Chapter: / Page 24

Doc ID: DOC-1787


In Table 11, ADSP-SC57x/ADSP-2157x Detailed Signal Descriptions, the direction of the C1_FLG[n] and C2_FLG[n] pins is incorrect.

The correct direction for both pins is InOut.

Chapter: / Page 41

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In Table 20, ADSP-SC57x/ADSP-2157x 176-Lead LQFP Signal Descriptions, the Description column for signal SYS_FAULT is incorrect. The correct pin description is Active-Low Fault Output.

Chapter: / Page 49

Doc ID: DOC-1812


In Table 25, ADSP-SC57x/ADSP-2157x Designer Quick Reference, the note in the Description and Notes column for the JTG_TRST signal should read:


The JTG_TRST signal must be held low during power-up until all power supplies are stable.

Chapter: / Page 57

Doc ID: DOC-1780


In the second row of Table 26, TWI_VSEL Selections and VDD_EXT/VBUSTWI, the TWI_VSEL selection should be TWI111, not TWI100.

Table 26 should also include the following footnote:

TWI_VSEL is the TWI voltage select field in the PADS_PCFG0 register. See the ADSP-SC57x/ADSP-2157x SHARC+ Processor Hardware Reference.

Chapter: / Page 82

Doc ID: DOC-1891


There are errors in footnote 2 and footnote 3 in Table 54, LPs–Receive.

Footnote 2 should read:

This specification indicates the minimum instantaneous width or period that can be tolerated due to duty cycle variation or jitter on the external LPx_CLK. For the external LPx_CLK ideal maximum frequency, see the fLCLKREXT specification in Table 27. For LPx_CLK generated by ADSP-215xx/ADSP-SC5xx link ports transmit and connected to link ports receive, the width or period requirement can be taken from Table 55, LPs–Transmit.

Footnote 3 should read:

LPx_ACK goes low with tDLALC relative to fall of LPx_CLK after first byte, but does not go low if the link buffer of the receiver is not about to fill.

Chapter: N/A / Page 140

Doc ID: DOC-1801


The following models are now available. They will be added to the Automotive Products table (Table 99) in the next revision (Rev C) of the data sheet.

Model Processor Instruction Rate (Max) ARM Instruction Rate (Max) Temperature Range ARM Cores SHARC+ Cores External Memory Ports Package Description Package Option
ADSC570WCSWZ5xx 500 MHz 500 MHz -40℃ to +105℃ 1 1 0 176-Lead LQFP_EP SW-176-5
ADSC572WCBCZ5xx 500 MHz 500 MHz -40℃ to +105℃ 1 1 1 400-Ball CSP_BGA BC-400-2

Last Update Date: 2023年08月14日