Doc ID: DOC-1787

Change

In Table 11, ADSP-SC57x/ADSP-2157x Detailed Signal Descriptions, the direction of the C1_FLG[n] and C2_FLG[n] pins is incorrect.

The correct direction for both pins is InOut.

Doc ID: DOC-1812

Change

In Table 25, ADSP-SC57x/ADSP-2157x Designer Quick Reference, the note in the Description and Notes column for the JTG_TRST signal should read:

 

The JTG_TRST signal must be held low during power-up until all power supplies are stable.

Doc ID: DOC-1780

Change

In the second row of Table 26, TWI_VSEL Selections and V_{DD_EXT}/V_BUSTWI, the TWI_VSEL selection should be TWI111, not TWI100.

Table 26 should also include the following footnote:

TWI_VSEL is the TWI voltage select field in the PADS_PCFG0 register. See the ADSP-SC57x/ADSP-2157x SHARC+ Processor Hardware Reference.

Doc ID: DOC-1801

Change

The following models are now available. They will be added to the Automotive Products table (Table 99) in the next revision (Rev C) of the data sheet.

Model	Processor Instruction Rate (Max)	ARM Instruction Rate (Max)	Temperature Range	ARM Cores	SHARC+ Cores	External Memory Ports	Package Description	Package Option
ADSC570WCSWZ5xx	500 MHz	500 MHz	-40℃ to +105℃	1	1	0	176-Lead LQFP_EP	SW-176-5
ADSC572WCBCZ5xx	500 MHz	500 MHz	-40℃ to +105℃	1	1	1	400-Ball CSP_BGA	BC-400-2

Last Update Date: 2020年03月19日