ADI Clocks: Optimizing and Supporting JESD204B Interfaces

Clock jitter attenuators are designed to support the JESD204B serial interface standard for connecting high-speed data converters and field-programmable gate arrays (FPGAs) operating in base station designs. The JESD204B interface was specifically developed to address high-data rate system design needs, ADI's clock jitter attenuators contain the functions that support and enhance the unique capabilities of that interface standard.


  • Presenter
  • Jeff Keip

    Senior Marketing Manager, High Speed DDS Portfolio

Jeff Keipは、半導体業界で20年ほどの経験があります。そのうち15年以上、周波数合成製品に取り組んできました。この9年間はアナログ・デバイセズの高速DDS製品シリーズの責任者として活躍しています。

  • Presenter
  • Tunc Cenger

    Product Line Director

Tunc Cenger is Product Line Director, Frequency Generation and High Data Rate at Analog Devices. He has over 15 years experience in the semiconductor industry, graduated with a BSEE from Istanbul Technical University and has one patent.