MT-101: Decoupling Techniques2/14/2015
MT-023: ADC Architectures IV: Sigma-Delta ADC Advanced Concepts and Applications2/14/2015
MT-022: ADC Architectures III: Sigma-Delta ADC Basics2/14/2015
MT-075: 高速 ADC 向け差動ドライバの基礎と応用2/3/2009
MT-074: 高精度 A/D コンバータ用の差動ドライバ2/3/2009
- 24 bit, 4 channel simultaneous sampling system
- High dynamic range with high crosstalk isolation
- Daisy chain configuration minimizes digital lines to host
The circuit shown in Figure 1 provides a high dynamic range four channel simultaneous sampling system with high crosstalk isolation, flexible sampling rates, minimal external components, and simple interface connections to a DSP or FPGA. The circuit uses four AD7765 24-bit sigma-delta ADCs in a daisy chain configuration to minimize the number of connections to the digital host. The AD7765’s fully integrated differential input/output amplifier, and reference buffer significantly reduce the external component requirement.
Using the AD7765 configured in a simultaneous sampling configuration provides
- Channel-to-channel crosstalk isolation superior to that of solutions that integrate multiple 24-bit ADCs on a single chip.
- 112 dB dynamic range at 156 kSPS.
- Adaptable to greater or smaller channel counts.
- Allows multiple SYNC control (can be phase shifted with respect to each other).
- Dual decimation rates (128 and 256) and flexible sampling clock handles wide range of input bandwidths.
Each of the four AD7765 devices is clocked with a common sampling clock (MCLK), synchronization signal (SYNC), and reset signal (RESET) shown in Figure 1. A common 4.096 V reference supplied from ADR444 using the circuit shown in Figure 5 is applied using a star point configuration to each AD7765 (each ADC has an internal reference buffer).
On power up, apply a RESET pulse to all devices (minimum low time of pulse is 1 × MCLK period). The RESET rising edge (which takes the ADC out of reset) is applied to each AD7765 synchronous with the MCLK falling edge. Then a SYNC pulse (minimum low time 4 × MCLK periods) is applied to all AD7765 devices. The SYNC signal acts to gate the AD7765 digital filter (when it is a logic low). On the first MCLK falling edge after SYNC returns to logic high, the AD7765 digital filter starts to process samples internally.
The SYNC function accomplishes two things:
Once all devices are synchronized all ADCs can be configured. Operating in a daisy chain requires that all ADCs use the same decimation rate (controlled by pin 18), and power mode (controlled by writing to the control register Address 0x0001) settings. This ensures that the data from each device is output simultaneously.
To write to all four devices in the chain, a common FSI (frame sync input) signal is applied to all the AD7765 devices. A write to the AD7765 is comprised of 32 bits (16 address bits, 16 register bits). FSI frames the data to the devices. Writing to all four devices, the SDI input to the chain is loaded with a single data write instruction—i.e., when FSI goes low, 32 bits are written to SDI (serial data input) of AD7765 (4).
The example shown in this note operates in normal power mode in decimate by 128 mode (maximum output data rate of 156 kSPS).
Reading Data from the Daisy Chain
Only one FSO (frame sync output) signal is applied to the digital host as the interrupt for reading data from the chain (FSO (1)). This signal is the frame signal for all four channels. The format of the data read back by the digital host (FPGA or DSP) is shown in Figure 3. Conversion data and status bits from AD7765 (1) are clocked out first (FSO (1) is active low during this time). Data and status bits follow from AD7765 (2), (3), and (4), respectively. Note that FSO (1) will be logic high when the data results from remaining converters in the chain are being clocked out.
The next transition of FSO (1) from logic high to logic low signals that the next set of samples from all four channels are ready to be read back. The digital host is required to begin reading back on the FSO (1) falling edge, and read back 4 × 32 bits, i.e., 128 bits from the SDO (1) serial output. Data output on SDO (serial data output) is synchronous with the SCO (serial clock output).
The AD7765 daisy chain circuit allows the user to simultaneously sample up to four channels at 156 kSPS. The speed of the output data rate can be changed by either reducing the MCLK frequency or changing the decimation rate of the AD7765. It is advised that the ADCs be re-synchronized following a change in the decimation rate. Figure 4 show the FFT from the output of AD7765 (3) running at the maximum sampling rate of 156 kSPS operating from an MCLK frequency of 40 MHz. A −0.5 dBFS input is applied to the AD7765 differential amplifier inputs with a 1 kHz input frequency.
Figure 5 shows the FFT output of AD7765 (3) running at a sampling rate of 97.65 kSPS operating from an MCLK frequency of 25 MHz with a 1 kHz (−0.5 dBFS) input. Table 1 shows the performance of the AD7765 at 40 MHz, 30 MHz, 25 MHz, and 20 MHz for Normal Power.
|MCLK (MHz)||20 MHz||25 MHz||30 MHz||40 MHz|
−3 dB PASS-BAND
ANALOG INPUT BW
|31.25 kHz||39.0625 kHz||46.3875 kHz||62.5 kHz|
The signal source was an Audio Precision SYS2522 analog output, balanced GND, 7.699 V p-p output, 40 Ω output impedance, high accuracy mode. The analog input was applied directly to the AD7765 integrated differential amplifier. The FFT sample size was 131,072.
One of the main performance benefits of implementing multi-channel simultaneous sampling with discrete ADCs rather than integrated components is the crosstalk performance. Table 2 shows the crosstalk on adjacent AD7765 channels when a −0.5 dB, 1 kHz input is applied to AD7765 (2).
|AD7765 (1)||AD7765 (2)||AD7765 (3)||AD7765 (4)|
|Pins 1 and
| −0.5 dBFS
|Pins 1 and
Pins 1 and
The ADR444 is a 4.096 V reference supply to each of the AD7765 devices in this circuit. One of the benefits of the AD7765 is that it has an on-board reference buffer, which isolates the user from the internal reference sampling circuitry. This means that no external buffer is required for the case where multiple devices share the same reference. The star point configuration shown in Figure 6 allows the reference voltage to be applied from parallel traces to each ADC from a single point. This is the best practice for minimizing any potential interactions between the ADCs. The reference voltage is serially tapped from a common reference trace to each device. The on-chip reference buffer also isolates the internal dynamic switched capacitor loads from the star point.
The circuit described is a scalable design in that it easily allows the user to adapt to new operating or application conditions. If only two or three ADC channels are required, the last ADC in the chain can be eliminated, and the SDI for the chain simply routed to Device (3).
There is flexibility in setting the sampling rates of the individual devices to handle different bandwidths. For example, the user can split the chain up into two sets of two channels each by routing a separate SYNC signal to each channel, or by simply using the decimation rate pin to change the effective sampling rate. In such an implementation, there is also a pin-for-pin replacement part, the AD7764, which allows the user to sample at up to 312 kSPS with a two-channel daisy chain.
Details on the layout of the PC board for AD7765 are described in the data sheet, with emphasis on the decoupling of supplies and the reference on the right hand side of the device. The Gerber files for the AD7765 evaluation board is available at www.analog.com by navigating to the Evaluation Board section on the AD7765 product page.