73M1866B/73M1966B PCM Connectivity

要約

In contrast to equipment that use the frame-sync (FS) reference method, Teridian's 73M1866B and 73M1966B MicroDAA® devices employ the first falling PCM clock (PCLK) edge after the FS assertion to reference their timing. This article describes the 73M1866B/73M1966B's features and explains how to use the devices with equipment that are designed with the FS reference method in mind.

Introduction

Some PCM equipment reference their timing on the PCM clock (PCLK) rising edge that precedes the first falling edge of PCLK that follows the assertion of frame sync (FS). This document refers to this timing method as the frame-sync reference method. The 73M1866 and 73M1966 use the first falling PCLK edge after the assertion of FS to reference their timing. This application note describes how to configure and use the 73M1x66 with equipment that uses the frame-sync reference method.

The 73M1866B/73M1966B PCM highway benefits from the following features, which ensure connectivity with all PCM interfaces:

  • Linear and compressed modes.
  • Master and slave modes.
  • Transmit time and clock slots.
  • Receive time and clock slots.
  • Transmit and receive edge selection.
  • Half bit drive for bit 0.
  • PCLK frequency selection.
  • PCM transmit enable.

FS reference timing equipment and the 73M1866B/73M1966B have different numbering schemes to designate the time at which PCM data is transmitted to or received from the PCM highway.

The key parameters to align between FS reference timing equipment and the 73M1866B73M1966B are the time and clock slots and the clock edge polarity for receive and transmit paths. Within a PCM frame, the transmission (reception) of an 8- or 16-bit data sample can start at any bit slot during that frame and with respect to either the rising or falling edges of PCLK. The 73M1866B/73M1966B bit numbering is slightly off from that of FS reference timing equipment, thus requiring mapping between the two numbering schemes.

Other parameters, such as linear and compressed modes, LSB half-bit drive, master and slave modes, and PCM enable do not need any translation between timing reference modes.

The 73M1866B/73M1966B PCM settings must be complementary to those of PCM. In other words, FS reference timing transmitter settings define what the 73M1866B/73M1966B receiver PCM settings must be. The same applies to FS reference timing receiver settings and the 73M1866B/73M1966B transmitter settings. The conversion is illustrated in Table 1 and Table 2.

Introduction

The ability to measure Neutral Currents is a key feature to enable the user to enhance tamper detection techniques. The current demo board firmware has the capability to measure Neutral Currents using the Compute Engine (CE) Firmware. All that is required is a minor modification to the existing demo board and firmware, which will be discussed below.

To measure Neutral Currents, a 4th current input channel needs to be created to be used along with the existing three voltage and three current inputs (VA, VB, VC, IA, IB, IC). The Neutral Current measurement can be implemented using the existing 71M6513 demo board with minor hardware and firmware modifications as given below:

Hardware Modifications:

  1. The Neutral Current input can be connected to the 71M6513 Auxiliary input V3 (pin 86)
  2. Analog Auxiliary input V3 is measured with respect to VBIAS (pin 81)
  3. The input circuit for Neutral Current measurement is to be added as shown in the figure below:

Firmware Procedure for Measuring Neutral Current

  1. The Neutral Current measurement is performed by acquiring the auxiliary input data from the V3 pin (pin 86).
  2. The analog data measured is referenced to the VBIAS pin (pin 81).
  3. Analog input V3 data can be read using the MUX_ALT mode bit in the I/O memory.
  4. The TERIDIAN Demo Code revision 3.04 accesses the MUX_ALT mode once a second.
  5. To acquire Neutral Current with a higher number of samples the existing Demo Board firmware has been modified with an MPU register named ALT_MUX_RATE.
  6. The modified firmware stores the ALT_MUX_RATE at MPU RAM (XRAM) location 0x0F, and the value is configurable using the )f=xx command via the serial interface.
  7. The default value for the ALT_MUX_RATE is 2520. The multiplexer is driven once in 2520 samples to acquire the auxiliary data from the Temperature and V3 inputs. The default sampling rate for the auxiliary data is 1Hz. The resulting sampling rate is 2520/ALT_MUX_RATE.
  8. If ALT_MUX_RATE is set to 10 then the auxiliary data is sampled at every 10th sample and thereby the auxiliary data sample rate is 252 Hz.
  9. The Minimum value for ALT_MUX_RATE is 10. That is 252Hz is the maximum recommended sample rate.

The Data collected for several ALT_MUX_RATE settings is given below:

Table 1: Transmitter to 73M1866B/73M1966B Receiver Settings for PCLK Frequency of 2.048MHz
PCM 73M1866B/73M1966B
Transmit Time Slot Receive Time Slot Receive Clock Slot Receive Edge Polarity
RTS[5:0] RCS[2:0] RPOL
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
31
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 2: Receiver to 73M1866B/73M1966B Transmitter Settings for PCLK Frequency of 2.048MHz
PCM 73M1866B/73M1966B
Receive Time Slot Transmit Time Slot Transmit Clock Slot Transmit Edge Polarity
RTS[5:0] RCS[2:0] TPOL
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
31
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0