Overview
Features and Benefits
- Full featured evaluation board for the AD9161, AD9162, AD9163, and AD9164
- ACE software for control
- Direct clocking vs. on-board clocking
- Showing RF modes of the DAC, including mixed mode and 2× NRZ
- NCO only mode
- JESD204B interface mode
Product Details
This user guide is for the AD9161, AD9162, AD9163, and AD9164 evaluation board. The evaluation board connects to an ADS7-V2EBZ pattern generator for quick evaluation of the AD9161, AD9162, AD9163, and AD9164, high speed, RF digital-to-analog converters (RF DACs). The ADS7-V2EBZ automatically formats the data and sends it to the evaluation board, which simplifies evaluation of the device. The evaluation board runs from the FPGA mezzanine card (FMC) power supply.
The evaluation board includes a clock buffer, the AD9508, which provides the reference clock and SYSREF± pins to the ADS7-V2EBZ, and the SYSREF± pins signal to the DAC.
The evaluation board can be driven by an external clock or the on-board clock (ADF4355). There is a single-pole, double throw (SPDT) switch on the board for selecting the clock source.
Markets and Technologies
Applicable Parts
Package Contents
- AD9162-FMC-EBZ, AD9164-FMC-EBZ, AD9162-FMCB-EBZ, AD9164-FMCB-EBZ, AD9161-FMCC-EBZ, AD9162-FMCC-EBZ, AD9163-FMCC-EBZ, or AD9164-FMCC-EBZ
- Mini USB cable
- Evaluation board DVD
Documentation & Resources
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Using MATLAB with ADS7 and AD916x Eval Boards11/20/2019WIKI
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UG-1526: AD9161/AD9162/AD9163/AD9164 User Guide11/8/2019PDF1M
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046277 Design Files (Rev. E)2/6/2023ZIP18 M
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046215 Design Files (Rev. C)2/6/2023ZIP11 M
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Schematic12/9/2020PDF
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Gerber Files12/9/2020ZIP
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BRD File12/9/2020BRD
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BOM12/9/2020CSV
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Schematic11/20/2019PDF
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Gerber Files11/20/2019ZIP
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BRD File11/20/2019BRD
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BOM11/20/2019CSV
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Schematic11/20/2019PDF
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Gerber Files11/20/2019ZIP
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BRD File11/20/2019BRD
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BOM11/20/2019XLS
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Schematic11/20/2019PDF
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Gerber Files11/20/2019ZIP
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BRD File11/20/2019BRD
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BOM11/20/2019XLS