Features and Benefits

  • TX
    • 16-bit 12GSPS RFDAC
    • JESD204B Interface
      • 8 lanes up to 12.5Gbps
    • 1x/2x/4x/6x/8x/12x/16x/24x/32x Interpolation
    • 64-bit NCO at max rate
    • Analog Modes of Operation:
      • Normal Mode: 6GSPS DAC rate
        • Synthesis up to 2.5GHz (1st Nyquist)
      • Mix Mode: 6GSPS DAC rate
        • Synthesis in 2nd & 3rd Nyquist zones
      • 2X Normal Mode: 12GSPS DAC rate
        • Synthesis up to 6GHz (1st Nyquist)
      • Excellent dynamic performance
  • RX
    • 3.2GHz full power bandwidth at 2.5GSPS
      • Noise Density = -149.5dBFs/Hz, ENOB = 9.5 bits
      • SFDR = 77 dBc at 1GHz Ain (2.5Gsps)
      • SFDR = 77dBc at 1.8GHz Ain (2.5Gsps)
    • +/-0.3 LSB DNL, +/-1.0 LSB INL
    • Dual supplies : 1.3V and 2.5V
    • 8 or 6 Lane JESD204B Outputs
    • Programmable clipping threshold for Fast Detect output
    • Two Integrated wide band digital down converters (DDC) per channel
      • 10-bit complex NCO
      • 2 cascaded half band filters (dec/8, dec/16)
    • Timestamp for synchronous processing alignment
      • SYSREF Setup/Hold detector
    • Programmable Interrupt (IRQ) event monitor

Product Details

The AD-FMComms11-EBZ board is a system platform board for communication infrastructure applications that demonstrates the Direct to RF (DRF) transmitter and observation receiver architecture. Using high sample rate RFDAC(s) and RFADC(s), a number of components in previous generation transmitters can be eliminated, such as mixers, modulators, IF amplifiers and filters. The objective being to bring the ADC or DAC as close to the antenna as possible, leading to possibly more cost effective and efficient communications solution.

It is composed of multi-GSPS RF ADC and DAC, AD9625 and AD9162 respectively. The transmit path contains a balun, low pass filter, gain block and variable attenuation to produce an output appropriate for a power amplifier module. Along the observation path, the PA output is coupled back into the board through a variable attenuator, a balun and finally the ADC. Clock management is taken care of on board; all the necessary clocks are generated from a reference. Power management is present as well.


Evaluation Software

JESD204 Interface Framework
Integrated JESD204 software framework for rapid system-level development and optimization