MAX1437B
Info: : PRODUCTION
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MAX1437B

Octal, 12-Bit, 50Msps, 1.8V ADC with Serial LVDS Outputs

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Functionally Compatible with the MAX1437, but Provides a Much Smaller Footprint

Info: : PRODUCTION tooltip
Info: : PRODUCTION tooltip
Part Details
Part Models 2
1ku List Price Starting From $110.66
Features
  • Excellent Dynamic Performance
    • 70.2dB SNR at 5.3MHz
    • 98dBc SFDR at 5.3MHz
    • 82dB Channel Isolation at 5.3MHz
  • Ultra-Low Power
    • 96mW per Channel (Normal Operation)
  • Serial LVDS Outputs
  • Pin-Selectable LVDS/SLVS (Scalable Low-Voltage Signal) Mode
  • LVDS Outputs Support Up to 30in FR-4 Backplane Connections
  • Test Mode for Digital Signal Integrity
  • Fully Differential Analog Inputs
  • Wide Differential Input Voltage Range (1.4VP-P)
  • On-Chip 1.24V Precision Bandgap Reference
  • Clock Duty-Cycle Equalizer
  • Compact, 68-Pin TQFN Package with Exposed Pad
  • Evaluation Kit Available (Order MAX1437BEVKIT)
Additional Details
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The MAX1437B octal, 12-bit analog-to-digital converter (ADC) features fully differential inputs, a pipelined architecture, and digital error correction incorporating a fully differential signal path. This ADC is optimized for low-power and high-dynamic performance in medical imaging instrumentation and digital communications applications. The MAX1437B operates from a 1.8V single supply and consumes only 768mW (96mW per channel) while delivering a 70.2dB (typ) signal-to-noise ratio (SNR) at a 5.3MHz input frequency. In addition to low operating power, the MAX1437B features a low-power standby mode for idle periods.

An internal 1.24V precision bandgap reference sets the full-scale range of the ADC. A flexible reference structure allows the use of an external reference for applications requiring increased accuracy or a different input voltage range. The reference architecture is optimized for low noise.

A single-ended clock controls the data-conversion process. An internal duty-cycle equalizer compensates for wide variations in clock duty cycle. An on-chip phase-locked loop (PLL) generates the high-speed serial low-voltage differential signal (LVDS) clock.

The MAX1437B has self-aligned serial LVDS outputs for data, clock, and frame-alignment signals. The output data is presented in two's complement format.

The MAX1437B offers a maximum sample rate of 50Msps. This device is available in a small, 10mm x 10mm x 0.8mm, 68-pin TQFN package with exposed pad and is specified for the extended industrial (-40°C to +85°C) temperature range.

Applications

  • Instrumentation
  • Multichannel Communications
  • Ultrasound and Medical Imaging
Part Models 2
1ku List Price Starting From $110.66

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Documentation

Documentation

Part Model Pin/Package Drawing Documentation CAD Symbols, Footprints, and 3D Models
MAX1437BETK+
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MAX1437BETK+T
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