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AD9648: 14-Bit, 125 MSPS/105 MSPS, 1.8 V Dual Analog-to-Digital Converter Data Sheet (Rev. C)9/10/2015PDF1119 kB
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AD9648-EP: Enhanced Product Data Sheet (Rev. B)9/10/2015PDF235 K
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AD9648: Military Data Sheet9/9/2015
AD9648
14-Bit, 125 MSPS/105 MSPS, 1.8 V Dual Analog-to-Digital Converter
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Overview
Features and Benefits
- 1.8 V analog supply operation
- 1.8 V CMOS or LVDS outputs
- SNR = 74.5 dBFS at 70 MHz
- SFDR = 91 dBc at 70 MHz
- Low power: 106 mW/channel at 125 MSPS
- Differential analog input with 650 MHz bandwidth
- IF sampling frequencies to 200 MHz
- See data sheet for additional features
- Download AD9648-EP data sheet (pdf)
- Military temperature range: −55°C to +125°C
- Controlled manufacturing baseline
- Qualification data available on request
- V62/16606 DSCC Drawing Number
Product Details
The AD9648 is a monolithic, dual-channel, 1.8 V supply, 14-bit, 105 MSPS/125 MSPS analog-to-digital converter (ADC). It features a high performance sample-and-hold circuit and on-chip voltage reference. The product uses multistage differential pipeline architecture with output error correction logic to provide 14-bit accuracy at 125 MSPS data rates and to guarantee no missing codes over the full operating temperature range.The ADC contains several features designed to maximize flexibility and minimize system cost, such as programmable clock and data alignment and programmable digital test pattern generation. The available digital test patterns include built-in deterministic and pseudorandom patterns, along with custom user-defined test patterns entered via the serial port interface (SPI).
A differential clock input controls all internal conversion cycles. An optional duty cycle stabilizer (DCS) compensates for wide variations in the clock duty cycle while maintaining excellent overall ADC performance.
The digital output data is presented in offset binary, Gray code, or twos complement format. A data output clock (DCO) is provided for each ADC channel to ensure proper latch timing with receiving logic. Output logic levels of 1.8 V CMOS or LVDS are supported. Output data can also be multiplexed onto a single output bus.
The AD9648 is available in a 64-lead RoHS compliant LFCSP and is specified over the industrial temperature range (−40°C to +85°C).
Applications
- Communications
- Diversity radio systems
- Multimode digital receivers
GSM, EDGE, W-CDMA, LTE,
CDMA2000, WiMAX, TD-SCDMA - I/Q demodulation systems
- Smart antenna systems
- Broadband data applications
- Battery-powered instruments
- Hand held scope meters
- Portable medical imaging
- Ultrasound
- Radar/LIDAR
Product Highlights
- The AD9648 operates from a single 1.8 V analog power supply and features a separate digital output driver supply to accommodate 1.8 V CMOS or LVDS logic families.
- The patented sample-and-hold circuit maintains excellent performance for input frequencies up to 200 MHz and is designed for low cost, low power, and ease of use.
- A standard serial port interface supports various product features and functions, such as data output formatting, internal clock divider, power-down, DCO/data timing and offset adjustments.
- The AD9648 is packaged in a 64-lead RoHS compliant LFCSP that is pin compatible with the AD9650/AD9269/AD9268 16-bit ADC’s, the AD9258 14-bit ADC, the AD9628/AD9231 12-bit ADC’s, and the AD9608/AD9204 10-bit ADC’s, enabling a simple migration path between 10-bit and 16-bit converters sampling from 20 MSPS to 125 MSPS.
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Markets and Technologies
Product Lifecycle
Recommended for New Designs
This product has been released to the market. The data sheet contains all final specifications and operating conditions. For new designs, ADI recommends utilization of these products.
Evaluation Kits (2)
Documentation & Resources
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AN-905: VisualAnalog™ Converter Evaluation Tool Version 1.0 User Manual8/18/2020
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AN-878: High Speed ADC SPI Control Software (Rev. A)3/20/2018PDF585 kB
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AN-835: Understanding High Speed ADC Testing and Evaluation (Rev. B)5/12/2015PDF985 kB
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AN-282: Fundamentals of Sampled Data Systems2/14/2015PDF2131 kB
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AN-756: Sampled Systems and the Effects of Clock Phase Noise and Jitter (Rev. 0)2/14/2015PDF291K
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AN-827: A Resonant Approach to Interfacing Amplifiers to Switched-Capacitor ADCs (Rev. 0)2/14/2015PDF203 kB
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AN-935: Designing an ADC Transformer-Coupled Front End (Rev. 0)2/14/2015PDF363 kB
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AN-742: Frequency Domain Response of Switched-Capacitor ADCs (Rev. C)2/14/2015PDF427 K
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AN-1142: Techniques for High Speed ADC PCB Layout (Rev. 0)2/2/2012PDF392 kB
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AN-737: How ADIsimADC Models an ADC (Rev. B)11/9/2007PDF373 kB
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AN-807: Multicarrier WCDMA Feasibility (Rev. 0)11/9/2007PDF969 kB
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AN-808: Multicarrier CDMA2000 Feasibility (Rev. 0)11/9/2007PDF1535 kB
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AN-803: Pin Compatible High Speed ADCs Simplify Design Tasks (Rev. 0)11/29/2006PDF356 kB
Tools & Simulations
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MathWorks®
S-Parameters
Design Tools
Visual Analog
For designers who are selecting or evaluating high speed ADCs, VisualAnalog™ is a software package that combines a powerful set of simulation and data analysis tools with a user-friendly graphical interface.
ADIsimRF
ADIsimRF is an easy-to-use RF signal chain calculator. Cascaded gain, noise, distortion and power consumption can be calculated, plotted and exported for signal chains with up to 50 stages. ADIsimRF also includes an extensive data base of device models for ADI’s RF and mixed signal components.
Product Recommendations
AD9648 Companion Parts
Design Resources
ADI has always placed the highest emphasis on delivering products that meet the maximum levels of quality and reliability. We achieve this by incorporating quality and reliability checks in every scope of product and process design, and in the manufacturing process as well. "Zero defects" for shipped products is always our goal.
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Pricing displayed is based on 1-piece. The USA list pricing shown is for budgetary use only, shown in United States dollars (FOB USA per unit), and is subject to change. International prices may vary due to local duties, taxes, fees and exchange rates.