AD9648
Info : RECOMMENDED FOR NEW DESIGNS
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AD9648

14-Bit, 125 MSPS/105 MSPS, 1.8 V Dual Analog-to-Digital Converter

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Info : RECOMMENDED FOR NEW DESIGNS tooltip
Info : RECOMMENDED FOR NEW DESIGNS tooltip
Part Details
Part Models 6
1ku List Price Starting From $54.30
Features
  • 1.8 V analog supply operation
  • 1.8 V CMOS or LVDS outputs
  • SNR = 74.5 dBFS at 70 MHz
  • SFDR = 91 dBc at 70 MHz
  • Low power: 106 mW/channel at 125 MSPS
  • Differential analog input with 650 MHz bandwidth
  • IF sampling frequencies to 200 MHz
  • See data sheet for additional features

    AD9648-EP supports defense and aerospace applications (AQEC standard)

    • Download AD9648-EP data sheet (pdf)
    • Military temperature range: −55°C to +125°C
    • Controlled manufacturing baseline
    • Qualification data available on request
    • V62/16606 DSCC Drawing Number
Additional Details
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The AD9648 is a monolithic, dual-channel, 1.8 V supply, 14-bit, 105 MSPS/125 MSPS analog-to-digital converter (ADC). It features a high performance sample-and-hold circuit and on-chip voltage reference. The product uses multistage differential pipeline architecture with output error correction logic to provide 14-bit accuracy at 125 MSPS data rates and to guarantee no missing codes over the full operating temperature range.

The ADC contains several features designed to maximize flexibility and minimize system cost, such as programmable clock and data alignment and programmable digital test pattern generation. The available digital test patterns include built-in deterministic and pseudorandom patterns, along with custom user-defined test patterns entered via the serial port interface (SPI).

A differential clock input controls all internal conversion cycles. An optional duty cycle stabilizer (DCS) compensates for wide variations in the clock duty cycle while maintaining excellent overall ADC performance.

The digital output data is presented in offset binary, Gray code, or twos complement format. A data output clock (DCO) is provided for each ADC channel to ensure proper latch timing with receiving logic. Output logic levels of 1.8 V CMOS or LVDS are supported. Output data can also be multiplexed onto a single output bus.

The AD9648 is available in a 64-lead RoHS compliant LFCSP and is specified over the industrial temperature range (−40°C to +85°C).

Applications

  • Communications
  • Diversity radio systems
  • Multimode digital receivers
    GSM, EDGE, W-CDMA, LTE,
    CDMA2000, WiMAX, TD-SCDMA
  • I/Q demodulation systems
  • Smart antenna systems
  • Broadband data applications
  • Battery-powered instruments
  • Hand held scope meters
  • Portable medical imaging
  • Ultrasound
  • Radar/LIDAR

Product Highlights

  1. The AD9648 operates from a single 1.8 V analog power supply and features a separate digital output driver supply to accommodate 1.8 V CMOS or LVDS logic families.
  2. The patented sample-and-hold circuit maintains excellent performance for input frequencies up to 200 MHz and is designed for low cost, low power, and ease of use.
  3. A standard serial port interface supports various product features and functions, such as data output formatting, internal clock divider, power-down, DCO/data timing and offset adjustments.
  4. The AD9648 is packaged in a 64-lead RoHS compliant LFCSP that is pin compatible with the AD9650/AD9269/AD9268 16-bit ADC’s, the AD9258 14-bit ADC, the AD9628/AD9231 12-bit ADC’s, and the AD9608/AD9204 10-bit ADC’s, enabling a simple migration path between 10-bit and 16-bit converters sampling from 20 MSPS to 125 MSPS.
Part Models 6
1ku List Price Starting From $54.30

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Documentation

Documentation

Part Model Pin/Package Drawing Documentation CAD Symbols, Footprints, and 3D Models
AD9648BCPZ-105
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AD9648BCPZ-125
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AD9648BCPZRL7-105
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AD9648BCPZRL7-125
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AD9648TCPZ-125-EP
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AD9648TCPZ125EPRL7
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Product Lifecycle

PCN

Feb 1, 2024

- 24_0009

Qualification of alternative Wafer Fab for TSMC 0.18um Mixed Signal CMOS Process

AD9648BCPZ-105

PRODUCTION

AD9648BCPZ-125

PRODUCTION

AD9648BCPZRL7-105

PRODUCTION

AD9648BCPZRL7-125

PRODUCTION

Jun 9, 2021

- 20_0126

Conversion of Select Sizes LFCSP Products from Punched to Sawn and Transfer of Assembly Site to ASE Korea

Filter by Model

reset

Reset Filters

Part Models

Product Lifecycle

PCN

Feb 1, 2024

- 24_0009

arrow down

Qualification of alternative Wafer Fab for TSMC 0.18um Mixed Signal CMOS Process

AD9648BCPZ-105

PRODUCTION

AD9648BCPZ-125

PRODUCTION

AD9648BCPZRL7-105

PRODUCTION

AD9648BCPZRL7-125

PRODUCTION

Jun 9, 2021

- 20_0126

arrow down

Conversion of Select Sizes LFCSP Products from Punched to Sawn and Transfer of Assembly Site to ASE Korea

Software & Part Ecosystem

Software & Part Ecosystem

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Evaluation Kit

Evaluation Kits 2

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EVAL-AD9648

AD9648 Evaluation Board

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EVAL-AD9648

AD9648 Evaluation Board

AD9648 Evaluation Board

Features and Benefits

  • Full featured evaluation board for the AD9648
  • SPI interface for setup and control
  • External, on-board oscillator, or AD9517 clocking option
  • Balun/transformer or amplifier input drive option
  • LDO regulator or switching power supply options
  • VisualAnalog® and SPI controller software interfaces

Product Detail

The AD9648-125EBZ is an evaluation board for the AD9648, dual 14-bit ADC. This reference design provides all of the support circuitry to operate devices in their various modes and configurations, It is designed to interface directly with the HSC-ADC-EVALCZ data capture card, allowing users to download captured data for analysis. The Visual Analog software package, which is used to interface with the device’s hardware, allows users to download captured data for analysis with a user-friendly graphical interface. The SPI controller software package is also compatible with this hardware and allows the user to access the SPI programmable features of the AD9648.

The AD9648 data sheet provides additional information related to device configuration and performance and should be consulted when using these tools. All documents and Visual Analog and SPI Controller are available at the High Speed ADC Evaluation Boards page. For additional information or questions, please email highspeed.converters@analog.com.

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HSC-ADC-EVALCZ

FPGA-Based Data Capture Kit

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HSC-ADC-EVALCZ

FPGA-Based Data Capture Kit

FPGA-Based Data Capture Kit

Features and Benefits

  • 64kB FIFO Depth
  • Works with single and multi-channel ADCs
  • Use with VisualAnalog® software
  • Based on Virtex-4 FPGA
  • May require adaptor to interface with some ADC eval boards
  • Allows programming of SPI control Up to 644 MSPS SDR / 800MSPS DDR Encode Rates on each channel
  • DDR Encode Rates on each channel

Product Detail

The HSC-ADC-EVALCZ high speed converter evaluation platform uses an FPGA based buffer memory board to capture blocks of digital data from the Analog Devices high speed analog-to-digital converter (ADC) evaluation boards. The board is connected to the PC through a USB port and is used with VisualAnalog® to quickly evaluate the performance of high speed ADCs. The evaluation kit is easy to set up. Additional equipment needed includes an Analog Devices high speed ADC evaluation board, a signal source, and a clock source. Once the kit is connected and powered, the evaluation is enabled instantly on the PC.
Tools & Simulations

Tools & Simulations 6

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