AD9523-1
Info : RECOMMENDED FOR NEW DESIGNS
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AD9523-1

Low Jitter Clock Generator with 14 LVPECL/LVDS/HSTL/29 LVCMOS Outputs

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Info : RECOMMENDED FOR NEW DESIGNS tooltip
Info : RECOMMENDED FOR NEW DESIGNS tooltip
Part Details
Part Models 2
1ku List Price Starting From $11.13
Features
  • Output frequency: <1 MHz to 1 GHz
  • Start-up frequency accuracy: <±100 ppm (determined by VCXO reference accuracy)
  • Zero delay operation
    Input-to-output edge timing: <150 ps
  • Dual VCO dividers
  • 14 outputs: configurable LVPECL, LVDS, HSTL, and LVCMOS
  • 14 dedicated output dividers with jitter-free adjustable delay
  • Adjustable delay: 63 resolution steps of ½ period of VCO output divider
  • Output-to-output skew: <50 ps
  • Duty cycle correction for odd divider settings
  • Automatic synchronization of all outputs on power-up
  • Absolute output jitter: <150 fs at 122.88 MHz Integration range: 12 kHz to 20 MHz
  • See data sheet for additional features
Additional Details
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The AD9523-1 provides a low power, multi-output, clock distribution function with low jitter performance, along with an on-chip PLL and VCO with two VCO dividers. The on-chip VCO tunes from 2.94 GHz to 3.1 GHz.

The AD9523-1 is designed to support the clock requirements for long term evolution (LTE) and multicarrier GSM base station designs. It relies on an external VCXO to provide the reference jitter cleanup to achieve the restrictive low phase noise requirements necessary for acceptable data converter SNR performance.

The input receivers, oscillator, and zero delay receiver provide both single-ended and differential operation. When connected to a recovered system reference clock and a VCXO, the device generates 14 low noise outputs with a range of 1 MHz to 1 GHz, and one dedicated buffered output from the input PLL (PLL1). The frequency and phase of one clock output relative to another clock output can be varied by means of a divider phase select function that serves as a jitter-free, coarse timing adjustment in increments that are equal to half the period of the signal coming out of the VCO.

An in-package EEPROM can be programmed through the serial interface to store user-defined register settings for power-up and chip reset.

APPLICATIONS

  • LTE and multicarrier GSM base stations
  • Wireless and broadband infrastructure
  • Medical instrumentation
  • Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs
  • Low jitter, low phase noise clock distribution
  • Clock generation and translation for SONET, 10Ge, 10G FC, and other 10 Gbps protocols
  • Forward error correction (G.710)
  • High performance wireless transceivers
  • ATE and high performance instrumentation
Part Models 2
1ku List Price Starting From $11.13

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Documentation

Documentation

Part Model Pin/Package Drawing Documentation CAD Symbols, Footprints, and 3D Models
AD9523-1BCPZ
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AD9523-1BCPZ-REEL7
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Product Lifecycle

PCN

Jun 26, 2023

- 23_0025

Package Outline Drawing and Data Sheet Revision for Select LFCSP Products in Amkor

Oct 13, 2015

- 15_0166

AD9523, AD9523-1, and AD9524 Specification Table Changes

AD9523-1BCPZ

PRODUCTION

AD9523-1BCPZ-REEL7

PRODUCTION

Jan 10, 2011

- 10_0351

AD9523-1 die revision

AD9523-1BCPZ

PRODUCTION

AD9523-1BCPZ-REEL7

PRODUCTION

Filter by Model

reset

Reset Filters

Part Models

Product Lifecycle

PCN

Jun 26, 2023

- 23_0025

arrow down

Package Outline Drawing and Data Sheet Revision for Select LFCSP Products in Amkor

Oct 13, 2015

- 15_0166

arrow down

AD9523, AD9523-1, and AD9524 Specification Table Changes

AD9523-1BCPZ

PRODUCTION

AD9523-1BCPZ-REEL7

PRODUCTION

Jan 10, 2011

- 10_0351

arrow down

AD9523-1 die revision

AD9523-1BCPZ

PRODUCTION

AD9523-1BCPZ-REEL7

PRODUCTION

Software & Part Ecosystem

Software & Part Ecosystem

Evaluation Kit

Evaluation Kits 3

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AD-FMCOMMS1-EBZ

FPGA Mezzanine Card for Wireless Communications

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AD-FMCOMMS1-EBZ

FPGA Mezzanine Card for Wireless Communications

FPGA Mezzanine Card for Wireless Communications

Features and Benefits

  • Includes schematics, layout, BOM, Gerber files, HDL, Linux® drivers, IIO Oscilloscope, VisualANALOG
  • FMC-compatible form factor
  • Powered from FMC connector
  • Provides one channel of ADC and one channel of DAC with full synchronization capabilities

Product Detail

This board is no longer available for ordering.

The AD-FMCOMMS1-EBZ high-speed analog module is designed to showcase the latest generation high-speed data converters. The AD-FMCOMMS1-EBZ provides the analog front-end for a wide range of compute-intensive FPGA-based radio applications.

The AD-FMCOMMS1-EBZ is an analog front end hardware platform that addresses a broad range of research, academic, industrial and defense applications. The AD-FMCOMMS1-EBZ enables RF applications from 400MHz to 4 GHz. The module is customizable to a wide range of frequencies by software without any hardware changes, providing options for GPS or IEEE 1588 Synchronization, and MIMO configurations.

When combined with the Xilinx ZYNQ® Software-Defined Radio Kit, AD-FMCOMMS1-EBZ enables a variety of wireless communications functions at the physical layer, from baseband to RF. With up to 4 GB of flash storage space, 512 MB of RAM, Gigabit Ethernet interface (depending on the base platform) and a Linux image built specifically for the AD-FMCOMMS1-EBZ, you can get everything you need for a easy out of the box experience. The platform offers enough flexibility for many applications, and supports streaming data, and standard web interfaces to analyze transmitted RF data.

Applications

  • Electronic test and measurement equipment
  • General-purpose software radios
  • Radar systems
  • Ultra wideband satellite receivers
  • Point to point communication systems
reference details image

AD-FMCDAQ2-EBZ

AD-FMCDAQ2-EBZ Evaluation Board

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AD-FMCDAQ2-EBZ

AD-FMCDAQ2-EBZ Evaluation Board

AD-FMCDAQ2-EBZ Evaluation Board

Features and Benefits

  • Includes schematics, layout, BOM, Gerber files, HDL, Linux® drivers, IIO Oscilloscope, VisualANALOG
  • FMC-compatible form factor
  • Powered from FMC connector
  • Provides two channels of ADC and two channels of DAC with full synchronization capabilities

Product Detail

The AD-FMCDAQ2-EBZ module is comprised of the AD9680 dual, 14-bit, 1.0 GSPS, JESD204B ADC, the AD9144 quad, 16-bit, 2.8 GSPS, JESD204B DAC, the AD9523-1 14-output, 1GHz clock, and power management components. It is clocked by an internally generated carrier platform via the FMC connector, comprising a completely self-contained data acquisition and signal synthesis prototyping platform. In an FMC footprint (84 mm × 69 mm), the module’s combination of wideband data conversion, clocking, and power closely approximates real-world hardware and software for system prototyping and design, with no compromise in signal chain performance.

Applications

  • Electronic test and measurement equipment
  • General-purpose software radios
  • Radar systems
  • Ultra wideband satellite receivers
  • Point-to-point communication systems

EVAL-AD9523-1

AD9523/AD9523-1 Evaluation Board

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EVAL-AD9523-1

AD9523/AD9523-1 Evaluation Board

AD9523/AD9523-1 Evaluation Board

Features and Benefits

  • Simple power connection using USB connection and on-board LDO voltage regulators
  • LDOs are easily bypassed for power measurements
  • AC-coupled differential SMA connectors
  • SMA connectors for
    2 reference inputs
    2 PLL status outputs
    1 reference test input
    2 VCXO interface inputs/outputs
  • Microsoft Windows®–based evaluation software with simple graphical user interface
  • On-board PLL loop filter
  • Easy access to digital I/O and diagnostic signals via I/O header
  • Status LEDs for diagnostic signals
  • USB computer interface
  • Software calculator provides flexibility, allowing programming of almost any rational input/output frequency ratio

Product Detail

The AD9523-1 is designed to support the clock requirements for long-term evolution (LTE) and multicarrier GSM base station designs. It relies on an external VCXO to provide the reference jitter cleanup to achieve the restrictive low phase noise requirements necessary for acceptable data converter SNR performance. The AD9523-1 evaluation board is a compact, easy-to-use platform for evaluating all features of the AD9523-1. A 122.88 MHz VCXO is mounted on the evaluation board to provide a complete solution.


The input receivers are configured as differential but the evaluation board has baluns to provide a single-ended input for easy evaluation using common laboratory single-ended signal sources. Output 8 is connected to an ADCLK905 clock buffer to provide a way to evaluate an Analog Devices, Inc., buffer. Although the ADCLK905 is a 1-to-1 buffer, the performance is similar to the larger fanout buffer, for example, the 1-to-2 buffer, ADCLK925. Output 1 and Output 9 are configured with baluns to provide a single-ended output to drive most test equipment. Output 0 is configured for differential zero delay operation.

Tools & Simulations

Tools & Simulations 2

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