AD9516-0
14-Output Clock Generator with Integrated 2.8 GHz VCO
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Features
- Low phase noise, phase-locked loop (PLL)
On-chip VCO tunes from 2.55 GHz to 2.95 GHz
External VCO/VCXO to 2.4 GHz optional
1 differential or 2 single-ended reference inputs - 6 pairs of 1.6 GHz LVPECL outputs
Each output pair shares a 1-to-32 divider with coarse phase delay
Additive output jitter: 225 fs rms
Channel-to-channel skew paired outputs of <10 ps
- 4 pairs of 800 MHz LVDS clock outputs
Each output pair shares two cascaded 1-to-32 dividers with coarse phase delay
Additive output jitter: 275 fs rms - Automatic synchronization of all outputs on power-up
- Manual output synchronization available
- 64-lead LFCSP
- See datasheet for additional features
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The AD9516-0 provides a multi-output clock distribution function with subpicosecond jitter performance, along with an on-chip PLL and VCO. The on-chip VCO tunes from 2.55 GHz to 2.95 GHz. Optionally, an external VCO/VCXO of up to 2.4 GHz can be used.
The AD9516-0 emphasizes low jitter and phase noise to maximize data converter performance, and it can benefit other applications with demanding phase noise and jitter requirements.
The AD9516-0 features six LVPECL outputs (in three pairs) and four LVDS outputs (in two pairs). Each LVDS output can be reconfigured as two CMOS outputs. The LVPECL outputs operate to 1.6 GHz, the LVDS outputs operate to 800 MHz, and the CMOS outputs operate to 250 MHz.
Each pair of outputs has dividers that allow both the divide ratio and coarse delay (or phase) to be set. The range of division for the LVPECL outputs is 1 to 32. The LVDS/CMOS outputs allow a range of divisions up to a maximum of 1024.
The AD9516-0 is available in a 64-lead LFCSP and can be operated from a single 3.3 V supply. An external VCO, which requires an extended voltage range, can be accommodated by connecting the charge pump supply (VCP) to 5 V. A separate LVPECL power supply can be from 2.5 V to 3.3 V (nominal).
The AD9516-0 is specified for operation over the industrial range of −40°C to +85°C.
APPLICATIONS
- Low jitter, low phase noise clock distribution
- 10/40/100 Gb/sec networking line cards, including SONET, Synchronous Ethernet, OTU2/3/4
- Forward error correction (G.710)
- Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs
- High performance wireless transceivers
- ATE and high performance instrumentation
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AD9516-0
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Application Note 13
AN-769: Generating Multiple Clock Outputs from the AD9540 (Rev.0)
AN-823: Direct Digital Synthesizers in Clocking Applications Time (Rev.0)
AN-927: Determining if a Spur is Related to the DDS/DAC or to Some Other Source (For Example, Switching Supplies) (Rev.0)
AN-939: Super-Nyquist Operation of the AD9912 Yields a High RF Output Signal (Rev.0)
AN-756: Sampled Systems and the Effects of Clock Phase Noise and Jitter (Rev.0)
AN-0974: Multicarrier TD-SCMA Feasibility (Rev.0)
AN-873: Lock Detect on the ADF4xxx Family of PLL Synthesizers (Rev.0)
AN-741: Little Known Characteristics of Phase Noise (Rev.0)
AN-501: Aperture Uncertainty and ADC System Performance (Rev.A)
AN-0983: Introduction to Zero-Delay Clock Timing Techniques
AN-769: Generating Multiple Clock Outputs from the AD9540
AN-835: Understanding High Speed ADC Testing and Evaluation
AN-2566: High Dynamic Range RF Transmitter Signal Chain Using Single External Frequency Reference for DAC Sample Clock and IQ Modulator LO Generation
Technical Articles 6
Understand the Effects of Clock Jitter and Phase Noise on Sampled Systems
ADI Buys Korean Mobile TV Chip Maker
Speedy A/Ds Demand Stable Clocks
Design A Clock-Distribution Strategy With Confidence
Low-power direct digital synthesizer cores enable high level of integration
Improved DDS Devices Enable Advanced Comm Systems
Evaluation Design File 3
Frequently Asked Question 1
Device Drivers 1
Product Selection Guide 1
Analog Dialogue 1
Rarely Asked Question Page 12
Webcast 2
ADI has always placed the highest emphasis on delivering products that meet the maximum levels of quality and reliability. We achieve this by incorporating quality and reliability checks in every scope of product and process design, and in the manufacturing process as well. "Zero defects" for shipped products is always our goal. View our quality and reliability program and certifications for more information.
| Part Model | Pin/Package Drawing | Documentation | CAD Symbols, Footprints, and 3D Models |
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| AD9516-0BCPZ |
64-Lead LFCSP (9mm x 9mm w/ EP)
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| AD9516-0BCPZ-REEL7 |
64-Lead LFCSP (9mm x 9mm w/ EP)
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64-Lead LFCSP (9mm x 9mm w/ EP)
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- Pin/Package Drawing
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64-Lead LFCSP (9mm x 9mm w/ EP)
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HTML
Material Declaration
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HTML
Reliablity Data
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SamacSys
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PCN
Jun 9, 2021
- 20_0126
Conversion of Select Sizes LFCSP Products from Punched to Sawn and Transfer of Assembly Site to ASE Korea
AD9516-0BCPZ
PRODUCTION
AD9516-0BCPZ-REEL7
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Filter by Model
Part Models
Product Lifecycle
PCN
Jun 9, 2021
- 20_0126
Conversion of Select Sizes LFCSP Products from Punched to Sawn and Transfer of Assembly Site to ASE Korea
AD9516-0BCPZ
PRODUCTION
AD9516-0BCPZ-REEL7
PRODUCTION
Software & Part Ecosystem
Device Drivers
Looking for Evaluation Software? You can find it here
Evaluation Kits 1
EVAL-AD9516-0
AD9516-0 Evaluation Board
Features and Benefits
- Simple power connection using 6 V wall adapter and on-board LDO voltage regulators
- LDOs are easily bypassed for power measurements
- 8 ac-coupled differential LVPECL SMA connectors
- 2 ac-coupled LVPECL differential headers
- 2 dc-coupled differential LVDS SMA connectors that are reconfigurable to four CMOS SMA connectors
- 2 dc-coupled LVDS differential headers that are reconfigurable to four CMOS connectors
- SMA connectors for
- 2 reference inputs
- Charge pump output
- Clock distribution input
- USB connection to PC
- Microsoft Windows-based evaluation software with simple graphical user interface
- On-board PLL loop filter
- Easy access to digital I/O and diagnostic signals via I/O header
- Status LEDs for diagnostic signals
Product Detail
The AD9516-x, AD9517-x, and AD9518-x are very low noise PLL clock synthesizers featuring an integrated VCO, clock dividers, and up to 14 outputs. The AD9516 features automatic holdover and a flexible reference input circuit allowing for very smooth reference clock switching. The AD9516 family also features the necessary provisions for an external VCXO.
The AD9516 evaluation board is a compact, easy-to-use platform for evaluating all features of the AD9516. The user guide covers all six versions of the AD9516 family, as well as the AD9517 and AD9518 families (hereafter referred to as AD951x). The AD9516, AD9517, and AD9518 differ only in package size, and the number of outputs. The evaluation software main window for the AD9517 and AD9518 reflects fewer outputs, but the operation is identical for all devices.
Although the Quick Start Guide to the AD9516 PLL section applies specifically to the AD9516-3, increasing the N (feed-back) divider and channel divider increases the VCO frequency to the allowable frequency range of other AD9516 versions.
For the AD9516-5, which lacks an internal VCO, certain portions of this document that apply to the internal VCO (such as VCO calibration) can be ignored.
Applications
- Clocking of analog-to-digital and digital-to-analog converters up to 2.9 GHz
- Networking and communications line cards
- Test and measurement equipment
- Wireless base stations, controllers
- Clock cleanup/jitter attenuation
- Clock distribution
Resources
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ADIsimCLK Design and Evaluation Software
