AD9269
16-Bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS, 1.8 V Dual Analog-to-Digital Converter
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Features
- 1.8 V analog supply operation
- 1.8 V to 3.3 V output supply
- Integrated quadrature error correction (QEC)
- SNR
77.6 dBFS at 9.7 MHz input
71 dBFS at 200 MHz input - SFDR
93 dBc at 9.7 MHz input
80 dBc at 200 MHz input - Low power
44 mW per channel at 20 MSPS
100 mW per channel at 80 MSPS
- Differential input with 700 MHz bandwidth
- On-chip voltage reference and sample-and-hold circuit
- 2V p-p differential analog input
- DNL = −0.5/+1.1 LSB
- Serial port control options
- Offset binary, gray code, or twos complement data format
- Optional clock duty cycle stabilizer (DCS)
- See data sheet for additional features
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The AD9269 is a monolithic, dual-channel, 1.8 V supply, 16-bit, 20/40/65/80 MSPS analog-to-digital converter (ADC). It features a high performance sample-and-hold circuit and on-chip voltage reference.
The product uses multistage differential pipeline architecture with output error correction logic to provide 16-bit accuracy at 80 MSPS data rates and to guarantee no missing codes over the full operating temperature range.
The AD9269 incorporates an optional integrated dc correction and quadrature error correction block (QEC) that corrects for dc offset, gain, and phase mismatch between the two channels. This functional block can be very beneficial to complex signal processing applications such as direct conversion receivers.
The ADC also contains several features designed to maximize flexibility and minimize system cost, such as programmable clock and data alignment and programmable digital test pattern generation. The available digital test patterns include built-in deterministic and pseudorandom patterns, along with custom user-defined test patterns entered via the serial port interface (SPI).
A differential clock input controls all internal conversion cycles. An optional duty cycle stabilizer (DCS) compensates for wide variations in the clock duty cycle while maintaining excellent overall ADC performance.
The digital output data is presented in offset binary, gray code, or twos complement format. A data output clock (DCO) is pro-vided for each ADC channel to ensure proper latch timing with receiving logic. Both 1.8 V and 3.3 V CMOS levels are supported, and output data can be multiplexed onto a single output bus.
The AD9269 is available in a 64-lead RoHS-compliant LFCSP and is specified over the industrial temperature range (−40°C to +85°C).
APPLICATIONS
- Communications
- Diversity radio systems
- Multimode digital receivers
GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA - I/Q demodulation systems
- Smart antenna systems
- Battery-powered instruments
- Hand held scope meters
- Portable medical imaging
- Ultrasound
- Radar/LIDAR
Ask a Question
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Support
Analog Devices Support Portal is a one-stop shop to answer all your ADI questions.
Visit the ADI Support Page
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AD9269
Documentation
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Documentation
Data Sheet 1
User Guide 2
Application Note 9
AN-827: A Resonant Approach to Interfacing Amplifiers to Switched-Capacitor ADCs (Rev.0)
AN-807: Multicarrier WCDMA Feasibility (Rev.0)
AN-808: Multicarrier CDMA2000 Feasibility (Rev.0)
AN-812: MicroController-Based Serial Port Interface (SPI) Boot Circuit (Rev.0)
AN-878: High Speed ADC SPI Control Software (Rev.A)
AN-586: LVDS Outputs for High Speed A/D Converters (Rev.0)
AN-935: Designing an ADC Transformer-Coupled Front End
AN-1211: Powering the AD9268 Dual Channel 16-Bit, 125 MSPS Analog-to-Digital Converter with the ADP2114 Synchronous Step-Down DC-to-DC Regulator for Increased Efficiency
AN-1142: Techniques for High Speed ADC PCB Layout
Technical Articles 2
Evaluation Design File 2
ADI has always placed the highest emphasis on delivering products that meet the maximum levels of quality and reliability. We achieve this by incorporating quality and reliability checks in every scope of product and process design, and in the manufacturing process as well. "Zero defects" for shipped products is always our goal. View our quality and reliability program and certifications for more information.
| Part Model | Pin/Package Drawing | Documentation | CAD Symbols, Footprints, and 3D Models |
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| AD9269BCPZ-20 |
64-Lead LFCSP (9mm x 9mm x 0.75mm w/ EP)
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| AD9269BCPZ-40 |
64-Lead LFCSP (9mm x 9mm x 0.75mm w/ EP)
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| AD9269BCPZ-65 |
64-Lead LFCSP (9mm x 9mm x 0.75mm w/ EP)
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| AD9269BCPZRL7-20 |
64-Lead LFCSP (9mm x 9mm x 0.75mm w/ EP)
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| AD9269BCPZRL7-40 |
64-Lead LFCSP (9mm x 9mm x 0.75mm w/ EP)
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| AD9269BCPZRL7-65 |
64-Lead LFCSP (9mm x 9mm x 0.75mm w/ EP)
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| AD9269BCPZRL7-80 |
64-Lead LFCSP (9mm x 9mm x 0.75mm w/ EP)
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- AD9269BCPZ-20
- Pin/Package Drawing
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64-Lead LFCSP (9mm x 9mm x 0.75mm w/ EP)
- Documentation
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HTML
Material Declaration
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HTML
Reliablity Data
- CAD Symbols, Footprints, and 3D Models
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Ultra Librarian
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SamacSys
- AD9269BCPZ-40
- Pin/Package Drawing
-
64-Lead LFCSP (9mm x 9mm x 0.75mm w/ EP)
- Documentation
-
HTML
Material Declaration
-
HTML
Reliablity Data
- CAD Symbols, Footprints, and 3D Models
-
Ultra Librarian
-
SamacSys
- AD9269BCPZ-65
- Pin/Package Drawing
-
64-Lead LFCSP (9mm x 9mm x 0.75mm w/ EP)
- Documentation
-
HTML
Material Declaration
-
HTML
Reliablity Data
- CAD Symbols, Footprints, and 3D Models
-
Ultra Librarian
-
SamacSys
- AD9269BCPZRL7-20
- Pin/Package Drawing
-
64-Lead LFCSP (9mm x 9mm x 0.75mm w/ EP)
- Documentation
-
HTML
Material Declaration
-
HTML
Reliablity Data
- CAD Symbols, Footprints, and 3D Models
-
Ultra Librarian
-
SamacSys
- AD9269BCPZRL7-40
- Pin/Package Drawing
-
64-Lead LFCSP (9mm x 9mm x 0.75mm w/ EP)
- Documentation
-
HTML
Material Declaration
-
HTML
Reliablity Data
- CAD Symbols, Footprints, and 3D Models
-
Ultra Librarian
-
SamacSys
- AD9269BCPZRL7-65
- Pin/Package Drawing
-
64-Lead LFCSP (9mm x 9mm x 0.75mm w/ EP)
- Documentation
-
HTML
Material Declaration
-
HTML
Reliablity Data
- CAD Symbols, Footprints, and 3D Models
-
Ultra Librarian
-
SamacSys
- AD9269BCPZRL7-80
- Pin/Package Drawing
-
64-Lead LFCSP (9mm x 9mm x 0.75mm w/ EP)
- Documentation
-
HTML
Material Declaration
-
HTML
Reliablity Data
- CAD Symbols, Footprints, and 3D Models
-
Ultra Librarian
-
SamacSys
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Part Models
Product Lifecycle
PCN
Jun 9, 2021
- 20_0126
Conversion of Select Sizes LFCSP Products from Punched to Sawn and Transfer of Assembly Site to ASE Korea
AD9269BCPZ-20
PRODUCTION
AD9269BCPZ-40
PRODUCTION
AD9269BCPZ-65
PRODUCTION
AD9269BCPZRL7-20
PRODUCTION
AD9269BCPZRL7-40
PRODUCTION
AD9269BCPZRL7-65
PRODUCTION
AD9269BCPZRL7-80
PRODUCTION
Filter by Model
Part Models
Product Lifecycle
PCN
Jun 9, 2021
- 20_0126
Conversion of Select Sizes LFCSP Products from Punched to Sawn and Transfer of Assembly Site to ASE Korea
AD9269BCPZ-20
PRODUCTION
AD9269BCPZ-40
PRODUCTION
AD9269BCPZ-65
PRODUCTION
AD9269BCPZRL7-20
PRODUCTION
AD9269BCPZRL7-40
PRODUCTION
AD9269BCPZRL7-65
PRODUCTION
AD9269BCPZRL7-80
PRODUCTION
Software & Part Ecosystem
| Parts | Product Life Cycle | Description | ||
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Baseband Programmable VGA-Filters1 |
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Obsolete |
31 MHz, Dual Programmable Filters and Variable Gain Amplifiers |
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Clock Distribution Devices3 |
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RECOMMENDED FOR NEW DESIGNS |
800 MHz Clock Distribution IC, Dividers, Delay Adjust, Three Outputs |
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RECOMMENDED FOR NEW DESIGNS |
1.6 GHz Clock Distribution IC, Dividers, Delay Adjust, Three Outputs |
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RECOMMENDED FOR NEW DESIGNS |
1.6 GHz Clock Distribution IC, Dividers, Delay Adjust, Two Outputs |
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Clock Generation Devices3 |
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RECOMMENDED FOR NEW DESIGNS |
1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Eight Outputs |
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RECOMMENDED FOR NEW DESIGNS |
1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Five Outputs |
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RECOMMENDED FOR NEW DESIGNS |
1.2 GHz Clock Distribution IC, Two 1.6 GHz Inputs, Dividers, Delay Adjust, Five Outputs |
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Digital Control VGAs2 |
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RECOMMENDED FOR NEW DESIGNS |
41 dB Range, 1 dB Step Size, Programmable Dual VGA |
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RECOMMENDED FOR NEW DESIGNS |
Ultralow Distortion IF Dual VGA |
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Fully Differential Amplifiers2 |
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RECOMMENDED FOR NEW DESIGNS |
2.9 GHz Ultralow Distortion RF/IF Differential Amplifier |
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RECOMMENDED FOR NEW DESIGNS |
3.3 GHz Ultralow Distortion RF/IF Differential Amplifier |
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Single-Ended to Differential Amplifiers2 |
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RECOMMENDED FOR NEW DESIGNS |
Ultralow Distortion Differential ADC Driver (Dual) |
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RECOMMENDED FOR NEW DESIGNS |
Ultralow Distortion Differential ADC Driver (Dual) |
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Can't find the software or driver you need?
Request a Driver/SoftwareEvaluation Kits 2
HSC-ADC-EVALCZ
FPGA-Based Data Capture Kit
Features and Benefits
- 64kB FIFO Depth
- Works with single and multi-channel ADCs
- Use with VisualAnalog® software
- Based on Virtex-4 FPGA
- May require adaptor to interface with some ADC eval boards
- Allows programming of SPI control Up to 644 MSPS SDR / 800MSPS DDR Encode Rates on each channel
- DDR Encode Rates on each channel
Product Detail
Resources
Software
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29.79 M
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ZIP
EVAL-AD9269
AD9269 Evaluation Board
Product Detail
This page contains evaluation board documentation and ordering information for evaluating the AD9269.
The AD9269-80EBZ is an evaluation board for the AD9269, dual 16-bit ADC. This reference design provides all of the support circuitry to operate devices in their various modes and configurations. It is designed to interface directly with the HSC-ADC-EVALCZ data capture card, allowing users to download captured data for analysis. The Visual Analog software package, which is used to interface with the device's hardware, allows users to download captured data for analysis with a user-friendly graphical interface. The SPI controller software package is also compatible with this hardware and allows the user to access the SPI programmable features of the AD9269.
The AD9269 data sheet provides additional information related to device configuration and performance and should be consulted when using these tools. All documents and Visual Analog and SPI Controller are available at the High Speed ADC Evaluation Boards page. For additional information or questions, please email highspeed.converters@analog.com.
Resources
2699 kB
Tools & Simulations 6
Virtual Eval - BETA
IBIS Model 1
IBIS Model
SPICE Model 1
Visual Analog
ADIsimRF
MathWorks® 1
