AD9208
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AD9208

14-Bit, 3GSPS, JESD204B, Dual Analog-to-Digital Converter

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Info : RECOMMENDED FOR NEW DESIGNS tooltip
Info : RECOMMENDED FOR NEW DESIGNS tooltip
Part Details
Part Models 2
1ku List Price Starting From $1400.63
Features
  • JESD204B (Subclass 1) coded serial digital outputs 
    • Support for lane rates up to 16 Gbps per lane 
  • 1.65 W total power per channel at 3 GSPS (default settings) 
  • Performance at −2 dBFS amplitude, 2.6 GHz input
    • SFDR = 70 dBFS
    • SNR = 57.2 dBFS
  • Performance at −9 dBFS amplitude, 2.6 GHz input
    • SFDR = 78 dBFS
    • SNR = 59.5 dBFS
  • Integrated input buffer
  • Noise density = −152 dBFS/Hz
  • 0.975 V, 1.9 V, and 2.5 V dc supply operation
  • 9 GHz analog input full power bandwidth (−3 dB)
  • Amplitude detect bits for efficient AGC implementation
  • 2 integrated, wideband digital processors per channel
    • 48-bit NCO 
    • 4 cascaded half-band filters 
  • Phase coherent NCO switching
  • Up to 4 channels available 
  • Serial port control
    • Integer clock with divide by 2 and divide by 4 options
    • Flexible JESD204B lane configurations
  • On-chip dither
Additional Details
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The AD9208 is a dual, 14-bit, 3 GSPS analog-to-digital converter (ADC). The device has an on-chip buffer and a sample-and- hold circuit designed for low power, small size, and ease of use. This product is designed to support communications applications capable of direct sampling wide bandwidth analog signals of up to 5 GHz. The −3 dB bandwidth of the ADC input is 9 GHz. The AD9208 is optimized for wide input bandwidth, high sampling rate, excellent linearity, and low power in a small package.

The dual ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. The analog input and clock signals are differential inputs. The ADC data outputs are internally connected to four digital downconverters (DDCs) through a crossbar mux. Each DDC consists of up to five cascaded signal processing stages: a 48-bit frequency translator (numerically controlled oscillator (NCO)), and up to four half-band decimation filters. The NCO has the option to select preset bands over the general-purpose input/output (GPIO) pins, which enables the selection of up to three bands. Operation of the AD9208 between the DDC modes is selectable via SPI-programmable profiles.

In addition to the DDC blocks, the AD9208 has several functions that simplify the automatic gain control (AGC) function in a communications receiver. The programmable threshold detector allows monitoring of the incoming signal power using the fast detect control bits in Register 0x0245 of the ADC. If the input signal level exceeds the programmable threshold, the fast detect indicator goes high. Because this threshold indicator has low latency, the user can quickly turn down the system gain to avoid an overrange condition at the ADC input. In addition to the fast detect outputs, the AD9208 also offers signal monitoring capability. The signal monitoring block provides additional information about the signal being digitized by the ADC.

The user can configure the Subclasss 1 JESD204B-based high speed serialized output in a variety of one-lane, two-lane, four- lane, and eight-lane configurations, depending on the DDC configuration and the acceptable lane rate of the receiving logic device. Multidevice synchronization is supported through the SYSREF± and SYNCINB± input pins.

The AD9208 has flexible power-down options that allow significant power savings when desired. All of these features can be programmed using a 3-wire serial port interface (SPI).

The AD9208 is available in a Pb-free, 196-ball BGA, specified over the −40°C to +85°C ambient temperature range. This product is protected by a U.S. patent.

Note that throughout this data sheet, multifunction pins, such as FD_A/GPIO_A0, are referred to either by the entire pin name or by a single function of the pin, for example, FD_A, when only that function is relevant.

Product Highlights

  1. Wide, input −3 dB bandwidth of 9 GHz supports direct radio frequency (RF) sampling of signals up to about 5 GHz.
  2. Four integrated, wideband decimation filter and NCO blocks supporting multiband receivers.
  3. Fast NCO switching enabled through GPIO pins.
  4. A SPI controls various product features and functions to meet specific system requirements.
  5. Programmable fast overrange detection and signal monitoring.
  6. On-chip temperature dioide for system thermal management.
  7. 12mm × 12mm 196-Lead BGA

Applications

  • Diversity multiband, multimode digital receivers
  • 3G/4G, TD-SCDMA, W-CDMA, GSM, LTE, LTE-A
  • Electronic test and measurement systems
  • Phased array radar and electronic warfare
  • DOCSIS 3.0 CMTS upstream receive paths
  • HFC digital reverse path receivers
Part Models 2
1ku List Price Starting From $1400.63

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Documentation

Documentation

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Part Model Pin/Package Drawing Documentation CAD Symbols, Footprints, and 3D Models
AD9208BBPZ-3000
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AD9208BBPZRL-3000
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Software & Part Ecosystem

Software & Part Ecosystem

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Evaluation Kit

Evaluation Kits 2

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ADS8-V1EBZ

ADS8-V1 Evaluation Board

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ADS8-V1EBZ

ADS8-V1 Evaluation Board

ADS8-V1 Evaluation Board

Features and Benefits

  • Xilinx Kintex Ultrascale XCKU040-3FFVA1156E FPGA.
  • One (1) FMC+ connector.
  • Twenty (20) 16Gbps transceivers supported by one (1) FMC+ connector.
  • DDR4 SDRAM.
  • Simple USB 3.0 port interface.

Product Detail

When connected to a specified Analog Devices high speed adc evaluation board, the ADS8-V1 works as a data acquistion board. Designed to support the highest speed JESD204B A/D Converters, the FPGA on the ADS8-V1 acts as the data receiver, while the ADC is the data transmitter.

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EVAL-AD9208

Single AD9208 and Dual AD9208 Evaluation Boards

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EVAL-AD9208

Single AD9208 and Dual AD9208 Evaluation Boards

Single AD9208 and Dual AD9208 Evaluation Boards

Features and Benefits

Two evaluation options are available: AD9208-3000EBZ and AD9208-DUAL-EBZ.

  • AD9208-3000 Features
    • Full featured evaluation board for the AD9208-3000. 
    • Wide band Balun driven input. 
    • No external supply needed. Uses 12V-1A and 3.3V-3A supplies from FMC connector. 
    • Single software interface for device control and analysis through ACE. 
  • AD9208-DUAL Features
    • Demonstration board showing multi-chip synchronization of two AD9208 ADCs using HMC7044.
    • Self contained clocking for the ADCs as well as the FPGA.
    • Single external 12V supply.
    • Interfaces with VCU118 or similar FPGA development board with FMC+ (Vita57.4) connector.
    • Uses Analog Devices’ JESD204B IP framework.
    • Low SWaP high efficiency power delivery using Silent Switcher technology.
    • Full software support available Analog Devices Wiki Page.

Product Detail

The AD9208-3000EBZ supports the AD9208-3000, a 14-bit, 3GSPS dual analog-to-digital converter (ADC). The device has an on-chip buffer and a sample-and-hold circuit designed for low power, small size, and ease of use. This device is designed support direct RF sampling analog signals of up to 5 GHz. The 3 dB bandwidth of the ADC input is greater than 9 GHz. The AD9208 is optimized for wide input bandwidth, high sampling rate, excellent linearity, and low power in a small package.

This reference design provides all of the support circuitry required to operate the ADC in its various modes and configurations. It is designed to interface directly with the ADS7-V2EBZ data capture card, allowing users to download captured data for analysis. The device control and subsequent data analyses can now be done using the ACE software package.

The AD9208-DUAL-EBZ is a demonstration board designed to show multi-chip synchronization using JESD204B subclass1 protocol. The AD9208-3000 is a 14-bit, 3GSPS dual analog-to-digital converter (ADC). This device is designed support direct RF sampling analog signals of up to 5 GHz. The 3 dB bandwidth of the ADC input is greater than 9 GHz. The AD9208 is optimized for wide input bandwidth, high sampling rate, excellent linearity, and low power in a small package. The HMC7044 is a high performance, dual-loop, integer-N jitter attenuator capable of performing reference selection and generation of ultralow phase noise frequencies for high speed data converters with either parallel or serial (JESD204B type) interfaces. The LTM8074 is a 40VIN, 1.2A continuous, 1.75A peak, step-down µModule® (power module) regulator. The Silent Switcher architecture minimizes EMI while delivering high efficiency at frequencies up to 2.2MHz.

This reference design provides all of the support circuitry required to operate the ADC in its various modes and configurations. It is designed to easily demonstrate multi-chip synchronization using the JESD204B subclass1 protocol. The board is designed to interface directly with FPGA development boards with FMC+ (Vita57.4) connector.

Tools & Simulations

Tools & Simulations 7

LTspice® is a powerful, fast and free simulation software, schematic capture and waveform viewer with enhancements and models for improving the simulation of analog circuits.

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