AD9161
Info : RECOMMENDED FOR NEW DESIGNS
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AD9161

11-Bit, 12 GSPS, RF Digital-to-Analog Converters

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Info : RECOMMENDED FOR NEW DESIGNS tooltip
Info : RECOMMENDED FOR NEW DESIGNS tooltip
Part Details
Part Models 2
1ku List Price Starting From $114.28
Features
  • DAC update rate up to 12 GSPS (minimum)
  • Direct RF synthesis at 6 GSPS (minimum)
    • DC to 2.5 GHz in baseband 1× bypass mode
    • DC to 6 GHz in 2× nonreturn-to-zero (NRZ) mode
    • 1.5 GHz to 7.5 GHz in Mix-Mode
  • Bypassable interpolation (1× or bypass mode)
    • 2×, 3×, 4×, 6×, 8×, 12×, 16×, 24×
  • Excellent dynamic performance
Additional Details
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The AD9161 is a high performance, 11-bit digital-to-analog converter (DAC) that supports data rates to 6 GSPS. The DAC core is based on a quad-switch architecture coupled with a 2× interpolator filter that enables an effective DAC update rate of up to 12 GSPS in some modes. The high dynamic range and bandwidth makes these DACs ideally suited for the most demanding high speed radio frequency (RF) DAC applications.

In baseband mode, wide bandwidth capability combines with high dynamic range to support DOCSIS 3.1 cable infrastructure compliance from the minimum of two carriers to full maximum spectrum of 1.794 GHz. A 2× interpolator filter (FIR85) enables the AD9161/AD9162 to be configured for lower data rates and converter clocking to reduce the overall system power and ease the filtering requirements. In Mix-Mode operation, the AD9161/AD9162 can reconstruct RF carriers in the second and third Nyquist zones up to 7.5 GHz while still maintaining exceptional dynamic range. The output current can be programmed from 8 mA to 38.76 mA. The AD9161/AD9162 data interface consists of up to eight JESD204B serializer/deserializer (SERDES) lanes that are programmable in terms of lane speed and number of lanes to enable application flexibility.

A serial peripheral interface (SPI) can configure the AD9161/AD9162 and monitor the status of all registers. The AD9161/AD9162 are offered in an 165-ball, 8.0 mm × 8.0 mm, 0.5 mm pitch, CSP_BGA package and in an 169-ball, 11 mm × 11 mm, 0.8 mm pitch, CSP_BGA package, including a leaded ball option for the AD9162.

Product Highlights

  1. High dynamic range and signal reconstruction bandwidth supports RF signal synthesis of up to 7.5 GHz.
  2. Up to eight lanes JESD204B SERDES interface flexible in terms of number of lanes and lane speed.
  3. Bandwidth and dynamic range to meet DOCSIS 3.1 compliance with margin.

Applications

  • Broadband communications systems
    • DOCSIS 3.1 cable modem termination system (CMTS)/video on demand (VOD)/edge quadrature amplitude modulation (EQAM)
  • Wireless communications infrastructure
    • W-CDMA, LTE, LTE-A, point to point
  • Instrumentation, automatic test equipment (ATE)
  • Radars and jammers
Part Models 2
1ku List Price Starting From $114.28

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Documentation

Documentation

Part Model Pin/Package Drawing Documentation CAD Symbols, Footprints, and 3D Models
AD9161BBCZ
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  • HTML
AD9161BBCZRL
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Software & Part Ecosystem

Software & Part Ecosystem

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Evaluation Kit

Evaluation Kits 3

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EVAL-AD916X

AD9161/AD9162/AD9163/AD9164 Evaluation Board

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EVAL-AD916X

AD9161/AD9162/AD9163/AD9164 Evaluation Board

AD9161/AD9162/AD9163/AD9164 Evaluation Board

Features and Benefits

  • Full featured evaluation board for the AD9161, AD9162, AD9163, and AD9164
  • ACE software for control
  • Direct clocking vs. on-board clocking
  • Showing RF modes of the DAC, including mixed mode and 2× NRZ
  • NCO only mode
  • JESD204B interface mode

Product Detail

This user guide is for the AD9161, AD9162, AD9163, and AD9164 evaluation board. The evaluation board connects to an ADS7-V2EBZ pattern generator for quick evaluation of the AD9161, AD9162, AD9163, and AD9164, high speed, RF digital-to-analog converters (RF DACs). The ADS7-V2EBZ automatically formats the data and sends it to the evaluation board, which simplifies evaluation of the device. The evaluation board runs from the FPGA mezzanine card (FMC) power supply.

The evaluation board includes a clock buffer, the AD9508, which provides the reference clock and SYSREF± pins to the ADS7-V2EBZ, and the SYSREF± pins signal to the DAC.

The evaluation board can be driven by an external clock or the on-board clock (ADF4355). There is a single-pole, double throw (SPDT) switch on the board for selecting the clock source.

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ADS8-V1EBZ

ADS8-V1 Evaluation Board

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ADS8-V1EBZ

ADS8-V1 Evaluation Board

ADS8-V1 Evaluation Board

Features and Benefits

  • Xilinx Kintex Ultrascale XCKU040-3FFVA1156E FPGA.
  • One (1) FMC+ connector.
  • Twenty (20) 16Gbps transceivers supported by one (1) FMC+ connector.
  • DDR4 SDRAM.
  • Simple USB 3.0 port interface.

Product Detail

When connected to a specified Analog Devices high speed adc evaluation board, the ADS8-V1 works as a data acquistion board. Designed to support the highest speed JESD204B A/D Converters, the FPGA on the ADS8-V1 acts as the data receiver, while the ADC is the data transmitter.

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ADS7-V2EBZ

FPGA Based Data Capture Kit

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ADS7-V2EBZ

FPGA Based Data Capture Kit

FPGA Based Data Capture Kit

Features and Benefits

  • Based on Virtex-7 FPGA 
  • One (1) FMC-HPC connector 
  • Ten (10) 13.1 Gbps transceivers supported 
  • Two (2) DDR3-1866 DIMMs 
  • Simple USB port interface (2.0)



Product Detail

The ADS7-V2 Evaluation Board was developed to support the evaluation of Analog Devices high speed A/D converters, D/A converters and Transceivers with JESD204B bit rates up to 13.1 Gbps. The Quick Start Wiki site listed below provides a high level overview of the platform. In addition, each use case of the board has its own section (e.g. Using the ADS7-V2 for High Speed A/D Converter Evaluation). The ADS7-V2 is intended to be used only with specified Analog Devices Evaluation Boards. The ADS7-V2 is not intended to be used as a development platform, and no support is available for standalone operation. Please refer to Xilinx and its approved distributors for FPGA Development Kits
Tools & Simulations

Tools & Simulations 6

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