ADI Clocks: Optimizing and Supporting JESD204B Interfaces
Clock jitter attenuators are designed to support the JESD204B serial interface standard for connecting high-speed data converters and field-programmable gate arrays (FPGAs) operating in base station designs. The JESD204B interface was specifically developed to address high-data rate system design needs, ADI's clock jitter attenuators contain the functions that support and enhance the unique capabilities of that interface standard.
Senior Marketing Manager, High Speed DDS Portfolio
Jeff Keip is the senior marketing manager in charge of the high speed DDS portfolio at Analog Devices. He has been responsible for product definition and roadmap planning for the high speed DDS products at Analog Devices for over 9 years. He holds a BSEE from the University of California at Davis, and is the primary inventor of the programmable modulus function for DDS.
Product Line Director
Tunc Cenger is Product Line Director, Frequency Generation and High Data Rate at Analog Devices. He has over 15 years experience in the semiconductor industry, graduated with a BSEE from Istanbul Technical University and has one patent.