Frequently Asked Question
Why don't you spec psrr and cmrr in the datasheet?
PSRR and CMRR is meaningful and well understood in the case of an op amp. However, its meaning for a clock chip is much less clearly stated, so we do not spec these for our clock devices. As stated in the data sheets, the power supply voltage must be kept within 5% of the nominal voltage (3.3V) in order to meet the data sheet specs. We don't specify a small signal noise limit on the power supply. Rather, we indicate that good power supply design and bypassing is assumed.
It is important that power supplies be as quiet as practicable. At the clock device, power supply pins should be well bypassed by adequate capacitors of low ESR, as near to the power supply pins as possible. It is possible that high frequency noise on the power supply pins could show up on the output if the power supply pins are inadequately bypassed. Also, any noise on the common ground can affect all of the circuits on a board, and can couple to the outputs. Therefore, it is important to follow good layout and bypassing practice on all of the circuits on the board to minimize the injection of noise into the common ground.
ADI clocking devices feature differential inputs and outputs (LVPECL and LVDS, but not CMOS). The conscientious use of differential paths greatly reduces the susceptibility to any common-mode noise.