Frequently Asked Question
Why is my phase noise shape changing when I change the PLL settings?
A PLL is a closed-loop feedback system, and as such should be designed to be stable under a certain set of operating condition. Any change in the loop parameters that effects the closed loop bandwidth will change the shape of the phase noise.
Frequently, the loop is designed to be stable by specifying the desired closed loop bandwidth and phase margin, a method supported by ADIsimCLK. When the loop filter is designed for the PLL, the user specifies the charge pump current, PFD frequency and VCO Kvco in order to get a stable design. If the user changes any of the PLL settings that affect these terms, then they are actually changing the closed loop bandwidth of the PLL and the phase margin.
Assuming the loop was designed with sufficient phase margin, small changes in loop parameters usually just result in small changes in the closed loop bandwidth, and hence the shape of the phase noise, without making the loop become unstable (however the user should make sure their design is actually sufficiently stable for these new setting by examining the loop's stability using ADIsimCLK or another PLL design tool). Large changes in loop parameters will result in drastic changes in the loop bandwidth or make the entire loop unlockable. Both of these will change the shape of the phase noise.