Education Library

Frequently Asked Question

What is the fine delay adjust which is available on certain LVDS/CMOS outputs?

The fine delay adjust is provided as a way to set a variable delay on that particular output with respect to another output or outputs. It is set up by selecting an appropriate full-scale delay, and then selecting a fraction of that full-scale as the actual delay.

The fine delay adjust is implemented in an analog block, which uses a programmable current and a selectable number of capacitors, to create a voltage ramp. When integrated by the capacitor(s), the current will create a voltage which increases linearly with time (a voltage ramp). The higher the current, the faster the voltage will increase. The more capacitors selected, the slower the voltage will increase. By selecting an appropriate current value, and number of capacitors, a ramp with a desired voltage-vs-time ramp is created. This sets the full-scale delay time.

When a fine delay is selected for a given clock output, that output is held until the fine delay period is completed. A delay period begins when an input clock edge triggers the current generator, beginning the voltage ramp. The voltage ramp is then applied to one input of a comparator. A 5-bit DAC creates the other input for the comparator. When the ramp voltage equals the DAC voltage, the delay is terminated, allowing the clock to continue. Therefore the voltage output of the DAC sets the actual time delay, which is a fraction of the full-scale delay. At the end of the delay, the capacitors are discharged and the current source is turned off. The cycle begins again.

The mode of operation of the fine delay block also sets a restriction on the amount of delay which can be obtained. In general a delay of up to one-half of the output clock period is achievable. Also, there is a maximum input clock frequency at which the delay block will no longer reliably reset and allow another trigger. This maximum frequency of the input clock is between 450 and 500 MHz. When this maximum frequency is exceeded the clock output will stop toggling.