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Frequently Asked Question

What is the best way to terminate LVPECL outputs to get lowest jitter?

The data sheets for the ADI clock ICs show both a load resistor with AC-coupled termination, and the "traditional" Thevenin termination scheme for LVPECL. There seems to be little difference between the two termination methods in jitter performance; layout and other considerations are more important. Both termination schemes are capable of giving the same jitter performance when all other factors are considered.