Frequently Asked Question
Is there an advantage to running a higher VCO frequency than the output frequency?
Yes. As a clock input signal traverses the switching region of an input stage, random noise in the input stage adds time jitter to the signal as it is passed along to subsequent stages. A signal which traverses this switching region faster (has higher slew rate) is less affected by the random noise, resulting in less added time jitter, and lower jitter at the clock outputs. For a signal of the same amplitude, a higher frequency signal has a higher (faster) slew rate, and therefore can result in lower time jitter through the clock distribution system.
Any jitter added at the input to a clock distribution system cannot be reduced by subsequent division of the clock frequency (phase noise does reduce with division, but not jitter). So, the jitter should be reduced as much as possible at the input.
This means that in principle there is an advantage to running the VCO at a higher frequency than that required at the clock outputs.