Frequently Asked Question
If I change the level of PECL output, does it affect the jitter?
Yes, the slew rate of a clock signal can affect jitter. The amount of jitter due to an input stage (receiver) is reduced by a faster slew rate at the input.
A higher amplitude (signal voltage swing) can result in a faster slew rate. The amplitude of the AD9510/11/12 LVPECL outputs can be selected as 810 mV, 660 mV, 500 mV, or 340 mV. The default swing is the highest, 810 mV. This swing gives the highest slew rate, and therefore should result in the lowest jitter. Setting the LVPECL output swing to a lower amplitude will not improve the jitter.