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Frequently Asked Question

How does the clock clean-up function of the AD951x parts work?

The AD9510 and AD9511 include an on-chip PLL core which requires an external VCO or VCXO and a loop filter to configure a PLL loop. This PLL loop can be used to considerably clean up a reference clock signal which has picked up noise as it has been distributed. This has the effect of reducing the phase noise and time jitter on a noisy clock reference.

The PLL loop must be designed around the PLL core characteristics and the selected VCO/VCXO. Often, the VCO/VCXO frequency is higher by some integer multiplier (N) than the reference clock frequency. A suitable loop bandwidth must be selected in order to design the loop filter.

The noise on the reference clock signal will be suppressed outside the PLL loop bandwidth. However, the noise on the reference within the loop bandwidth will be gained up by the ratio 20*log(N), where N is the frequency multiplier of the loop. The amount of cleanup that can be achieved depends on both the narrowness of the loop bandwidth and on the frequency multiplication. The stability of the loop and the settling time of the loop, as well as the practicality of the component values of the loop filter, are also affected by the loop bandwidth.

Outside of the loop bandwidth, the VCO/VCXO phase noise will predominate. So, it is important to select a VCO/VCXO with low broadband phase noise. As with all engineering tasks, a suitable compromise among all of the factors involved must be achieved. A good clock reference cleanup design can result in significant system performance improvements. The locally distributed clock time jitter can often be reduced to the order of 1 ps rms or better.

Remember that ADIsimCLK can help you design your PLL loop, and simulate its performance.