Frequently Asked Question
Can the REF CLK be gated on and off?
In general, yes. This is a valid “sleep” strategy. Gating off the REF CLK between operating periods will significantly reduce the idling current. The DDS logic is CMOS, and when it is not clocking, the current is greatly reduced. On the AD9858 (because the DAC is implemented in bipolar), the analog bias currents do not reduce when the reference clock is gated off. Some DDSes also provide power-down modes where different sections of the DDS can be powered down—please refer to the specific device data sheet.