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Frequently Asked Question

Can I gate the REF CLK on and off?

Yes. This is a valid "sleep" strategy. Gating off the REF CLK between operating periods will significantly reduce the idling current.

The DDS logic is CMOS, and when it is not clocking, the current is greatly reduced. On the AD9858 (because the DAC is implemented in bipolar), the analog bias currents do not reduce when the ref clock is gated off.