Design & Integration Files
- Bill of Materials
- Gerber Files
- Assembly Drawing
Part Numbers with "Z" indicate RoHS Compliance. Boards checked are needed to evaluate this circuit.
- EVAL-CN0227-HSCZ ($385.00) High Performance, 16-Bit, 250 MSPS Wideband Receiver with Antialiasing Filter
- HSC-ADC-EVALCZ ($837.94) High Speed Eval Control Board
Features & Benefits
- 16-Bit, 250MSPS Wideband Reciever
- Antialiasing Filter
- 72dB SNR @ 120MHz Input
- 82dB SFDR @ 120MHz Input
Markets and Technologies
Circuit Function & Benefits
The third-order Butterworth antialiasing filter is optimized based on the performance and interface requirements of the amplifier and ADC. The total insertion loss due to the filter network and other components is only 1.8 dB.
The overall circuit has a bandwidth of 152 MHz with a pass band flatness of 1 dB. The SNR and SFDR measured with a 120 MHz analog input are 72.6 dBFS and 82.2 dBc, respectively.
The circuit accepts a single-ended input and converts it to differential using a wide bandwidth (3 GHz) M/A-COM ECT1- 1-13M 1:1 transformer. The ADL5562 3.3 GHz differential amplifier has a differential input impedance of 400 Ω when operating at a gain of 6 dB and 200 Ω when operating at a gain of 12 dB. A gain option of 15.5 dB is also available.
The ADL5562 is an ideal driver for the AD9467, and the fully differential architecture through the low-pass filter and into the ADC provides good high frequency common-mode rejection, as well as minimizes second-order distortion products. The ADL5562 provides a gain of 6 dB or 12 dB depending on the input connection. In the circuit, a gain of 6 dB was used to compensate for the insertion loss of the filter network and transformer (approximately 1.8 dB), providing an overall signal gain of 3.9 dB. An input signal of +6.0 dBm produces a full-scale 2 V p-p differential signal at the ADC input.
The antialiasing filter is a third-order Butterworth filter designed with a standard filter design program. A Butterworth filter was chosen because of its flat response within the pass band. A third order filter yields an ac noise bandwidth ratio of 1.05 and can be designed with the aid of several free filter programs such as Nuhertz Technologies Filter Free (www.nuhertz/filter), or the Quite Universal Circuit Simulator (Qucs) Free Simulation (www.qucs.sourceforge.net).
In order to achieve best performance, the ADL5562 should be loaded with a net differential load of 200 Ω. The 15 Ω series resistors isolate the filter capacitance from the amplifier output, and the 243 Ω resistors in parallel with the downstream impedance yield a net load impedance of 203 Ω when added to the 30 Ω series resistance.
The 20 Ω resistors in series with the ADC inputs isolate internal switching transients from the filter and the amplifier. The 511 Ω resistor in parallel with the ADC serves to reduce the input impedance of the ADC for more predictable performance.
The third-order Butterworth filter was designed with a source impedance of 38.6 Ω, a load impedance of 269 Ω, and a 3 dB bandwidth of 180 MHz. The calculated values from the program are shown in Figure 1. The values chosen for the filter passive components were the closest standard values to those generated by the program.
The internal 3.5 pF capacitance of the ADC was subtracted from the value of the second shunt capacitor to yield a value of 32.29 pF. In the circuit, this capacitor was realized using two 62 pF capacitors connected to ground as shown in Figure 1. This provides the same filtering effect and offers some ac common-mode rejection.
The measured performance of the system is summarized in Table 1, where the 3 dB bandwidth is 152 MHz. The total insertion loss of the network is approximately 2 dB. The bandwidth response is shown in Figure 3; the SNR and SFDR performance are shown in Figure 4.
|Performance Specs @ 2 V p-p FS||Final Results|
|Cutoff Frequency (-3 dB)||152 MHz|
|Pass-Band Flatness (6 MHz to 125 Mhz)||1 dB|
|SNRF @ 120 MHz||72.6 dBFS|
|SFDR @ 120 MHz||82.2 dBc|
|H2/H3 @ 120 MHz||86.6 dBc/82.2 dBc|
|Overall Gain @ 10 MHz||3.9 dB|
|Input Drive @ 10 MHz||6.0 dBm|
Filter and Interface Design Procedure
In this section, a general approach to the design of the amplifier/ADC interface with filter is presented. In order to achieve optimum performance (bandwidth, SNR, SFDR, etc.), there are certain design constraints placed on the general circuit by the amplifier and the ADC:
- The amplifier should see the correct dc load recommended by the data sheet for optimum performance.
- The correct amount of series resistance must be used between the amplifier and the load presented by the filter. This is to prevent undesired peaking in the pass band.
- The input to the ADC should be reduced by an external parallel resistor, and the correct series resistance should be used to isolate the ADC from the filter. This series resistor also reduces peaking.
The generalized circuit shown in Figure 5 applies to most high speed differential amplifier/ADC interfaces and will be used as a basis for the discussion. This design approach will tend to minimize the insertion loss of the filter by taking advantage of the relatively high input impedance of most high speed ADCs and the relatively low impedance of the driving source (amplifier).
The basic design process is as follows:
- Select the external ADC termination resistor RTADC so that the parallel combination of RTADC and RADC is between 200 Ω and 400 Ω.
- Select RKB based on experience and/or the ADC data sheet recommendations, typically between 5 Ω and 36 Ω.
- Calculate the filter load impedance using:
ZAAFL = RTADC || (RADC + 2RKB)
- Select the amplifier external series resistor RA. Make RA less than 10 Ω if the amplifier differential output impedance is 100 Ω to 200 Ω. Make RA between 5 Ω and 36 Ω if the output impedance of the amplifier is 12 Ω or less.
- Select RTAMP so that the total load seen by the amplifier,
ZAL, is optimum for the particular differential
amplifier chosen using the equation:
ZAL = 2RA + (ZAAFL || 2RTAMP).
- Calculate the filter source resistance:
ZAAFS = 2RTAMP || (ZO + 2RA).
- Using a filter design program or tables design the filter using the source and load impedances, ZAAFS and ZAAFL, type of filter, bandwidth, order, etc. Use a bandwidth that is about 40% higher than one-half the sampling rate to ensure flatness in the frequency span between dc and fs/2.
- The internal ADC capacitance, CADC, should be
subtracted from the final shunt capacitor value
generated by the program. The program will give the
value CSHUNT2 for the differential shunt capacitor. The
final common-mode shunt capacitance is
CAAF2 = 2(CSHUNT2 – CADC).
After running these preliminary calculations, the circuit should be given a quick review for the following items.
- The value of CAAF2 should be at least 10 pF so that it is several times larger than CADC. This minimizes the sensitivity of the filter to variations in CADC.
- The ratio of ZAAFL to ZAAFS should not be more than about 7 so that the filter is within the limits of most filter tables and design programs.
- The value of CAAF1 should be at least 5 pF to minimize sensitivity to parasitic capacitance and component variations.
- The inductor, LAAF, should be a reasonable value of at least several nH.
In some cases, the filter design program may provide more than one unique solution, especially with higher order filters. The solution that uses the most reasonable set of component values should always be chosen. Also choose a configuration that ends in a shunt capacitor so that it can be combined with the ADC input capacitance.
Circuit Optimization Techniques and Trade-Offs
The parameters in this interface circuit are very interactive, therefore, it is almost impossible to optimize the circuit for all key specifications (bandwidth, bandwidth flatness, SNR, SFDR, gain, etc.). However, the peaking which often occurs in the bandwidth response can be minimized by varying RA and RKB.
Notice in Figure 6 how the pass-band peaking is reduced as the value of the output series resistance, RA, is increased. However, as the value of this resistance increases, there is more signal attenuation, and the amplifier must drive a larger signal to fill the ADCs full-scale input range.
The value of RA also affects SNR performance. Larger values, while reducing the bandwidth peaking, tend to slightly increase the SNR because of the higher signal level required to drive the ADC full scale.
The RKB series resistor on the ADC inputs should be selected to minimize distortion caused by any residual charge injection from the internal sampling capacitor within the ADC. Increasing this resistor also tends to reduce bandwidth peaking.
However, increasing RKB increases signal attenuation, and the amplifier must drive a larger signal to fill the ADC input range. Another method for optimizing the pass-band flatness is to vary the filter shunt capacitor, CAAF2, by a small amount.
The ADC input termination resistor, RTADC, should normally be selected to make the net ADC input impedance between 200 Ω and 400 Ω. Making it lower reduces the effect of the ADC input capacitance and may stabilize the filter design but increases the insertion loss of the circuit. Increasing the value will also reduce peaking.
Balancing these trade-offs can be somewhat difficult. In this design, each parameter was given equal weight, therefore, the values chosen are representative of the interface performance for all the design characteristics. In some designs different values might be chosen to optimize SFDR, SNR, or input drive level, depending on system requirements.
The SFDR performance in this design is determined by two factors: the amplifier and ADC interface component values as shown in Figure 1, and the setting of the internal front-end buffer bias current in the AD9467 via an internal register. The final SFDR performance numbers shown in Table 1 and Figure 4 were obtained after following the SFDR optimization described in the AD9467 data sheet.
Another trade-off that can be made in this particular design is the ADC full-scale setting. The full-scale ADC differential input voltage was set for 2 V p-p for the data obtained with this design, which optimizes SFDR. Changing the full-scale input range to 2.5 V p-p yields about 1.5 dB improvement in SNR but slightly degrades the SFDR performance. The input range is set by the value loaded into an internal register in the AD9467 as described in the data sheet.
Note that the signal in this design is ac coupled with the 0.1 μF capacitors to block the common-mode voltages between the amplifier, its termination resistors, and the ADC inputs. Please refer to the AD9467 data sheet for further details regarding common-mode voltages.
Passive Component and PC Board Parasitic Considerations
The performance of this or any high speed circuit is highly dependent on proper PCB layout. This includes, but is not limited to, power supply bypassing, controlled impedance lines (where required), component placement, signal routing, and power and ground planes. See Tutorials MT-031 and MT-101 for more detailed information regarding PCB layout for high speed ADCs and amplifiers.
Low parasitic surface-mount capacitors, inductors, and resistors should be used for the passive components in the filter. The inductors chosen are from the Coilcraft 0603CS series. The surface mount capacitors used in the filter are 5%, C0G, 0402- type for stability and accuracy.
See the CN-0227 Design Support Package (www.analog.com/CN0227-DesignSupport) for complete documentation on the system.
For applications that require less bandwidth and lower power, the ADL5561 differential amplifier can be used. The ADL5561 has a bandwidth of 2.9 GHz and only uses 40 mA of current. For even lower power and bandwidth, the ADA4950-1 could also be used. This device has a 1 GHz bandwidth and only uses 10 mA of current. For higher bandwidth, the 6 GHz ADL5565 differential amplifier is pin compatible with the others listed above.
Circuit Evaluation & Test
This circuit uses a modified AD9467-250EBZ circuit board and the HSC-ADC-EVALCZ FPGA-based data capture board. The two boards have mating high speed connectors, allowing for the quick setup and evaluation of the circuit’s performance. The modified AD9467-250EBZ board contains the circuit evaluated as described in this note, and the HSC-ADC-EVALCZ data capture board is used in conjunction with Visual Analog evaluation software, as well as the SPI Controller software to properly control the ADC and capture the data. See User Guide UG-200 for the schematics, BOM, and layout for the AD9467-250EBZ board. The "readme.txt" file in the CN-0227 Design Support Package (www.analog.com/CN0227-DesignSupport) describes the modifications made to the standard AD9467-250EBZ board. Application Note AN-835 contains complete details on how to set up the hardware and software to run the tests described in this circuit note.
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