Software such as C code and/or FPGA code, used to communicate with component's digital interface.
Features & Benefits
- 18-bit accurate voltage output source
- +/- 10V programmable output range
- Less than +/- 0.5 dB INL & DNL all codes
Markets & Technology
- Instrumentation & Measurement
- Industrial Automation Technology (IAT)
Circuit Function & Benefits
Figure 1 shows the AD5781 configured in a gain-of-two mode such that a single reference source can be used to generate a symmetrical bipolar output voltage range. This mode of operation uses an external op amp (A2), as well as on-chip resistors (see AD5781 data sheet) to provide the gain of two. These internal resistors are thermally matched to each other and to the DAC ladder resistance, resulting in ratiometric thermal tracking. The output buffer is again the AD8676, used for its low noise and low drift. This amplifier is also used (A1) to amplify the +5 V reference voltage from the low noise ADR445 to +10 V. R2 and R3 in this gain circuit are precision metal foil resistors with 0.01% tolerance and a temperature coefficient resistance of 0.6 ppm/°C. For optimum performance over temperature, R1 and R2 should be in a single package, such as the Vishay 300144 or VSR144 series. R2 and R3 are selected to be 1 kΩ to keep noise in the system low. R1 and C1 form a low-pass filter with a cutoff frequency of approximately 10 Hz. The purpose of this filter is to attenuate voltage reference noise.
Figure 2. Integral Nonlinearity vs. DAC Code
The precision performance of the circuit shown in Figure 1 is demonstrated in the data in Figure 2 and Figure 3, which show integral nonlinearity and differential nonlinearity as a function of DAC code. As can be seen, both are significantly within the specifications of ±0.5 LSB and ±0.5 LSB, respectively.
The total unadjusted error for the circuit consists of the dc errors combined together—that is, INL error, offset error, and gain error. Figure 4 shows a plot of total unadjusted error as a function of DAC code. The maximum errors occur at DAC code zero and DAC code 262,143. This is expected, and due to the absolute error in the voltage reference output, the mismatch in external resistors R2 and R3 (see Figure 1), and the mismatch in the AD5781 internal resistors RFB and R1 (see Figure 5).
Figure 3. Differential Nonlinearity vs DAC Code
Figure 4. Total Unadjusted Error vs. DAC Code
Figure 5. Internal Gain-of-Two Circuitry (Simplified Schematic)
The specified voltage reference absolute error is 0.04%; the specified mismatch in resistors R2 and R3 in this case is 0.02%; the specified mismatch in internal resistors R1 and RFB is 0.01%. This results in a total gain error of 0.07% of full-scale range, or 184 LSBs. Figure 4 shows the measured value to be 20 LSBs, or 0.007% of full-scale range, indicating that all components are performing significantly better than their specified tolerances.
To be able to realize high precision, the peak-to-peak noise at the circuit output must be maintained below 1 LSB, which is 76.29 μV for 18-bit resolution and a 20 V peak-to-peak voltage range. Figure 6 shows peak-to-peak noise measured in the 0.1 Hz to 10 Hz bandwidth over a period of 10 seconds. The peak-to-peak values for each of the three conditions are 1.34 μV for mid-scale output, 12.92 μV for full-scale output, and 15.02 μV for zero-scale output. Mid-scale output exhibits the lowest noise, as it represents the noise from the DAC core only. The noise contribution from each voltage reference path is attenuated by the DAC when mid-scale code is selected.
Figure 6. Voltage Noise in 0.1 Hz to 10 Hz Bandwidth
A real application, however, will not have a high-pass cutoff at 0.1 Hz to attenuate 1/f noise, but will include frequencies down to dc in its pass band; therefore, the measured peak-to-peak noise will be more realistically shown in Figure 7. In this case, the noise at the output of the circuit was measured over a period of 100 seconds, effectively including frequencies as low as 0.01 Hz in the measurement. The upper frequency cutoff is at approximately 14 Hz and is limited by the measurement setup. For the three conditions shown in Figure 7, the peak-to-peak values are 1.61 μV for mid-scale output, 43.33 μV for full-scale output, and 36.89 μV for zero-scale output. The worst-case peak-to-peak value of 43.33 μV corresponds to approximately ½ LSB.
Figure 7. Voltage Noise Measured Over 100 Second Period
As the time period over which the measurement is taken is increased, lower frequencies will be included, and the peak-to-peak value will increase. At low frequencies, temperature drift and thermocouple effects become contributors to noise. These effects can be minimized by choosing components with low thermal coefficients. In this circuit, the main contributor to low frequency 1/f noise is the voltage reference. It also exhibits the greatest temperature coefficient value in the circuit of 3 ppm/°C.
Circuit Evaluation & Test
|AD8676||Ultra Precision, 36 V, 2.8 nV/√Hz Dual RRO Op Amp||
|AD5781||True 18-Bit, Voltage Output DAC ±0.5 LSB INL, ±0.5 LSB DNL||
|ADR445||Ultralow Noise, LDO XFET® 5.0V Voltage Reference w/Current Sink and Source||