Design & Integration Files
- Bill of Materials
- Assembly Drawing
Part Numbers with "Z" indicate RoHS Compliance. Boards checked are needed to evaluate this circuit
- EVAL-ADF4350EB1Z ($175.00) ADF4350 evaluation board used to evaluate this circuit. Please see "Circuit Evaluation & Test" section for set up information.
Software such as C code and/or FPGA code, used to communicate with component's digital interface.
Features & Benefits
- Direct conversion broadband transmitter
- Functions from 69 MHz to 2.2 GHz
Markets and Technologies
Circuit Function & Benefits
This circuit is a complete implementation of the analog portion of a broadband direct conversion transmitter (analog baseband in, RF out). RF frequencies from 68.75 MHz to 2.2 GHz are supported through the use of a PLL with a broadband integrated voltage controlled oscillator (VCO). Unlike modulators that use a divide-by-1 LO stage (as described in CN-0134), harmonic filtering of the LO is not required.
To achieve optimum performance, the only requirement is that the LO inputs of the modulator be driven differentially. The ADF4350 provides differential RF outputs and is, therefore, an excellent match. This PLL-to-modulator interface is applicable to all I/Q modulators and I/Q demodulators that contain a 2XLO-based phase splitter. Low noise LDOs ensure that the power management scheme has no adverse impact on phase noise and error vector magnitude (EVM). This combination of components represents industry-leading direct conversion transmitter performance over a frequency range of 68.75 MHz to 2.2 GHz. For frequencies above 2.2 GHz, it is recommended to use a divide-by-1 modulator, as described in CN-0134.
The circuit shown in Figure 1 uses the ADF4350, a fully integrated fractional-N PLL IC, and the ADL5385 wideband transmit modulator.
The ADF4350 provides the local oscillator (the LO is twice the modulator RF output frequency) signal for the ADL5385 transmit quadrature modulator, which upconverts analog I/Q signals to RF. Taken together, the two devices provide a wideband baseband I/Q-to-RF transmit solution.
The ADF4350 is powered off the ultralow noise 3.3 V ADP150 regulator for optimal LO phase noise performance. The ADL5385 is powered off a 5 V ADP3334 LDO. The ADP150 LDO has an output voltage noise of only 9 μV rms, integrated from 10 Hz to 100 kHz, and helps to optimize VCO phase noise and reduce the impact of VCO pushing (equivalent to power supply rejection). See CN-0147 for more details on powering the ADF4350 with the ADP150 LDO.
The ADL5385 uses a divide-by-2 block to generate the quadrature LO signals. The quadrature accuracy is, thus, dependent on the duty cycle accuracy of the incoming LO signal (as well as the matching of the internal divider flip-flops). Any imbalance in the rise and fall times causes even order harmonics to appear, as evident on the ADF4350 RF outputs. When driving the modulator LO inputs differentially, even-order cancellation of harmonics is achieved, improving the overall quadrature generation. (See “Wideband A/D Converter Front-End Design Considerations: When to Use a Double Transformer Configuration.” Rob Reeder and Ramya Ramachandran. Analog Dialogue, 40-07.)
Because sideband suppression performance is dependent on the modulator quadrature accuracy, better sideband suppression is achievable when driving the LO input ports differentially vs. single-ended. The ADF4350 has differential RF outputs compared to a single-ended output available on most competitor PLL devices with integrated VCO.
The ADF4350 output match consists of the ZBIAS pull-up and, to a lesser extent, the decoupling capacitors on the supply node. To get a broadband match, it is recommended to use either a resistive load (ZBIAS= 50 Ω) or a resistive in parallel with a reactive load for ZBIAS. The latter gives slightly higher output power, depending on the inductor chosen. An inductor value of 19 nH or greater should be used for LO operation below 1 GHz. The measured results in this circuit were performed using ZBIAS = 50 Ω and an output power setting of +5 dBm. When using the 50 Ω resistor, this setting gives approximately 0 dBm on each output across the full band, or +3 dBm differentially. The ADL5385 LO input drive level specification is −10 dBm to +5 dBm; therefore, it should be possible to reduce the ADF4350 output power to save current.
A sweep of sideband suppression versus RF output frequency is shown in Figure 2. In this sweep, the test conditions were as follows: baseband I/Q amplitude = 1.4 V p-p differential sine waves in quadrature with a 500 mV dc bias; baseband I/Q frequency (fBB) = 1 MHz; LO = 2 × RFOUT. A simplified diagram of the test setup is shown in Figure 3. A modified ADL5385 evaluation board was used because the standard ADL5385 board does not allow a differential LO input drive.
This circuit achieves comparable or improved sideband suppression performance when compared to driving the ADL5385 with a low noise RF signal generator, as used in the data sheet measurement. Using the differential RF outputs of the ADF4350 provides even-order harmonic cancellation and improves modulator quadrature accuracy. This impacts sideband suppression performance and EVM (error vector magnitude). A single carrier W-CDMA composite EVM of better than 2% was measured with the circuit shown in Figure 1. The solution thus provides a low EVM broadband solution for frequencies from 68.75 MHz to 2.2 GHz. For frequencies above 2.2 GHz, a divide-by-1 modulator block should be used, as described in CN-0134.
A complete design support package for this circuit note can be found at http://www.analog.com/CN0144-DesignSupport.
The PLL-to-modulator interface described in this circuit note is applicable to all I/Q modulators that contain a 2XLO-based phase splitter. It is also applicable to 2XLO-based I/Q demodulators such as the ADL5387.
Circuit Evaluation & Test
Circuit note CN-0144 uses the EVAL-ADF4350EB1Z and the ADL5385-EVALZ boards for evaluation of the described circuit, allowing for quick setup and evaluation. The EVAL-ADF4350EB1Z board uses the standard ADF4350 programming software, contained on the CD that accompanies the evaluation board.
Windows® XP, Windows Vista (32-bit), or Windows 7 (32-bit) PC with USB Port, the ADF4350EB1Z, and the ADL5385-EVALZ circuit evaluation boards, the ADF4350 programming software, power supplies, I-Q signal source, such as a Rhode & Schwarz AMIQ, and a spectrum analyzer. See this circuit note and the UG-109 user guide for evaluation board EVAL-ADF435EB1Z and the ADF4350 and ADL5385 data sheets.
This circuit note contains a description of the circuit, the schematic, and a block diagram of the test setup. The user guide UG-109 details the installation and use of the EVAL-ADF4350 evaluation software. UG-109 also contains board setup instructions and the board schematic, layout, and bill of materials. The ADL5385-EVALZ board schematic, block diagram, bill of materials, layout and assembly information is included in the ADL5385 data sheet. See the ADF4350 and ADL5385 data sheet for device information.
Functional Block Diagram
Circuit note CN-0144 contains the function block diagram of the described test setup in Figure 3.
Setup and Test
After setting up the equipment, standard RF test methods should be used to measure the sideband suppression of the circuit.
Further Improvements with Filtering
The sideband suppression of this circuit can be further improved by filtering the LO signal before the LOIP and LOIN pins of the ADL5385. Filtering attenuates harmonic levels so as to minimize errors in the quadrature generation block of the ADL5385. At some frequencies, this can result in improvements over 10 dB. However, using a filter will limit the bandwidth of the circuit. See Figure 4 for narrowband results.
The LO signal was passed through a low-pass filter with a 3 dB point at approximately 2600 MHz. This results in a usable output frequency up to approximately 1300 MHz.
|ADL5385||30 MHz TO 2200 MHz Quadrature Modulator||
|ADP3334||High Accuracy Low IQ, 500 mA anyCAP® Adjustable Low Dropout Regulator||
|ADF4350||Wideband Synthesizer with Integrated VCO||
|ADP150||Ultralow Noise, 150 mA CMOS Linear Regulator||