Features and Benefits
- Transport Stream: Raw DTS bit stream
- Output Status: Number of output channels, number of output samples per channel and output channel ordering
- API: C callable 'Push' API
- Error Codes: Reports up to 3 unique error codes.
- Compliance: DTS certification
- Code base origin: DTS Coherent acoustics
- Reference Code Revision #: V2.30.20
- Certification: Certified on ADSP-BF527/533/537/548
- Framework dependencies: None. No dependencies on processor peripherals or registers.
- Release Format: Object Code with source code wrapper
- Input format: Supports core decoding of all DTS encoded bitstreams.
- Output format: Supports up to 5.1 channels (5 Full bandwidth and 1 Low frequency effects), 16-bit or 24-bit PCM audio. The output configurations decide the order of channel placement.
- Output buffer samples per block: 256 Samples
- Sample Rate: All sampling frequencies specified for DTS core decoder (i.e. 8, 11.025, 12, 16, 22.05, 24, 32, 44.1 and 48kHz )
- Multi-channel: Fully re-entrant and multi-instancing capable
The DTS® technology, derived from the name Digital Theatre Systems, was initially focused on providing high fidelity, full bandwidth, and multi channel surround sound experience in theatres. The DTS 5.1 encoder efficiently encodes and reduces the demand on storage requirements while maintaining high fidelity multi-channel audio. With advancing technology, today it has become a de-facto for all ranges of consumer products such as DVD players, etc.
The DTS 5.1 decoder implementation has been highly optimised to run on the Analog Devices' Blackfin processor family. It is a self-contained software module that is fully compliant with DTS 5.1 specification and rigorously tested & demonstrated in real time environment. The ADI implementation has been certified by DTS Inc.
It contains a standard C-callable 'push' API with the added flexibility of using 'pull' (or 'poll') by adding light 'wrapper' code. The code has been implemented using Instruction and Data cache and has no dependencies on processor peripherals or registers. The module comes along with a light wrapper API which enables block approach for integration to overall framework. This makes system integration much easier.
| Code memory (KiB)
||Data RAM (KiB)
||Constant Data Tables (KiB)
|| MIPS Average
- MIPS measured using Fs = 48kHz, optimal memory layout, worst case test vector, running on a ADSP-BF533.
- Code compatible across all BF5xx processors, with silicon anomaly workarounds implemented based on ADSP-BF533 Silicon Revision 0.3 and later, ADSP-BF537 Silicon Revision 0.3 and ADSP-BF561 Silicon Revision 0.4 and later.
- "Data RAM" for one instance, includes Stack, Scratch, Instance/State, Minimum Input and Output Single Buffers.
- Input buffer size is 2K bytes and output buffer size is 6K bytes
- Windows XP Professional SP3 (32-bit only).
- Windows Vista Business/Enterprise/Ultimate SP2 (32-bit only). It is recommended to install the software in a non-UAC-protected location.
- Windows 7 Professional/Enterprise/Ultimate (32 and 64-bit). It is recommended to install the software in a non-UAC-protected location.
- Minimum of 2 GHz single core processor, 3.3 GHz dual core is recommended.
- Minimum of 1 GB memory (RAM), 4 GB is recommended.
- Minimum of 2 GB hard disk (HDD) space is required.