Wideband RF Signal Processing
The ADI portfolio of wideband RF data acquisition and signal processing components, signal chains, and platform modules, contain the industry's highest-performing solutions for digitizing DC - 2+ GHz wideband RF signals for a variety of high-performance and demanding applications, such as RF instrumentation, defense electronics, and communications infrastructure. ADI offers FMC modules containing complete wideband RF signal chains in various configurations and including HDL operating software and device drivers for seamless connectivity and rapid system prototyping within the Xilinx FPGA development platform ecosystem.
The AD9144 is a quad, 16-bit, high dynamic range digital-to-analog converter (DAC) that provides a maximum sample rate of 2.8 GSPS, permitting a multicarrier generation up to the Nyquist frequency. The DAC outputs are optimized to interface seamlessly with the ADRF6720 analog quadrature modulator (AQM) from Analog Devices, Inc. An optional 3-wire or 4-wire serial port interface (SPI) provides for programming/readback of many internal parameters. Full-scale output current can be programmed over a typical range of 13.9 mA to 27.0 mA. The AD9144 is available in an 88-lead LFCSP.
- Greater than 1 GHz, ultrawide complex signal bandwidth enables emerging wideband and multiband wireless applications.
- Advanced low spurious and distortion design techniques provide high quality synthesis of wideband signals from baseband to high intermediate frequencies.
- JESD204B Subclass 1 support simplifies multichip synchronization in software and hardware design.
- Fewer pins for data interface width with serializer/ deserializer (SERDES) JESD204B eight-lane interface.
- Programmable transmit enable function allows easy design balance between power consumption and wake-up time.
- Small package size with 12 mm × 12 mm footprint.
- Wireless communications
3G/4G W-CDMA base stations
Software defined radios
- Wideband communications
Local multipoint distribution service (LMDS) and multichannel multipoint distribution service (MMDS)
- Transmit diversity, multiple input/multiple output (MIMO)
- Automated test equipment
The AD9625 is a 12-bit monolithic sampling analog-to-digital converter (ADC) that operates at conversion rates of up to 2.6 giga samples per second (GSPS). This product is designed for sampling wide bandwidth analog signals up to the second Nyquist zone. The combination of wide input bandwidth, high sampling rate, and excellent linearity of the AD9625 is ideally suited for spectrum analyzers, data acquisition systems, and a wide assortment of military electronics applications, such as radar and jamming/antijamming measures.
The analog input, clock, and SYSREF± signals are differential inputs. The JESD204B-based high speed serialized output is configurable in a variety of one-, two-, four-, six-, or eight-lane configurations. The product is specified over the industrial temperature range of −40°C to +85°C.
- High performance: exceptional SFDR in high sample rate applications, direct RF sampling, and on-chip reference.
- Flexible digital data output formats based on the JESD204B specification.
- Control path SPI interface port that supports various product features and functions, such as data formatting, gain, and offset calibration values.
- Spectrum analyzers
- Military communications
- High performance digital storage oscilloscopes
- Active jamming/antijamming
- Electronic surveillance and countermeasures
The AD9680 is a dual, 14-bit, 1.25 GSPS/1 GSPS/820 MSPS/ 500 MSPS analog-to-digital converter (ADC). The device has an on-chip buffer and sample-and-hold circuit designed for low power, small size, and ease of use. This device is designed for sampling wide bandwidth analog signals of up to 2 GHz. The AD9680 is optimized for wide input bandwidth, high sampling rate, excellent linearity, and low power in a small package.
The dual ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations.
The analog input and clock signals are differential inputs. Each ADC data output is internally connected to two digital downconverters (DDCs). Each DDC consists of up to five cascaded signal processing stages: a 12-bit frequency translator (NCO), and four half-band decimation filters. The DDCs are bypassed by default.
In addition to the DDC blocks, the AD9680 has several functions that simplify the automatic gain control (AGC) function in the communications receiver. The programmable threshold detector allows monitoring of the incoming signal power using the fast detect output bits of the ADC. If the input signal level exceeds the programmable threshold, the fast detect indicator goes high. Because this threshold indicator has low latency, the user can quickly turn down the system gain to avoid an overrange condition at the ADC input.
Users can configure the Subclass 1 JESD204B-based high speed serialized output in a variety of one-, two-, or four-lane configurations, depending on the DDC configuration and the acceptable lane rate of the receiving logic device. Multiple device synchronization is supported through the SYSREF± and SYNCINB± input pins.
The AD9680 has flexible power-down options that allow significant power savings when desired. All of these features can be programmed using a 1.8 V to 3.3 V capable, 3-wire SPI.
The AD9680 is available in a Pb-free, 64-lead LFCSP and is specified over the −40°C to +85°C industrial temperature range. This product is protected by a U.S. patent.
- Wide full power bandwidth supports IF sampling of signals up to 2 GHz.
- Buffered inputs with programmable input termination eases filter design and implementation.
- Four integrated wideband decimation filters and numerically controlled oscillator (NCO) blocks supporting multiband receivers.
- Flexible serial port interface (SPI) controls various product features and functions to meet specific system requirements.
- Programmable fast overrange detection.
- 9 mm × 9 mm, 64-lead LFCSP.
- Diversity multiband, multimode digital receivers 3G/4G, TD-SCDMA, W-CDMA, GSM, LTE
- General-purpose software radios
- Ultrawideband satellite receivers
- Signals intelligence (SIGINT)
- DOCSIS 3.0 CMTS upstream receive paths
- HFC digital reverse path receivers
- New AN-1353: How to Bypass VCO Calibration for the ADF4355-2, ADF4355, ADF4355-3, ADF4356, ADF5355, and ADF5356 (Rev. D) PDF
- AN-1396: How to Predict the Frequency and Magnitude of the Primary Phase Truncation Spur in the Output Spectrum of a Direct Digital Synthesizer (DDS) (Rev. 0) PDF
- AN-1390: Manual Band Selection for PLL Lock Time Reduction (Rev. 0) PDF
- AN-756: Sampled Systems and the Effects of Clock Phase Noise and Jitter (Rev. 0) PDF