Interactive Signal Chains
The circuit block diagram shown in Figure 1 is a low phase noise translation loop synthesizer (also known as an offset loop). This circuit translates the lower 100 MHz reference frequency of the ADF4002 phase locked loop (PLL) up to a higher frequency range of 5.0 GHz to 5.4 GHz, as determined by the frequency of the local oscillator (LO).
The translation loop synthesizer has very low phase noise (<50 fs) in contrast to a synthesizer using only a PLL. The low phase noise is because of the very low N value used by the ADF4002 integer-N PLL, which controls the voltage controlled oscillator (VCO). In this example, the ADF4002 phase frequency detector (PFD) runs at 100 MHz, and N = 1, yielding phase noise performance that is not limited by the N value of the PLL.
Applicable PartsView All
Data SheetsShow More..
Technical Articles PageShow More..
Product Selection Guide
Single Event Effects Radiation ReportsShow More..
Low Dose Rate Radiation ReportsShow More..
High Dose Rate Radiation ReportsShow More..
Solutions Bulletins & BrochuresShow More..
Three Ways to Stay Connected
Contact the ADI Sales Team
EZ Support Community
Subscribe to an eNewsletter